diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd
index f8ad262..605f21a 100644
--- a/lib/CPUs/MIPS/src/core/mips_bui.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_bui.vhd
@@ -29,6 +29,11 @@ library work;
 use work.mips_types.all;
 
 entity bui is
+	Generic
+	(
+		icache_size	: natural := 2048;	-- words
+		dcache_size	: natural := 2048	-- words
+	);
 	Port
 	(
 		RST_I			: in  STD_LOGIC;
@@ -64,8 +69,8 @@ architecture behavior of bui is
 	COMPONENT icache
 	GENERIC
 	(
-		cache_size	: natural := 2048;	-- words
-		line_size	: natural := 8		-- words
+		cache_size	: natural;	-- words
+		line_size	: natural	-- words
 	);
 	PORT
 	(
@@ -88,8 +93,8 @@ architecture behavior of bui is
 	COMPONENT dcache
 	GENERIC
 	(
-		cache_size	: natural := 2048;	-- words
-		line_size	: natural := 8		-- words
+		cache_size	: natural;	-- words
+		line_size	: natural	-- words
 	);
 	PORT
 	(
@@ -217,7 +222,7 @@ read_cyc_register:
 inst_icache : icache
 	GENERIC MAP
 	(
-		cache_size	=> 2048,	-- words
+		cache_size	=> icache_size,	-- words
 		line_size	=> 8
 	)	
 	PORT MAP
@@ -242,7 +247,7 @@ inst_icache : icache
 inst_dcache : dcache
 	GENERIC MAP
 	(
-		cache_size	=> 2048,	-- words
+		cache_size	=> dcache_size,	-- words
 		line_size	=> 8
 	)
 	PORT MAP
@@ -295,11 +300,6 @@ inst_bout_fifo: entity work.fifo_sync_dist
 	bout_fifo_re		<= not bout_fifo_empty and SRDY_I;
 	
 	bout_fifo_we		<= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
--- 	bout_fifo_we		<= STB_O_dmem_wr when dmem_mem_wr_gnt = '1' else
--- 						   STB_O_dmem_rd when dmem_mem_rd_gnt = '1' else
--- 						   STB_O_dcache when dcache_mem_gnt = '1' else
--- 						   STB_O_icache when icache_mem_gnt = '1' else '0';
-						   
 
 	bout_fifo_data_in	<= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');