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- refactored

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1538 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-26 16:40:32 +00:00
parent 7b2080f729
commit 8c656907f3
1 changed files with 30 additions and 30 deletions
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lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+4 -4
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@@ -496,6 +496,7 @@ proc_stage_ID_EX_1:
EX_stage.reg_a <= (others => '0');
EX_stage.reg_b <= (others => '0');
elsif sdu.EX_stall = '0' then
EX_stage.va <= vaddr;
EX_stage.nop <= sdu.EX_nop;
EX_stage.reg_a <= ID_stage.reg_a;
EX_stage.reg_b <= ID_stage.reg_b;
@@ -575,7 +576,6 @@ proc_stage_DMEM_ADDR:
begin
if rising_edge(clk_1) then
if sdu.EX_stall = '0' then
EX_stage.va <= vaddr;
if c0_ctrl_in.EB = '1' then
if ID_stage.ctrl.word2_en = '0' then
EX_stage.pa_off <= not vaddr(1 downto 0);
@@ -809,12 +809,12 @@ proc_stage_MEM_mux:
variable be : unsigned(3 downto 0);
begin
data := MEM_stage.ex_result;
if MEM_stage.ctrl.reg_link = '1' then
data := MEM_stage.epc + 8;
elsif MEM_stage.ctrl.dmem_en = '1' then
temp1 := load_shift(dmem_din, MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp);
temp2 := load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en);
be := load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp);
if MEM_stage.ctrl.reg_link = '1' then
data := MEM_stage.epc + 8;
elsif MEM_stage.ctrl.dmem_en = '1' then
if be(0) = '1' then
data(7 downto 0) := temp2(7 downto 0);
end if;