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- refactored

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1538 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-26 16:40:32 +00:00
parent 7b2080f729
commit 8c656907f3
1 changed files with 30 additions and 30 deletions
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lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+30 -30
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@@ -307,7 +307,7 @@ proc_stage_pc_next:
proc_stage_branch:
process(clk_2)
begin
if rising_edge(clk_2) then
if rising_edge(clk_2) then
if branch_ce = '1' then
pc.branch_take <= '0';
if EX_stage.ctrl.branch = '1' then
@@ -327,7 +327,7 @@ proc_stage_branch:
end case;
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
@@ -485,18 +485,19 @@ proc_stage_ID_EX_1:
begin
if rising_edge(clk_1) then
if stage_rst(1) = '1' then
EX_stage.nop <= '1';
EX_stage.nop <= '1';
EX_stage.op <= op_nop;
EX_stage.IR <= (others => '0');
EX_stage.ctrl <= ctrl_lines_default;
EX_stage.reg_write <= '0';
EX_stage.epc <= (others => '0');
EX_stage.pcn <= (others => '0');
EX_stage.events_in <= events_clr;
EX_stage.reg_a <= (others => '0');
EX_stage.reg_b <= (others => '0');
EX_stage.events_in <= events_clr;
EX_stage.reg_a <= (others => '0');
EX_stage.reg_b <= (others => '0');
elsif sdu.EX_stall = '0' then
EX_stage.nop <= sdu.EX_nop;
EX_stage.va <= vaddr;
EX_stage.nop <= sdu.EX_nop;
EX_stage.reg_a <= ID_stage.reg_a;
EX_stage.reg_b <= ID_stage.reg_b;
EX_stage.events_in <= ID_stage.events;
@@ -575,7 +576,6 @@ proc_stage_DMEM_ADDR:
begin
if rising_edge(clk_1) then
if sdu.EX_stall = '0' then
EX_stage.va <= vaddr;
if c0_ctrl_in.EB = '1' then
if ID_stage.ctrl.word2_en = '0' then
EX_stage.pa_off <= not vaddr(1 downto 0);
@@ -634,11 +634,11 @@ proc_wptr_mux:
proc_stage_bcu_op:
process(clk_1)
begin
if rising_edge(clk_1) then
if rising_edge(clk_1) then
if sdu.EX_stall = '0' then
bcu_op_a <= ID_stage.reg_a;
bcu_op_b <= ID_stage.reg_b;
end if;
end if;
end if;
end process;
@@ -649,7 +649,7 @@ alu_op2_mux:
variable data : word_t;
begin
if rising_edge(clk_1) then
if rising_edge(clk_1) then
if sdu.EX_stall = '0' then
data := ID_stage.reg_b;
@@ -666,7 +666,7 @@ alu_op2_mux:
end case;
EX_stage.alu_op2 <= data;
end if;
end if;
end if;
end process;
@@ -677,7 +677,7 @@ shifter_sa_mux:
variable data_inv : shamt_t;
begin
if rising_edge(clk_1) then
if rising_edge(clk_1) then
if sdu.EX_stall = '0' then
data := ID_stage.reg_a(4 downto 0);
case ID_stage.ctrl.shamt2_srcsel is
@@ -700,7 +700,7 @@ shifter_sa_mux:
EX_stage.shift_ctrl.shamt_nrm <= data;
EX_stage.shift_ctrl.shift_right <= ID_stage.ctrl.alu.shift_right;
EX_stage.shift_ctrl.shift_arith <= ID_stage.ctrl.alu.shift_arith;
end if;
end if;
end if;
end process;
@@ -753,19 +753,19 @@ proc_stage_MEM_n:
begin
if rising_edge(clk_1) then
if stage_rst(2) = '1' then
MEM_stage.nop <= '1';
MEM_stage.op <= op_nop;
MEM_stage.va <= (others => '0');
MEM_stage.pcn <= (others => '0');
MEM_stage.ex_result <= (others => '0');
MEM_stage.epc <= (others => '0');
MEM_stage.nop <= '1';
MEM_stage.op <= op_nop;
MEM_stage.va <= (others => '0');
MEM_stage.pcn <= (others => '0');
MEM_stage.ex_result <= (others => '0');
MEM_stage.epc <= (others => '0');
MEM_stage.wreg_we <= '0';
MEM_stage.reg_wptr <= (others => '0');
MEM_stage.reg_wptr <= (others => '0');
MEM_stage.ctrl <= ctrl_lines_default;
MEM_stage.pa_off <= (others => '0');
MEM_stage.events_in <= events_clr;
elsif sdu.MEM_stall = '0' then
MEM_stage.nop <= sdu.MEM_nop;
MEM_stage.nop <= sdu.MEM_nop;
MEM_stage.events_in <= EX_stage.events;
MEM_stage.op <= EX_stage.op;
MEM_stage.wreg_we <= EX_stage.wreg_we;
@@ -809,12 +809,12 @@ proc_stage_MEM_mux:
variable be : unsigned(3 downto 0);
begin
data := MEM_stage.ex_result;
temp1 := load_shift(dmem_din, MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp);
temp2 := load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en);
be := load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp);
if MEM_stage.ctrl.reg_link = '1' then
data := MEM_stage.epc + 8;
elsif MEM_stage.ctrl.dmem_en = '1' then
temp1 := load_shift(dmem_din, MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp);
temp2 := load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en);
be := load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp);
if be(0) = '1' then
data(7 downto 0) := temp2(7 downto 0);
end if;
@@ -850,16 +850,16 @@ proc_stage_WB_p:
begin
if rising_edge(clk_1) then
if stage_rst(3) = '1' then
WB_stage.nop <= '1';
WB_stage.nop <= '1';
WB_stage.op <= op_nop;
WB_stage.wreg_we <= '1';
WB_stage.reg_wptr <= (others => '0');
WB_stage.data <= (others => '0');
WB_stage.events <= events_clr;
WB_stage.bd <= '0';
WB_stage.exc <= '0';
WB_stage.events <= events_clr;
WB_stage.bd <= '0';
WB_stage.exc <= '0';
elsif sdu.WB_stall = '0' then
WB_stage.nop <= sdu.WB_nop;
WB_stage.nop <= sdu.WB_nop;
WB_stage.op <= MEM_stage.op;
WB_stage.wreg_we <= MEM_stage.wreg_we;
WB_stage.reg_wptr <= MEM_stage.reg_wptr;