diff --git a/lib/filter/src/fir_iterative.vhd b/lib/filter/src/fir_iterative.vhd
index 45133ff..2526e67 100644
--- a/lib/filter/src/fir_iterative.vhd
+++ b/lib/filter/src/fir_iterative.vhd
@@ -100,8 +100,9 @@ architecture Behavioral of fir_iterative is
 	constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
 	constant h_addr_bits : integer := taps_nbits(ntaps, fir_mode);
 	
-	subtype in_t is sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-	subtype stage_t is sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
+	subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
+	subtype stage_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
 	
 	type state_t is (init, idle, start, proc, p1, p2, output);
 	signal s, sn : state_t;
@@ -120,7 +121,7 @@ architecture Behavioral of fir_iterative is
 
 	type xmem_t is array (0 to ntaps-1) of in_t;
 	signal xmem : xmem_t;
-	signal y_out_reg : stage_t;
+	signal y_out_reg : out_t;
 	signal y_reg_valid : std_logic;
 	
 	-------------------------------------------------------------------------------
@@ -135,9 +136,9 @@ begin
 	if rising_edge(clk) then
 		y_reg_valid <= '0';
 		if srst = '1' then
-			y_out_reg <= to_sfixed(0, sproto(nbits_out, nbits_out_frac));
+			y_out_reg <= to_sfixed(0, y_out_reg);
 		elsif y_valid = '1' then
-			y_out_reg <=  y_stage;
+			y_out_reg <=  resize(y_stage, y_out_reg);
 			y_reg_valid <= '1';
 		end if;
 	end if;
diff --git a/lib/filter/src/fir_parallel.vhd b/lib/filter/src/fir_parallel.vhd
index 73a1da1..43d0cbf 100644
--- a/lib/filter/src/fir_parallel.vhd
+++ b/lib/filter/src/fir_parallel.vhd
@@ -99,13 +99,13 @@ architecture Behavioral of fir_parallel is
 	END COMPONENT;
 
 	-------------------------------------------------------------------------------
-	type coeff_array_t is array (natural range <>) of sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
-	type stages_array_t is array (natural range <>) of sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
+	type coeff_array_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
+	type stages_array_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
 
 	constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
 	constant fir_stage_mode : fir_stage_mode_t := transposed;
 
-	SIGNAL x_out       : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+	SIGNAL x_out       : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
 
 	SIGNAL x    	   : stages_array_t(0 to ntaps-2);
 	SIGNAL y           : stages_array_t(0 to ntaps-2);
diff --git a/lib/filter/src/fir_parallel_pkg.vhd b/lib/filter/src/fir_parallel_pkg.vhd
index 1925ae7..67ee5fe 100644
--- a/lib/filter/src/fir_parallel_pkg.vhd
+++ b/lib/filter/src/fir_parallel_pkg.vhd
@@ -48,7 +48,7 @@ package body fir_parallel_pkg is
 
 	---------------------------------------------------------------------------
 	function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t is
-	variable p : sfixed(sproto(nbits, nbits_int)'high downto sproto(nbits, nbits_int)'low);
+	variable p : sfixed(shi(nbits, nbits_int) downto slo(nbits, nbits_int));
 	begin
 		return to_sfixed_array(x, p);
 	end to_sfixed_array;	
diff --git a/lib/filter/src/fir_stage.vhd b/lib/filter/src/fir_stage.vhd
index 8001b7a..6462faa 100644
--- a/lib/filter/src/fir_stage.vhd
+++ b/lib/filter/src/fir_stage.vhd
@@ -66,10 +66,10 @@ end fir_stage;
 
 architecture Behavioral of fir_stage is
 
-signal xin : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-signal yin : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-signal hin : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-signal prod : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+signal xin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+signal yin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+signal hin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+signal prod : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
 signal valid, p_valid : std_logic;
 ------------------------------------------------------------
 begin
@@ -89,7 +89,7 @@ begin
 
 ------------------------------------------------------------
 	proc_in_reg_hx: process(srst, clk, in_valid, x_in, h_in)
-	variable p : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+	variable p : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
 	begin
 		if has_in_reg = true then
 			if rising_edge(clk) then
@@ -116,7 +116,7 @@ begin
 
 ------------------------------------------------------------
 	proc_pipe_reg: process(srst, clk, valid, xin, hin)
-	variable p : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+	variable p : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
 	begin
 		p := resize(xin * hin, p);
 		if has_pipe_reg = true then
@@ -137,7 +137,7 @@ begin
 	
 ------------------------------------------------------------
 	proc_out_reg: process(srst, clk, p_valid, prod, yin)
-	variable yout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+	variable yout : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
 	begin
 		yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate);
 --		if rising_edge(clk) then
diff --git a/lib/filter/src/tb_fir_iterative.vhd b/lib/filter/src/tb_fir_iterative.vhd
index b1a6fd9..3684f06 100644
--- a/lib/filter/src/tb_fir_iterative.vhd
+++ b/lib/filter/src/tb_fir_iterative.vhd
@@ -86,11 +86,11 @@ ARCHITECTURE behavior OF tb_fir_iterative IS
 	SIGNAL clk         : std_logic := '0';
 	SIGNAL srst        : std_logic := '1';
 	SIGNAL x_valid    : std_logic := '0';
-	SIGNAL h_din        : sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
-	SIGNAL x_din        : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+	SIGNAL h_din        : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
+	SIGNAL x_din        : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
 
 	--Outputs
-	SIGNAL y_dout       : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+	SIGNAL y_dout       : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
 	SIGNAL y_valid   : std_logic;
 	SIGNAL ready   : std_logic;
 
@@ -136,7 +136,7 @@ ARCHITECTURE behavior OF tb_fir_iterative IS
 		0.0
 		
 	);
-	type ymem_t is array (0 to nsamples-1) of sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+	type ymem_t is array (0 to nsamples-1) of sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
 	signal ymem : ymem_t;
 	
 	signal y_cnt : integer ;
diff --git a/lib/filter/src/tb_fir_parallel.vhd b/lib/filter/src/tb_fir_parallel.vhd
index 361df0a..32e451a 100644
--- a/lib/filter/src/tb_fir_parallel.vhd
+++ b/lib/filter/src/tb_fir_parallel.vhd
@@ -88,16 +88,16 @@ ARCHITECTURE behavior OF tb_fir_parallel IS
 	SIGNAL clk         : std_logic := '0';
 	SIGNAL srst        : std_logic := '1';
 	SIGNAL in_valid    : std_logic := '0';
-	SIGNAL x_in        : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+	SIGNAL x_in        : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
 
 	--Outputs
-	SIGNAL y_out       : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+	SIGNAL y_out       : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
 	SIGNAL out_valid   : std_logic := '0';
 
 	SIGNAL fileout_enable   : std_logic := '1';
 	
 	-- Test coefficients
-	SIGNAL coeff_in : sfixed_array_t(0 to ntaps-1, sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low) := to_sfixed_array(FilterCoef_Lowpass(ntaps, 0.125, 0.125), nbits_stages, nbits_stages_frac);
+	SIGNAL coeff_in : sfixed_array_t(0 to ntaps-1, shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)) := to_sfixed_array(FilterCoef_Lowpass(ntaps, 0.125, 0.125), nbits_stages, nbits_stages_frac);
 	
 	SIGNAL xi, yo : real := 0.0;
 	
diff --git a/lib/filter/src/tb_fir_stage.vhd b/lib/filter/src/tb_fir_stage.vhd
index 74ae167..d5a2d16 100644
--- a/lib/filter/src/tb_fir_stage.vhd
+++ b/lib/filter/src/tb_fir_stage.vhd
@@ -78,7 +78,7 @@ ARCHITECTURE behavior OF tb_fir_stage IS
 	);
 	END COMPONENT;
 
-	type stages_t is array (natural range <>) of sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low); 
+	type stages_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); 
 
 	--Constants
 	constant PERIOD : time := 10 ns;
@@ -88,11 +88,11 @@ ARCHITECTURE behavior OF tb_fir_stage IS
 	SIGNAL clk         : std_logic := '0';
 	SIGNAL srst        : std_logic := '1';
 	SIGNAL in_valid    : std_logic := '0';
-	SIGNAL x_in        : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+	SIGNAL x_in        : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
 
 	--Outputs
-	SIGNAL x_out       : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
-	SIGNAL y_out       : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+	SIGNAL x_out       : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
+	SIGNAL y_out       : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
 	SIGNAL out_valid   : std_logic := '0';
 
 	SIGNAL x    	   : stages_t(0 to ntaps-2);