From 8b49c6197c69d4d4e3738cc823f752350580374d Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 27 Oct 2009 21:25:36 +0000 Subject: [PATCH] - redesigned FSM. Zero leadin, zeroleadout and zero release is now possible - added assertion check for zero r/w-pulses Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@535 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/misc/async_port_wb.vhd | 118 +++++++++++++++++++------------------ 1 file changed, 61 insertions(+), 57 deletions(-) diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd index ab572d2..2ec000d 100644 --- a/lib/misc/async_port_wb.vhd +++ b/lib/misc/async_port_wb.vhd @@ -1,5 +1,5 @@ ----------------------------------------------------------------------- --- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.5 2009-02-08 17:34:18 Jens Exp $ +-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.6 2009-10-27 21:25:36 Jens Exp $ ----------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -49,7 +49,7 @@ architecture Behavioral of async_port_wb is drive_d : std_logic; end record; - type async_state_t is (start, reset, idle, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release); + type async_state_t is (start, reset, idle, leadin, pulse, leadout, release); signal s, sn : async_state_t; signal as : async_t; @@ -62,9 +62,13 @@ architecture Behavioral of async_port_wb is signal en : std_logic; signal data_reg : unsigned(data_width-1 downto 0); signal byte_en : unsigned(byte_sel_width-1 downto 0); + signal write : std_logic; ------------------------------------------------------------------ begin + + ASSERT async_timespec.ncyc_pulse_rd > 0 report "Read pulse length must be greater than zero!" severity failure; + ASSERT async_timespec.ncyc_pulse_wr > 0 report "Write pulse length must be greater than zero!" severity failure; SRDY_O <= CYC_I and rdyo; en <= CYC_I and STB_I; @@ -95,7 +99,7 @@ architecture Behavioral of async_port_wb is end process; proc_state: - process(s, cycle_cnt, en, WE_I) + process(s, cycle_cnt, en, write, WE_I) begin cycle_reload <= async_timespec.ncyc_pulse_rst; @@ -124,73 +128,72 @@ architecture Behavioral of async_port_wb is if en = '1' then as.cs <= '1'; cc_rst <= '1'; - cycle_reload <= async_timespec.ncyc_access-1; - if WE_I = '0' then - sn <= leadin_rd; + if async_timespec.ncyc_leadin = 0 then + sn <= pulse; + if WE_I = '1' then + cycle_reload <= async_timespec.ncyc_pulse_wr-1; + as.wr <= '1'; + as.drive_d <= '1'; + else + cycle_reload <= async_timespec.ncyc_pulse_rd-1; + as.rd <= '1'; + end if; else - sn <= leadin_wr; + cycle_reload <= async_timespec.ncyc_leadin-1; + sn <= leadin; + end if; + end if; + + when leadin => + as.cs <= '1'; + if cycle_cnt = 0 then + cc_rst <= '1'; + sn <= pulse; + if write = '1' then + cycle_reload <= async_timespec.ncyc_pulse_wr-1; + as.wr <= '1'; + as.drive_d <= '1'; + else + cycle_reload <= async_timespec.ncyc_pulse_rd-1; + as.rd <= '1'; end if; end if; - when leadin_rd => + when pulse => as.cs <= '1'; - if cycle_cnt = 0 then - cc_rst <= '1'; - cycle_reload <= async_timespec.ncyc_pulse_rd-1; - as.rd <= '1'; - sn <= read; - end if; - - when leadin_wr => - as.cs <= '1'; - if cycle_cnt = 0 then - cc_rst <= '1'; - cycle_reload <= async_timespec.ncyc_pulse_wr-1; - as.wr <= '1'; - as.drive_d <= '1'; - sn <= write; - end if; - - when read => - as.cs <= '1'; - as.rd <= '1'; - if cycle_cnt = 0 then - cc_rst <= '1'; - cycle_reload <= async_timespec.ncyc_cs_hold-1; --- as.rd <= '0'; - sn <= leadout_rd; - ack <= '1'; - end if; - - when write => - as.drive_d <= '1'; - as.cs <= '1'; - as.wr <= '1'; + as.rd <= not write; + as.drive_d <= write; + as.wr <= write; if cycle_cnt = 0 then as.wr <= '0'; + as.rd <= '0'; cc_rst <= '1'; - cycle_reload <= async_timespec.ncyc_cs_hold-1; - sn <= leadout_wr; --- ack <= '1'; + ack <= not write; + if async_timespec.ncyc_leadout = 0 then + as.cs <= '0'; + if async_timespec.ncyc_release = 0 then + sn <= idle; + else + cycle_reload <= async_timespec.ncyc_release-1; + sn <= release; + end if; + else + cycle_reload <= async_timespec.ncyc_leadout-1; + sn <= leadout; + end if; end if; - - when leadout_rd => + + when leadout => as.cs <= '1'; if cycle_cnt = 0 then cc_rst <= '1'; - cycle_reload <= async_timespec.ncyc_release-1; - sn <= release; - as.cs <= '0'; - end if; - - when leadout_wr => - as.cs <= '1'; - as.drive_d <= '1'; - if cycle_cnt = 0 then - cc_rst <= '1'; - cycle_reload <= async_timespec.ncyc_release-1; - sn <= release; as.cs <= '0'; + if async_timespec.ncyc_release = 0 then + sn <= idle; + else + cycle_reload <= async_timespec.ncyc_release-1; + sn <= release; + end if; end if; when release => @@ -250,6 +253,7 @@ architecture Behavioral of async_port_wb is if rising_edge(CLK_I) then if en = '1' and rdy = '1' then data_reg <= DAT_I(data_width-1 downto 0); + write <= WE_I; end if; end if; end process;