From 88bd1e16d97a01b0027a0679685e6a2941f7467b Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sun, 21 Mar 2010 14:49:51 +0000
Subject: [PATCH] - added TX_RAM_SIZE generic Committed on the Free edition of
 March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and
 support: http://march-hare.com/cvsnt/

git-svn-id: http://moon:8086/svn/vhdl/trunk@806 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/emac/emac_jb.vhd        | 10 +++++++---
 lib/emac/src/tb_emac_jb.vhd | 16 +++++++++++++++-
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/lib/emac/emac_jb.vhd b/lib/emac/emac_jb.vhd
index 1daca4a..ada8e05 100644
--- a/lib/emac/emac_jb.vhd
+++ b/lib/emac/emac_jb.vhd
@@ -3,10 +3,13 @@ USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 use std.textio.all; --  Imports the standard textio package.
 
+use work.utils_pkg.all;
+
 ENTITY emac_jb IS
 	Generic
 	(
-		f_sysclk	: real	:= 100.0
+		f_sysclk	: real		:= 100.0;
+		TX_RAM_SIZE	: natural	:= 2048
 	);
 	Port
 	(
@@ -40,7 +43,8 @@ END emac_jb;
 
 ARCHITECTURE behavior OF emac_jb IS
 
-	constant TX_RAM_ADDR_WIDTH	: natural := 9;
+	constant TX_RAM_ADDR_WIDTH	: natural := NextExpBaseTwo(TX_RAM_SIZE);
+	
 	subtype word_ptr_t is unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
 	
 	-- Signals for EMAC connections
@@ -118,7 +122,7 @@ ARCHITECTURE behavior OF emac_jb IS
 	signal piso_din_rdy		: std_logic;
 	signal tx_data_vld		: std_logic;
 	
-	subtype inter_frame_gap_cnt_t is natural range 0 to natural(10.0*f_sysclk)-1;
+	subtype inter_frame_gap_cnt_t is natural range 0 to natural(1.0*f_sysclk)-1;
 	signal inter_frame_gap_cnt	: inter_frame_gap_cnt_t;
 	signal inter_frame_gap_rdy	: std_logic;
 	
diff --git a/lib/emac/src/tb_emac_jb.vhd b/lib/emac/src/tb_emac_jb.vhd
index e156215..1ea1f7a 100644
--- a/lib/emac/src/tb_emac_jb.vhd
+++ b/lib/emac/src/tb_emac_jb.vhd
@@ -33,6 +33,7 @@ ARCHITECTURE behavior OF tb_emac_jb IS
 
 	constant CLK_PERIOD		: time := 10 ns;
 	constant MII_CLK_PERIOD	: time := 8 ns;
+
 	signal CLK				: std_logic := '1';
 	signal RST				: std_logic := '1';
 
@@ -93,7 +94,8 @@ BEGIN
 inst_emac_jb : entity work.emac_jb
 	GENERIC MAP
 	(
-		f_sysclk	=> 100.0
+		f_sysclk	=> 100.0,
+		TX_RAM_SIZE	=> 2048
 	)
 	PORT MAP
 	(
@@ -313,6 +315,18 @@ STIMULUS: process
  		emac_alloc (1536);
  		emac_write (1536);
 
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
 		emac_alloc (64);
 		emac_write (64);