del
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@480 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -1,211 +0,0 @@
|
|||||||
-------------------------------------------------------------------------
|
|
||||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
|
||||||
-- This file: Dual-ported register file with asynchrous read
|
|
||||||
|
|
||||||
-- Copyright (C) 2007 J. Ahrensfeld
|
|
||||||
|
|
||||||
-- This library is free software; you can redistribute it and/or
|
|
||||||
-- modify it under the terms of the GNU Lesser General Public
|
|
||||||
-- License as published by the Free Software Foundation; either
|
|
||||||
-- version 2.1 of the License, or (at your option) any later version.
|
|
||||||
|
|
||||||
-- This library is distributed in the hope that it will be useful,
|
|
||||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
||||||
-- Lesser General Public License for more details.
|
|
||||||
|
|
||||||
-- You should have received a copy of the GNU Lesser General Public
|
|
||||||
-- License along with this library; if not, write to the Free Software
|
|
||||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
|
||||||
|
|
||||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
|
||||||
|
|
||||||
-----------------------------------------------------------------------
|
|
||||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r_virtex4.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
|
|
||||||
-----------------------------------------------------------------------
|
|
||||||
|
|
||||||
library IEEE;
|
|
||||||
use IEEE.STD_LOGIC_1164.ALL;
|
|
||||||
use IEEE.numeric_std.ALL;
|
|
||||||
|
|
||||||
library UNISIM;
|
|
||||||
use UNISIM.vcomponents.all;
|
|
||||||
|
|
||||||
entity dpram_2w2r is
|
|
||||||
Generic
|
|
||||||
(
|
|
||||||
addr_width : integer := 3;
|
|
||||||
data_width : integer := 8
|
|
||||||
);
|
|
||||||
Port
|
|
||||||
(
|
|
||||||
clk_a : in STD_LOGIC;
|
|
||||||
clk_b : in STD_LOGIC;
|
|
||||||
en_a : in STD_LOGIC;
|
|
||||||
en_b : in STD_LOGIC;
|
|
||||||
we_a : in STD_LOGIC;
|
|
||||||
we_b : in STD_LOGIC;
|
|
||||||
addr_a : in unsigned (addr_width-1 downto 0);
|
|
||||||
addr_b : in unsigned (addr_width-1 downto 0);
|
|
||||||
din_a : in unsigned (data_width-1 downto 0);
|
|
||||||
din_b : in unsigned (data_width-1 downto 0);
|
|
||||||
dout_a : out unsigned (data_width-1 downto 0);
|
|
||||||
dout_b : out unsigned (data_width-1 downto 0)
|
|
||||||
);
|
|
||||||
end dpram_2w2r;
|
|
||||||
|
|
||||||
architecture Structure of dpram_2w2r is
|
|
||||||
|
|
||||||
signal do_a : std_logic_vector(31 downto 0);
|
|
||||||
signal do_b : std_logic_vector(31 downto 0);
|
|
||||||
signal di_a : std_logic_vector(31 downto 0);
|
|
||||||
signal di_b : std_logic_vector(31 downto 0);
|
|
||||||
signal ad_a : std_logic_vector(14 downto 0);
|
|
||||||
signal ad_b : std_logic_vector(14 downto 0);
|
|
||||||
signal wr_a : std_logic_vector(3 downto 0);
|
|
||||||
signal wr_b : std_logic_vector(3 downto 0);
|
|
||||||
|
|
||||||
begin
|
|
||||||
|
|
||||||
-- RAMB16: 16k+2k Parity Paramatizable block RAM
|
|
||||||
-- Virtex-4
|
|
||||||
-- Xilinx HDL Libraries Guide, version 9.1i
|
|
||||||
RAMB16_inst : RAMB16
|
|
||||||
generic map
|
|
||||||
(
|
|
||||||
DOA_REG => 0, -- Optional output registers on the A port (0 or 1)
|
|
||||||
DOB_REG => 0, -- Optional output registers on the B port (0 or 1)
|
|
||||||
INIT_A => X"000000000", -- Initial values on A output port
|
|
||||||
INIT_B => X"000000000", -- Initial values on B output port
|
|
||||||
INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output registers (TRUE or FALSE)
|
|
||||||
INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output registers (TRUE or FALSE)
|
|
||||||
RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
|
|
||||||
RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
|
|
||||||
READ_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
|
|
||||||
READ_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36
|
|
||||||
SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
|
|
||||||
|
|
||||||
-- "GENERATE_X_ONLY" or "NONE"
|
|
||||||
SRVAL_A => X"000000000", -- Port A output value upon SSR assertion
|
|
||||||
SRVAL_B => X"000000000", -- Port B output value upon SSR assertion
|
|
||||||
WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
||||||
WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
||||||
WRITE_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
|
|
||||||
WRITE_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36
|
|
||||||
|
|
||||||
-- The following INIT_xx declarations specify the initial contents of the RAM
|
|
||||||
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
|
|
||||||
-- The next set of INITP_xx are for the parity bits
|
|
||||||
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
||||||
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
|
|
||||||
)
|
|
||||||
port map
|
|
||||||
(
|
|
||||||
CASCADEOUTA => open, -- 1-bit cascade output
|
|
||||||
CASCADEOUTB => open, -- 1-bit cascade output
|
|
||||||
DOA => do_a, -- 32-bit A port Data Output
|
|
||||||
DOB => do_b, -- 32-bit B port Data Output
|
|
||||||
DOPA => open, -- 4-bit A port Parity Output
|
|
||||||
DOPB => open, -- 4-bit B port Parity Output
|
|
||||||
ADDRA => ad_a, -- 15-bit A Port Address Input
|
|
||||||
ADDRB => ad_b, -- 15-bit B Port Address Input
|
|
||||||
CASCADEINA => '0', -- 1-bit cascade A input
|
|
||||||
CASCADEINB => '0', -- 1-bit cascade B input
|
|
||||||
CLKA => clk_a, -- Port A Clock
|
|
||||||
CLKB => clk_b, -- Port B Clock
|
|
||||||
DIA => di_a, -- 32-bit A port Data Input
|
|
||||||
DIB => di_b, -- 32-bit B port Data Input
|
|
||||||
DIPA => "0000", -- 4-bit A port parity Input
|
|
||||||
DIPB => "0000", -- 4-bit B port parity Input
|
|
||||||
ENA => en_a, -- 1-bit A port Enable Input
|
|
||||||
ENB => en_b, -- 1-bit B port Enable Input
|
|
||||||
REGCEA => '0', -- 1-bit A port register enable input
|
|
||||||
REGCEB => '0', -- 1-bit B port register enable input
|
|
||||||
SSRA => '0', -- 1-bit A port Synchronous Set/Reset Input
|
|
||||||
SSRB => '0', -- 1-bit B port Synchronous Set/Reset Input
|
|
||||||
WEA => wr_a, -- 4-bit A port Write Enable Input
|
|
||||||
WEB => wr_b -- 4-bit B port Write Enable Input
|
|
||||||
);
|
|
||||||
-- End of RAMB16_inst instantiation
|
|
||||||
|
|
||||||
dout_a <= unsigned(do_a(7 downto 0));
|
|
||||||
dout_b <= unsigned(do_b(7 downto 0));
|
|
||||||
di_a <= X"000000" & std_logic_vector(din_a);
|
|
||||||
di_b <= X"000000" & std_logic_vector(din_b);
|
|
||||||
ad_a <= '0' & std_logic_vector(addr_a) & "000";
|
|
||||||
ad_b <= '0' & std_logic_vector(addr_b) & "000";
|
|
||||||
wr_a <= (3 downto 0 => we_a);
|
|
||||||
wr_b <= (3 downto 0 => we_b);
|
|
||||||
|
|
||||||
end Structure;
|
|
||||||
|
|
||||||
Reference in New Issue
Block a user