diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.prj b/projects/mips_sys/ise101/mips_sys/mips_sys.prj
index ce7b8ab..9e78e5f 100644
--- a/projects/mips_sys/ise101/mips_sys/mips_sys.prj
+++ b/projects/mips_sys/ise101/mips_sys/mips_sys.prj
@@ -1,16 +1,15 @@
+vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
 vhdl work "../../src/sdram_config.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
 vhdl work "../../../../lib/misc/utils_pkg.vhd"
 vhdl work "../../../../lib/misc/singleshot.vhd"
 vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
-vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
 vhdl work "../../../../lib/uart/kcuart_tx.vhd"
 vhdl work "../../../../lib/uart/kcuart_rx.vhd"
 vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
@@ -18,8 +17,8 @@ vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
 vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd"
 vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd"
 vhdl work "../../src/bootloader.ROM_ld.vhd"
@@ -29,10 +28,11 @@ vhdl work "../../../../lib/uart/uart_tx.vhd"
 vhdl work "../../../../lib/uart/uart_rx.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
 vhdl work "../../../../lib/misc/async_types.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
 vhdl work "../../../../lib/ac97_ctrl/src/core/ac_io.vhd"
 vhdl work "../../src/async_defs.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
 vhdl work "../../../../lib/uart/uart_wb.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
 vhdl work "../../../../lib/misc/rom_wb.vhd"
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
index b62311a..4b52d29 100644
--- a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
+++ b/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
@@ -1,16 +1,15 @@
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
 vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
 vhdl work "W:\vhdl\lib\misc\singleshot.vhd"
 vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
 vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
 vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
 vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
@@ -18,8 +17,8 @@ vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
 vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd"
 vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
@@ -29,10 +28,11 @@ vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
 vhdl work "W:\vhdl\lib\misc\async_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
 vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_io.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\async_defs.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
 vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"