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- Added bus error signals

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git-svn-id: http://moon:8086/svn/vhdl/trunk@33 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-09 11:51:55 +00:00
parent 098b5982b2
commit 86866b26a7
1 changed files with 15 additions and 1 deletions
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lib/CPUs/MIPS/src/core/mips_top.vhd
+15 -1
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@@ -31,6 +31,7 @@ use work.mips_types.all;
entity mips_top is entity mips_top is
Port Port
( (
debug : out unsigned(1 downto 0);
RST_I : in STD_LOGIC; RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC; CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC; ACK_I : in STD_LOGIC;
@@ -51,15 +52,18 @@ end mips_top;
architecture rtl of mips_top is architecture rtl of mips_top is
COMPONENT pipeline is COMPONENT pipeline is
Port ( Port
(
rst : in STD_LOGIC; rst : in STD_LOGIC;
clk : in STD_LOGIC; clk : in STD_LOGIC;
halt : in STD_LOGIC; halt : in STD_LOGIC;
int : in unsigned (5 downto 0); int : in unsigned (5 downto 0);
imem_err : in STD_LOGIC;
imem_rdy : in STD_LOGIC; imem_rdy : in STD_LOGIC;
imem_en : out STD_LOGIC; imem_en : out STD_LOGIC;
imem_addr : out word_t; imem_addr : out word_t;
imem_data : in word_t; imem_data : in word_t;
dmem_err : in STD_LOGIC;
dmem_rdy : in STD_LOGIC; dmem_rdy : in STD_LOGIC;
dmem_en : out STD_LOGIC; dmem_en : out STD_LOGIC;
dmem_re : out STD_LOGIC; dmem_re : out STD_LOGIC;
@@ -69,10 +73,12 @@ architecture rtl of mips_top is
dmem_dout : out word_t dmem_dout : out word_t
); );
END COMPONENT; END COMPONENT;
signal imem_err : std_logic;
signal imem_rdy : std_logic; signal imem_rdy : std_logic;
signal imem_en : std_logic; signal imem_en : std_logic;
signal imem_addr : word_t; signal imem_addr : word_t;
signal imem_din : word_t; signal imem_din : word_t;
signal dmem_err : std_logic;
signal dmem_rdy : std_logic; signal dmem_rdy : std_logic;
signal dmem_en : std_logic; signal dmem_en : std_logic;
signal dmem_re : std_logic; signal dmem_re : std_logic;
@@ -97,10 +103,12 @@ architecture rtl of mips_top is
CYC_O : out STD_LOGIC; CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC; STB_O : out STD_LOGIC;
MRDY_O : out STD_LOGIC; MRDY_O : out STD_LOGIC;
cpu_imem_err : out STD_LOGIC;
cpu_imem_rdy : out STD_LOGIC; cpu_imem_rdy : out STD_LOGIC;
cpu_imem_en : in STD_LOGIC; cpu_imem_en : in STD_LOGIC;
cpu_imem_addr : in word_t; cpu_imem_addr : in word_t;
cpu_imem_din : out word_t; cpu_imem_din : out word_t;
cpu_dmem_err : out STD_LOGIC;
cpu_dmem_rdy : out STD_LOGIC; cpu_dmem_rdy : out STD_LOGIC;
cpu_dmem_en : in STD_LOGIC; cpu_dmem_en : in STD_LOGIC;
cpu_dmem_re : in STD_LOGIC; cpu_dmem_re : in STD_LOGIC;
@@ -114,6 +122,8 @@ architecture rtl of mips_top is
begin begin
------------------------------------------------------------------- -------------------------------------------------------------------
debug(0) <= imem_err;
debug(1) <= dmem_err;
inst_pipeline: pipeline inst_pipeline: pipeline
PORT MAP PORT MAP
@@ -122,10 +132,12 @@ inst_pipeline: pipeline
clk => CLK_I, clk => CLK_I,
halt => '0', halt => '0',
int => INT, int => INT,
imem_err => imem_err,
imem_rdy => imem_rdy, imem_rdy => imem_rdy,
imem_en => imem_en, imem_en => imem_en,
imem_addr => imem_addr, imem_addr => imem_addr,
imem_data => imem_din, imem_data => imem_din,
dmem_err => dmem_err,
dmem_rdy => dmem_rdy, dmem_rdy => dmem_rdy,
dmem_en => dmem_en, dmem_en => dmem_en,
dmem_re => dmem_re, dmem_re => dmem_re,
@@ -150,10 +162,12 @@ inst_bui: bui
CYC_O => CYC_O, CYC_O => CYC_O,
STB_O => STB_O, STB_O => STB_O,
MRDY_O => MRDY_O, MRDY_O => MRDY_O,
cpu_imem_err => imem_err,
cpu_imem_rdy => imem_rdy, cpu_imem_rdy => imem_rdy,
cpu_imem_en => imem_en, cpu_imem_en => imem_en,
cpu_imem_addr => imem_addr, cpu_imem_addr => imem_addr,
cpu_imem_din => imem_din, cpu_imem_din => imem_din,
cpu_dmem_err => dmem_err,
cpu_dmem_rdy => dmem_rdy, cpu_dmem_rdy => dmem_rdy,
cpu_dmem_en => dmem_en, cpu_dmem_en => dmem_en,
cpu_dmem_re => dmem_re, cpu_dmem_re => dmem_re,