From 860e2984fd6a1b396acd14ef7434486c81ee70b9 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 28 Dec 2008 16:29:13 +0000 Subject: [PATCH] - Cleaned up git-svn-id: http://moon:8086/svn/vhdl/trunk@154 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/radio/nco/src/mix_cordic_dbg.vhd | 209 --------------------------- lib/radio/nco/src/nco_cordic_dbg.vhd | 209 --------------------------- 2 files changed, 418 deletions(-) delete mode 100644 lib/radio/nco/src/mix_cordic_dbg.vhd delete mode 100644 lib/radio/nco/src/nco_cordic_dbg.vhd diff --git a/lib/radio/nco/src/mix_cordic_dbg.vhd b/lib/radio/nco/src/mix_cordic_dbg.vhd deleted file mode 100644 index 25d9054..0000000 --- a/lib/radio/nco/src/mix_cordic_dbg.vhd +++ /dev/null @@ -1,209 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.cordic_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity mix is -Generic -( - nbits_wave_in : integer := 18; - nbits_wave_in_frac : integer := 16; - nbits_wave_out : integer := 18; - nbits_wave_out_frac : integer := 16; - nbits_phase : integer := 16 -); -Port -( - srst : in std_logic; - clk : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - wave_in_i : in sfixed; - wave_in_q : in sfixed; - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic; - debug_out : out debug_mix_out_t -); -end mix; - -architecture Behavioral of mix is - - COMPONENT cordic_pipe_top - GENERIC - ( - cordic_mode : cordic_mode_t; - z_range : real; - gain_corr_mode : gain_corr_mode_t; - nstages : integer; - nbits_x_in : integer; - nbits_y_in : integer; - nbits_z_in : integer; - nbits_frac_x_in : integer; - nbits_frac_y_in : integer; - nbits_frac_z_in : integer; - nbits_x_out : integer; - nbits_y_out : integer; - nbits_z_out : integer; - nbits_frac_x_out : integer; - nbits_frac_y_out : integer; - nbits_frac_z_out : integer - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - vld_in : in std_logic; - xin : in sfixed; - yin : in sfixed; - zin : in sfixed; - xout : out sfixed; - yout : out sfixed; - zout : out sfixed; - vld_out : out std_logic - ); - END COMPONENT; - -------------------------------------------------------------------------------- - constant nbits_phase_frac : integer := nbits_phase; - -------------------------------------------------------------------------------- - signal phase : signed(nbits_phase-1 downto 0); - signal freq_in_r : signed(nbits_phase-1 downto 0); - signal phase_in_r : signed(nbits_phase-1 downto 0); - signal xin, yin : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)); - signal xout, yout : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac)); - - signal wave_out_valid : std_logic; - - signal zin : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac)); - signal zout : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac)); - -------------------------------------------------------------------------------- -begin - - wave_out_i <= xout; - wave_out_q <= yout; - xin <= wave_in_i; - yin <= wave_in_q; - - out_valid <= wave_out_valid; - - debug_out.i_in <= to_real(wave_in_i); - debug_out.q_in <= to_real(wave_in_q); - debug_out.i_out <= to_real(xout); - debug_out.q_out <= to_real(yout); - - ------------------------------------------------------------- - proc_phase_accu: process(clk) - variable phase_accu : signed(nbits_phase-1 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - phase_accu := (others => '0'); - else - phase <= phase_accu + phase_in_r; - if pacc_clr = '1' then - phase_accu := (others => '0'); - elsif pacc_inc = '1' then - phase_accu := phase_accu + freq_in_r; - end if; - end if; - end if; - zin <= sfixed(phase); - end process; - ------------------------------------------------------------- - freq_in_reg: process(srst, clk, freq_load, freq_in) - begin - if rising_edge(clk) then - if srst = '1' then - freq_in_r <= (others => '0'); - elsif freq_load = '1' then - freq_in_r <= signed(freq_in); - end if; - end if; - end process; - ------------------------------------------------------------- - phase_in_reg: process(srst, clk, phase_load, phase_in) - begin - if rising_edge(clk) then - if srst = '1' then - phase_in_r <= (others => '0'); - elsif phase_load = '1' then - phase_in_r <= signed(phase_in); - end if; - end if; - end process; - ------------------------------------------------------------- - inst_cordic_ud: cordic_pipe_top - GENERIC MAP - ( - cordic_mode => cordic_mode_rotate, - z_range => 1.0, - gain_corr_mode => gain_mode_disabled, - nstages => nbits_phase, - nbits_x_in => nbits_wave_in, - nbits_frac_x_in => nbits_wave_in_frac, - nbits_y_in => nbits_wave_in, - nbits_frac_y_in => nbits_wave_in_frac, - nbits_z_in => nbits_phase, - nbits_frac_z_in => nbits_phase_frac, - nbits_x_out => nbits_wave_out, - nbits_frac_x_out => nbits_wave_out_frac, - nbits_y_out => nbits_wave_out, - nbits_frac_y_out => nbits_wave_out_frac, - nbits_z_out => nbits_phase, - nbits_frac_z_out => nbits_phase_frac - ) - PORT MAP - ( - rst => srst, - clk => clk, - vld_in => '1', - xin => xin, - yin => yin, - zin => zin, - xout => xout, - yout => yout, - zout => zout, - vld_out => wave_out_valid - ); - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/nco_cordic_dbg.vhd b/lib/radio/nco/src/nco_cordic_dbg.vhd deleted file mode 100644 index 0f505dd..0000000 --- a/lib/radio/nco/src/nco_cordic_dbg.vhd +++ /dev/null @@ -1,209 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.cordic_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity nco is -Generic -( - nbits_wave : integer := 18; - nbits_wave_frac : integer := 16; - nbits_phase : integer := 16 -); -Port -( - srst : in std_logic; - clk : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic; - debug_out : out debug_out_t -); -end nco; - -architecture Behavioral of nco is - - COMPONENT cordic_pipe_top - GENERIC - ( - cordic_mode : cordic_mode_t; - z_range : real; - gain_corr_mode : gain_corr_mode_t; - nstages : integer; - nbits_x_in : integer; - nbits_y_in : integer; - nbits_z_in : integer; - nbits_frac_x_in : integer; - nbits_frac_y_in : integer; - nbits_frac_z_in : integer; - nbits_x_out : integer; - nbits_y_out : integer; - nbits_z_out : integer; - nbits_frac_x_out : integer; - nbits_frac_y_out : integer; - nbits_frac_z_out : integer - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - vld_in : in std_logic; - xin : in sfixed; - yin : in sfixed; - zin : in sfixed; - xout : out sfixed; - yout : out sfixed; - zout : out sfixed; - vld_out : out std_logic - ); - END COMPONENT; - -------------------------------------------------------------------------------- - constant nbits_phase_frac : integer := nbits_phase; - -------------------------------------------------------------------------------- - signal phase : signed(nbits_phase-1 downto 0); - signal freq_in_r : signed(nbits_phase-1 downto 0); - signal phase_in_r : signed(nbits_phase-1 downto 0); - signal wave_i_ud, wave_q_ud : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)); - - signal wave_ud_valid, phase_vld : std_logic; - - signal zin_ud : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac)); - signal xin : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(0.0, shi(nbits_wave, nbits_wave_frac), slo(nbits_wave, nbits_wave_frac)); - signal yin :sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(1.0, shi(nbits_wave, nbits_wave_frac), slo(nbits_wave, nbits_wave_frac)); - - signal zout_ud : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac)); - -------------------------------------------------------------------------------- -begin - - wave_out_i <= wave_i_ud; - wave_out_q <= wave_q_ud; - out_valid <= wave_ud_valid; - - debug_out.lfsr <= (others => '0'); - debug_out.i_d <= 0.0; - debug_out.q_d <= 0.0; - debug_out.i_ud <= to_real(wave_i_ud); - debug_out.q_ud <= to_real(wave_q_ud); - - ------------------------------------------------------------- - proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r) - variable phase_accu : signed(nbits_phase-1 downto 0); - - begin - if rising_edge(clk) then - phase_vld <= '0'; - if srst = '1' then - phase_accu := (others => '0'); - else - phase_vld <= '1'; - phase <= phase_accu + phase_in_r; - if pacc_clr = '1' then - phase_accu := (others => '0'); - elsif pacc_inc = '1' then - phase_accu := phase_accu + freq_in_r; - end if; - end if; - end if; - phase_out <= unsigned(phase); - zin_ud <= sfixed(phase); - end process; - ------------------------------------------------------------- - freq_in_reg: process(srst, clk, freq_load, freq_in) - begin - if rising_edge(clk) then - if srst = '1' then - freq_in_r <= (others => '0'); - elsif freq_load = '1' then - freq_in_r <= signed(freq_in); - end if; - end if; - end process; - ------------------------------------------------------------- - phase_in_reg: process(srst, clk, phase_load, phase_in) - begin - if rising_edge(clk) then - if srst = '1' then - phase_in_r <= (others => '0'); - elsif phase_load = '1' then - phase_in_r <= signed(phase_in); - end if; - end if; - end process; - ------------------------------------------------------------- - inst_cordic_ud: cordic_pipe_top - GENERIC MAP - ( - cordic_mode => cordic_mode_rotate, - z_range => 1.0, - gain_corr_mode => gain_mode_disabled, - nstages => nbits_phase, - nbits_x_in => nbits_wave, - nbits_frac_x_in => nbits_wave_frac, - nbits_y_in => nbits_wave, - nbits_frac_y_in => nbits_wave_frac, - nbits_z_in => nbits_phase, - nbits_frac_z_in => nbits_phase_frac, - nbits_x_out => nbits_wave, - nbits_frac_x_out => nbits_wave_frac, - nbits_y_out => nbits_wave, - nbits_frac_y_out => nbits_wave_frac, - nbits_z_out => nbits_phase, - nbits_frac_z_out => nbits_phase_frac - ) - PORT MAP - ( - rst => srst, - clk => clk, - vld_in => phase_vld, - xin => xin, - yin => yin, - zin => zin_ud, - xout => wave_i_ud, - yout => wave_q_ud, - zout => zout_ud, - vld_out => wave_ud_valid - ); - ------------------------------------------------------------- -end Behavioral;