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- added SEL_I and multiple write-enables on async port

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git-svn-id: http://moon:8086/svn/vhdl/trunk@256 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-18 21:44:57 +00:00
parent 60bb979bb7
commit 8534d570e0
1 changed files with 10 additions and 5 deletions
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lib/misc/async_port_wb.vhd
+9 -4
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@@ -1,10 +1,10 @@
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.3 2008-10-12 14:12:14 Jens Exp $ -- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.4 2009-01-18 21:44:57 Jens Exp $
----------------------------------------------------------------------- -----------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; use IEEE.NUMERIC_STD.ALL;
use work.sys_types.all; use work.async_types.all;
------------------------------------------------------------------ ------------------------------------------------------------------
entity async_port_wb is entity async_port_wb is
@@ -12,6 +12,7 @@ entity async_port_wb is
( (
addr_width : natural := 32; addr_width : natural := 32;
data_width : natural := 32; data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t async_timespec : async_timespec_t
); );
Port Port
@@ -24,13 +25,14 @@ entity async_port_wb is
ACK_O : out STD_LOGIC; ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC; SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC; MRDY_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ADDR_I : in unsigned(31 downto 0); ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0); DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0); DAT_O : out unsigned(31 downto 0);
async_a : out unsigned(addr_width-1 downto 0); async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0); async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic; async_cs : out std_logic;
async_wr : out std_logic; async_wr : out unsigned(byte_sel_width-1 downto 0);
async_rd : out std_logic; async_rd : out std_logic;
async_rst : out std_logic async_rst : out std_logic
); );
@@ -58,6 +60,7 @@ architecture Behavioral of async_port_wb is
signal rdyo : std_logic; signal rdyo : std_logic;
signal en : std_logic; signal en : std_logic;
signal data_reg : unsigned(data_width-1 downto 0); signal data_reg : unsigned(data_width-1 downto 0);
signal byte_en : unsigned(byte_sel_width-1 downto 0);
------------------------------------------------------------------ ------------------------------------------------------------------
begin begin
@@ -206,7 +209,7 @@ architecture Behavioral of async_port_wb is
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
async_cs <= (not async_timespec.pol_cs) xor as.cs; async_cs <= (not async_timespec.pol_cs) xor as.cs;
async_wr <= (not async_timespec.pol_we) xor as.wr; async_wr <= ((byte_sel_width-1 downto 0 => as.wr) and byte_en) xor (byte_sel_width-1 downto 0 => not async_timespec.pol_we);
async_rd <= (not async_timespec.pol_oe) xor as.rd; async_rd <= (not async_timespec.pol_oe) xor as.rd;
async_rst <= (not async_timespec.pol_rst) xor as.rst; async_rst <= (not async_timespec.pol_rst) xor as.rst;
end if; end if;
@@ -230,8 +233,10 @@ architecture Behavioral of async_port_wb is
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
if RST_I = '1' then if RST_I = '1' then
async_a <= (others => '0'); async_a <= (others => '0');
byte_en <= (others => '0');
elsif en = '1' and rdy = '1' then elsif en = '1' and rdy = '1' then
async_a <= ADDR_I(addr_width-1 downto 0); async_a <= ADDR_I(addr_width-1 downto 0);
byte_en <= SEL_I(byte_sel_width-1 downto 0);
end if; end if;
end if; end if;
end process; end process;