Initial version
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@809 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -0,0 +1,571 @@
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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use std.textio.all; -- Imports the standard textio package.
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use work.emac_types.all;
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use work.utils_pkg.all;
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ENTITY emac_tx IS
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Generic
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(
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f_sysclk : real := 100.0;
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RAM_SIZE : natural := 2048
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);
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Port
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(
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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din : in unsigned(31 downto 0);
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ctrl_in : in tx_ctrl_in_t;
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ctrl_out : out tx_ctrl_out_t;
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mii_tx_clk : in STD_LOGIC;
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mii_tx_en : out STD_LOGIC;
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mii_tx_er : out STD_LOGIC;
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mii_tx : out unsigned(7 downto 0)
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);
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END emac_tx;
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ARCHITECTURE behavior OF emac_tx IS
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constant RAM_ADDR_WIDTH : natural := NextExpBaseTwo(RAM_SIZE);
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subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
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signal fifo_din : unsigned(35 downto 0);
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signal fifo_dout : unsigned(35 downto 0);
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signal fifo_we : std_logic;
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signal fifo_re : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_full : std_logic;
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signal flush_en : std_logic;
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signal flush_rdy : std_logic;
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signal flush_ptr_set : std_logic;
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signal flush_ptr : word_ptr_t;
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signal alloc_req_size : unsigned(15 downto 0);
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signal fill_size : word_ptr_t;
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signal fill_cnt : word_ptr_t;
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signal fill_ptr : word_ptr_t;
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signal fill_rdy : std_logic;
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signal fill_cnt_set : std_logic;
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signal fill_cnt_adv : std_logic;
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signal fill_ptr_set : std_logic;
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signal fill_ptr_adv : std_logic;
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signal fill_remain : unsigned(1 downto 0);
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signal alloc_OK : std_logic;
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signal alloc_req : std_logic;
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signal alloc_ack : std_logic;
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signal nwords_free : word_ptr_t;
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signal alloc_base : word_ptr_t;
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signal alloc_size : word_ptr_t;
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signal alloc_en : std_logic;
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signal free_en : std_logic;
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signal commit_en : std_logic;
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signal uncommit_en : std_logic;
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signal xfer_size : word_ptr_t;
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signal xfer_ptr : word_ptr_t;
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signal xfer_cnt : word_ptr_t;
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signal xfer_ptr_set : std_logic;
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signal xfer_ptr_adv : std_logic;
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signal xfer_cnt_set : std_logic;
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signal xfer_cnt_adv : std_logic;
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signal xfer_rdy : std_logic;
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signal xfer_tag : unsigned(3 downto 0);
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signal xfer_remain : unsigned(1 downto 0);
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signal xfer_odd : std_logic;
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signal xfer_remain_en : std_logic;
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signal ram_en_a : std_logic;
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signal ram_we_a : std_logic;
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signal ram_addr_a : word_ptr_t;
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signal ram_din_a : unsigned(35 downto 0);
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signal ram_dout_a : unsigned(35 downto 0);
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signal ram_en_b : std_logic;
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signal ram_we_b : std_logic;
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signal ram_addr_b : word_ptr_t;
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signal ram_din_b : unsigned(35 downto 0);
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signal ram_dout_b : unsigned(35 downto 0);
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signal piso_din_be : unsigned(3 downto 0);
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signal piso_din_rdy : std_logic;
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signal data_vld : std_logic;
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subtype inter_frame_gap_cnt_t is natural range 0 to natural(1.0*f_sysclk)-1;
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signal inter_frame_gap_cnt : inter_frame_gap_cnt_t;
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signal inter_frame_gap_rdy : std_logic;
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alias ram_data_in_a is ram_din_a(31 downto 0);
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alias ram_tag_in_a is ram_din_a(35 downto 32);
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alias ram_data_out_a is ram_dout_a(31 downto 0);
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alias ram_tag_out_a is ram_dout_a(35 downto 32);
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alias ram_data_in_b is ram_din_b(31 downto 0);
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alias ram_tag_in_b is ram_din_b(35 downto 32);
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alias ram_data_out_b is ram_dout_b(31 downto 0);
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alias ram_tag_out_b is ram_dout_b(35 downto 32);
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type host_state_t is (host_init, host_flush, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
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signal host_s, host_sn : host_state_t;
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type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_wait, xfer_active, xfer_free);
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signal xfer_s, xfer_sn : xfer_state_t;
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type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
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constant piso_byte_mask_rom : piso_byte_mask_array_t :=
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(
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"1111",
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"0001",
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"0011",
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"0111"
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);
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begin
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ctrl_out.alloc_req <= alloc_req;
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mii_tx_er <= ctrl_in.tx_er;
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ram_tag_in_b <= "0000";
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ram_en_b <= not fifo_full or uncommit_en or flush_en;
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ram_we_b <= uncommit_en or flush_en;
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ram_addr_b <= flush_ptr when (flush_en = '1' or uncommit_en = '1') else xfer_ptr;
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xfer_tag <= ram_tag_out_b;
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ram_en_a <= '1';
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ram_we_a <= commit_en or fill_cnt_adv;
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ram_tag_in_a <= fill_remain & "01" when commit_en = '1' else "0000";
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ram_data_in_a <= resize(fill_size, 16) & resize(alloc_base, 16) when commit_en = '1' else din;
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ram_addr_a <= alloc_base when commit_en = '1' else fill_ptr;
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piso_din_be <= (others => '1');
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fifo_re <= piso_din_rdy;
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data_vld <= not fifo_empty;
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fifo_din(35 downto 32) <= piso_byte_mask_rom(to_integer(xfer_remain)) when xfer_remain_en = '1' else "1111";
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fifo_din(31 downto 0) <= ram_data_out_b;
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------------------------------------------------------------------
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host_state_next:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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host_s <= host_init;
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else
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host_s <= host_sn;
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end if;
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end if;
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end process;
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host_state:
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process(host_s, flush_rdy, alloc_req, alloc_OK, fill_rdy, ctrl_in.data_vld)
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begin
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flush_en <= '0';
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flush_ptr_set <= '0';
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alloc_ack <= '0';
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fill_cnt_set <= '0';
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fill_cnt_adv <= '0';
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fill_ptr_set <= '0';
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fill_ptr_adv <= '0';
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commit_en <= '0';
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alloc_en <= '0';
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host_sn <= host_s;
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case host_s is
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when host_init =>
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flush_ptr_set <= '1';
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host_sn <= host_flush;
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when host_flush =>
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flush_en <= '1';
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if flush_rdy = '1' then
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flush_en <= '0';
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host_sn <= host_idle;
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end if;
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when host_idle =>
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if alloc_req = '1' then
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host_sn <= host_alloc;
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end if;
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when host_alloc =>
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if alloc_OK = '1' then
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host_sn <= host_setup;
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alloc_ack <= '1';
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end if;
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when host_setup =>
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fill_cnt_set <= '1';
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fill_ptr_set <= '1';
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host_sn <= host_arm;
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when host_arm =>
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fill_ptr_adv <= '1';
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fill_cnt_adv <= '1';
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host_sn <= host_fill;
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when host_fill =>
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fill_cnt_adv <= ctrl_in.data_vld;
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fill_ptr_adv <= not fill_rdy and ctrl_in.data_vld;
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if alloc_req = '1' then
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host_sn <= host_alloc;
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elsif fill_rdy = '1' then
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host_sn <= host_commit;
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end if;
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when host_commit =>
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commit_en <= '1';
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alloc_en <= '1';
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host_sn <= host_idle;
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when others =>
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host_sn <= host_idle;
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end case;
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end process;
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------------------------------------------------------------------
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-- Allocation stuff
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------------------------------------------------------------------
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alloc_req_size_register:
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process(clk)
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begin
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if rising_edge(clk) then
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if ctrl_in.alloc_req_size_vld = '1' then
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alloc_req_size <= din(15 downto 0);
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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alloc_request_logic:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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alloc_req <= '0';
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elsif ctrl_in.alloc_req_en = '1' and alloc_req = '0' then
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alloc_req <= '1';
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fill_remain <= alloc_req_size(1 downto 0);
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fill_size <= alloc_req_size(word_ptr_t'left+2 downto 2);
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if din(1 downto 0) /= "00" then
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fill_size <= alloc_req_size(word_ptr_t'left+2 downto 2) + 1;
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end if;
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ctrl_out.alloc_req_size <= resize(alloc_req_size(word_ptr_t'left downto 0), 16);
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elsif alloc_ack = '1' then
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alloc_req <= '0';
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alloc_size <= fill_size;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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alloc_base_logic:
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process(clk)
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begin
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if rising_edge(clk) then
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if flush_en = '1' then
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alloc_base <= (others => '0');
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elsif commit_en = '1' then
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alloc_base <= fill_ptr;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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alloc_eval_logic:
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process(clk)
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begin
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if rising_edge(clk) then
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alloc_OK <= '0';
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if alloc_req = '1' then
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if fill_size < nwords_free then
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alloc_OK <= '1';
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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nwords_free_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if flush_en = '1' then
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nwords_free <= (others => '1');
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elsif alloc_en = '1' then
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nwords_free <= nwords_free - fill_size;
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elsif free_en = '1' then
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nwords_free <= nwords_free + xfer_size;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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flush_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if flush_en = '0' then
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flush_rdy <= '0';
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if flush_ptr_set = '1' then
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flush_ptr <= (others => '1');
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elsif xfer_ptr_set = '1' then
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flush_ptr <= ram_data_out_b(flush_ptr'left downto 0);
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end if;
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elsif flush_ptr /= 0 then
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flush_ptr <= flush_ptr - 1;
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else
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flush_rdy <= '1';
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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-- Fill stuff
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------------------------------------------------------------------
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fill_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if fill_cnt_set = '1' then
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fill_rdy <= '0';
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fill_cnt <= alloc_size;
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elsif fill_cnt_adv = '1' then
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if fill_cnt /= 0 then
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fill_cnt <= fill_cnt - 1;
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else
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fill_rdy <= '1';
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end if;
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end if;
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end if;
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end process;
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fill_pointer:
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process(clk)
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begin
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if rising_edge(clk) then
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if fill_ptr_set = '1' then
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fill_ptr <= alloc_base;
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elsif fill_ptr_adv = '1' then
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fill_ptr <= fill_ptr + 1;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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-- Transfer stuff
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------------------------------------------------------------------
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xfer_state_next:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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xfer_s <= xfer_init;
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else
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xfer_s <= xfer_sn;
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end if;
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end if;
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end process;
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xfer_state:
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process(xfer_s, xfer_tag, xfer_odd, xfer_rdy, inter_frame_gap_rdy, alloc_en, fifo_full)
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begin
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xfer_cnt_set <= '0';
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xfer_cnt_adv <= '0';
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xfer_ptr_set <= '0';
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xfer_ptr_adv <= '0';
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xfer_remain_en <= '0';
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fifo_we <= '0';
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free_en <= '0';
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uncommit_en <= '0';
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xfer_sn <= xfer_s;
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case xfer_s is
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when xfer_init =>
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xfer_sn <= xfer_idle;
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when xfer_idle =>
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if xfer_tag(0) = '1' then
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xfer_ptr_set <= '1';
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xfer_cnt_set <= '1';
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xfer_sn <= xfer_wait;
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end if;
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when xfer_wait =>
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if inter_frame_gap_rdy = '1' then
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xfer_sn <= xfer_setup;
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xfer_ptr_adv <= '1';
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xfer_cnt_adv <= '1';
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uncommit_en <= '1';
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end if;
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when xfer_setup =>
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xfer_ptr_adv <= '1';
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xfer_cnt_adv <= '1';
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xfer_sn <= xfer_active;
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when xfer_active =>
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fifo_we <= '1';
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xfer_cnt_adv <= not fifo_full;
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xfer_ptr_adv <= not fifo_full;
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if xfer_rdy = '1' then
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xfer_remain_en <= xfer_odd;
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xfer_cnt_adv <= '0';
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xfer_ptr_adv <= '0';
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if fifo_full = '0' then
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xfer_sn <= xfer_free;
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end if;
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end if;
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when xfer_free =>
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free_en <= not alloc_en;
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if alloc_en = '0' then
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xfer_sn <= xfer_idle;
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end if;
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when others =>
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xfer_sn <= xfer_idle;
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end case;
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end process;
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------------------------------------------------------------------
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interframe_gap_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if flush_en = '1' then
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inter_frame_gap_rdy <= '1';
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elsif fifo_empty = '0' then
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inter_frame_gap_rdy <= '0';
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inter_frame_gap_cnt <= inter_frame_gap_cnt_t'high;
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elsif inter_frame_gap_cnt /= 0 then
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inter_frame_gap_cnt <= inter_frame_gap_cnt - 1;
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else
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inter_frame_gap_rdy <= '1';
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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xfer_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if xfer_cnt_set = '1' then
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xfer_size <= (others => '0');
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xfer_rdy <= '0';
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xfer_cnt <= ram_data_out_b(xfer_ptr'left+16 downto 16);
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elsif xfer_cnt_adv = '1' then
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if xfer_cnt /= 0 then
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xfer_cnt <= xfer_cnt - 1;
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xfer_size <= xfer_size + 1;
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else
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xfer_rdy <= '1';
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end if;
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end if;
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end if;
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end process;
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xfer_pointer:
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process(clk)
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begin
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if rising_edge(clk) then
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if xfer_ptr_set = '1' then
|
||||
xfer_ptr <= ram_data_out_b(xfer_ptr'left downto 0);
|
||||
xfer_remain <= xfer_tag(3 downto 2);
|
||||
xfer_odd <= '0';
|
||||
if xfer_tag(3 downto 2) /= "00" then
|
||||
xfer_odd <= '1';
|
||||
end if;
|
||||
elsif xfer_ptr_adv = '1' then
|
||||
xfer_ptr <= xfer_ptr + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
inst_ram : entity work.dpram_2w2r
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => RAM_ADDR_WIDTH,
|
||||
data_width => 36
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
clk_b => clk,
|
||||
en_a => ram_en_a,
|
||||
en_b => ram_en_b,
|
||||
we_a => ram_we_a,
|
||||
we_b => ram_we_b,
|
||||
addr_a => ram_addr_a,
|
||||
addr_b => ram_addr_b,
|
||||
din_a => ram_din_a,
|
||||
din_b => ram_din_b,
|
||||
dout_a => ram_dout_a,
|
||||
dout_b => ram_dout_b
|
||||
);
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_fifo: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 4,
|
||||
data_width => 36,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_w => clk,
|
||||
clk_r => mii_tx_clk,
|
||||
we => fifo_we,
|
||||
re => fifo_re,
|
||||
fifo_full => fifo_full,
|
||||
fifo_empty => fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => fifo_din,
|
||||
data_r => fifo_dout
|
||||
);
|
||||
|
||||
inst_piso : entity work.piso
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width_in => 32,
|
||||
data_width_out => 8,
|
||||
msb_first => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => mii_tx_clk,
|
||||
din_vld => data_vld,
|
||||
din_rdy => piso_din_rdy,
|
||||
din_be => fifo_dout(35 downto 32),
|
||||
din => fifo_dout(31 downto 0),
|
||||
dout_en => mii_tx_en,
|
||||
dout => mii_tx
|
||||
|
||||
);
|
||||
|
||||
end behavior;
|
||||
Reference in New Issue
Block a user