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git-svn-id: http://moon:8086/svn/vhdl/trunk@809 cc03376c-175c-47c8-b038-4cd826a8556b

lib/emac/src/emac_top_jb.vhd

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+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.emac_types.all;
+use work.utils_pkg.all;
+
+ENTITY emac_top_jb IS
+	Generic
+	(
+		f_sysclk	: real		:= 100.0;
+		TX_RAM_SIZE	: natural	:= 2048;
+		RX_RAM_SIZE	: natural	:= 2048
+	);
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		INT_O		: out STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		mii_rx_clk	: in  STD_LOGIC;
+		mii_rx_dv	: in  STD_LOGIC;
+		mii_rx_er	: in  STD_LOGIC;
+		mii_rx		: in unsigned(7 downto 0);
+		mii_tx_clk	: in  STD_LOGIC;
+		mii_tx_en	: out STD_LOGIC;
+		mii_tx_er	: out STD_LOGIC;
+		mii_tx		: out unsigned(7 downto 0);
+		mii_gtx_clk	: out STD_LOGIC;
+		mii_crs		: in  STD_LOGIC;
+		mii_col		: in  STD_LOGIC
+		
+	);
+END emac_top_jb;
+
+ARCHITECTURE behavior OF emac_top_jb IS
+
+	-- Signals for EMAC connections
+	signal tx_ctrl_in		: tx_ctrl_in_t;
+	signal tx_ctrl_out		: tx_ctrl_out_t;
+	signal tx_din			: unsigned(31 downto 0);
+
+	signal rx_ctrl_in		: rx_ctrl_in_t;
+	signal rx_ctrl_out		: rx_ctrl_out_t;
+	signal rx_dout			: unsigned(31 downto 0);
+	
+	signal rx_int_en		: std_logic;
+	signal tx_int_en		: std_logic;
+	signal irq_rx			: std_logic;
+	signal irq_tx			: std_logic;
+
+	signal if_rdy			: std_logic;
+begin
+
+	SRDY_O				<= CYC_I and if_rdy;
+	INT_O				<= irq_rx or irq_tx;
+	mii_gtx_clk			<= '0';
+
+------------------------------------------------------------------
+registers_write: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if_rdy			<= '1';
+			tx_ctrl_in.data_vld					<= '0';
+			tx_ctrl_in.alloc_req_size_vld		<= '0';
+			tx_ctrl_in.alloc_req_en				<= '0';
+			if RST_I = '1' then
+				rx_int_en			<= '0';
+				tx_int_en			<= '0';
+				tx_ctrl_in.tx_er	<= '0';
+		elsif (STB_I and CYC_I and WE_I) = '1' then
+				case ADDR_I(5 downto 2) is
+				
+				when "0000" =>
+					tx_ctrl_in.tx_er			<= DAT_I(31);
+					tx_ctrl_in.alloc_req_en		<= DAT_I(16);
+					tx_int_en					<= DAT_I(5);
+					rx_int_en					<= DAT_I(4);
+					
+				when "0001" => 
+					if_rdy			<= '0';		-- allow request size to propagate inside TX module
+					tx_ctrl_in.alloc_req_size_vld	<= '1';
+					tx_din							<= X"0000" & DAT_I(31 downto 16);
+					
+				when "0010" =>
+					tx_ctrl_in.data_vld		<= '1';
+					tx_din					<= DAT_I;
+					
+				when others => null;
+				end case;
+			end if;	
+		end if;	
+	end process;
+
+registers_read: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			ACK_O			<= '0';
+			if (STB_I and CYC_I) = '1' then
+				ACK_O		<= not WE_I;
+				DAT_O		<= (others => '0');
+				case ADDR_I(5 downto 2) is
+
+				when "0000" =>
+					DAT_O(31)	<= tx_ctrl_in.tx_er;
+					DAT_O(30)	<= mii_rx_er;
+					DAT_O(29)	<= mii_col;
+					DAT_O(28)	<= mii_crs;
+					DAT_O(16)	<= tx_ctrl_out.alloc_req;
+					DAT_O(5)	<= tx_int_en;
+					DAT_O(4)	<= rx_int_en;
+
+				when "0001" => 
+					DAT_O(31 downto 16)	<= tx_ctrl_out.alloc_req_size(15 downto 0);
+
+				when "0010" =>
+
+				when others => null;
+				end case;
+			end if;
+		end if;	
+	end process;
+
+irq_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			irq_tx		<= tx_int_en;
+			irq_rx		<= rx_int_en;
+		end if;
+	end process;
+
+inst_emac_rx : entity work.emac_rx
+	GENERIC MAP
+	(
+		f_sysclk	=> f_sysclk,
+		RAM_SIZE	=> RX_RAM_SIZE
+	)
+	PORT MAP
+	(
+		clk			=> CLK_I,
+		rst			=> RST_I,
+		dout		=> rx_dout,
+		ctrl_in		=> rx_ctrl_in,
+		ctrl_out	=> rx_ctrl_out,
+		mii_rx_clk	=> mii_rx_clk,
+		mii_rx_dv	=> mii_rx_dv,
+		mii_rx_er	=> mii_rx_er,
+		mii_rx		=> mii_rx,
+		mii_crs		=> mii_crs,
+		mii_col		=> mii_col
+		
+	);
+
+
+inst_emac_tx : entity work.emac_tx
+	GENERIC MAP
+	(
+		f_sysclk	=> f_sysclk,
+		RAM_SIZE	=> TX_RAM_SIZE
+	)
+	PORT MAP
+	(
+		clk			=> CLK_I,
+		rst			=> RST_I,
+		din			=> tx_din,
+		ctrl_in		=> tx_ctrl_in,
+		ctrl_out	=> tx_ctrl_out,
+		mii_tx_clk	=> mii_tx_clk,
+		mii_tx_en	=> mii_tx_en,
+		mii_tx_er	=> mii_tx_er,
+		mii_tx		=> mii_tx
+		
+	);
+
+
+end behavior;