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[J-Uart]

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- fixed receiver


git-svn-id: http://moon:8086/svn/vhdl/trunk@1363 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2017-01-05 10:56:59 +00:00
parent 9d420b16d4
commit 84363d2734
2 changed files with 24 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/uart/juart_rx.vhd
+23 -33
View File
@@ -47,7 +47,6 @@ architecture behavior of juart_rx is
constant OVERSAMPLING : natural := 16; constant OVERSAMPLING : natural := 16;
subtype bit_count_t is natural range 0 to OVERSAMPLING-1; subtype bit_count_t is natural range 0 to OVERSAMPLING-1;
subtype idle_count_t is natural range 0 to OVERSAMPLING-1;
signal bit_count_rst : std_logic; signal bit_count_rst : std_logic;
signal bit_count : bit_count_t; signal bit_count : bit_count_t;
@@ -55,9 +54,7 @@ signal data_valid : std_logic;
signal shiftreg_en : std_logic; signal shiftreg_en : std_logic;
signal shiftreg : unsigned (7 downto 0); signal shiftreg : unsigned (7 downto 0);
signal sample_count_rst : std_logic; signal sample_count_rst : std_logic;
signal sample_count : unsigned (OVERSAMPLING-1 downto 0); signal sample_count : natural range 0 to OVERSAMPLING-1;
signal idle_count : idle_count_t;
signal is_idle : std_logic;
signal bit_sample : std_logic; signal bit_sample : std_logic;
type state_t is (idle, wait_start, start, shift, stop); type state_t is (idle, wait_start, start, shift, stop);
@@ -68,9 +65,6 @@ signal state_next : state_t;
-- --
begin begin
bit_sample <= sample_count(OVERSAMPLING/2) and en_16_x_baud;
is_idle <= '1' when idle_count = 0 else '0';
data_out_reg: data_out_reg:
process(clk) process(clk)
begin begin
@@ -96,39 +90,39 @@ begin
end process; end process;
statemachine: statemachine:
process(state, is_idle, bit_count, bit_sample, ser_in) process(state, bit_count, bit_sample, ser_in)
begin begin
state_next <= state; state_next <= state;
sample_count_rst <= '1'; sample_count_rst <= '0';
bit_count_rst <= '1'; bit_count_rst <= '0';
shiftreg_en <= '0'; shiftreg_en <= '0';
data_valid <= '0'; data_valid <= '0';
case state is case state is
when idle => when idle =>
if is_idle = '1' then if ser_in = '1' then
state_next <= wait_start; state_next <= wait_start;
end if; end if;
when wait_start => when wait_start =>
sample_count_rst <= '1';
if ser_in = '0' then if ser_in = '0' then
sample_count_rst <= '0';
state_next <= start; state_next <= start;
end if; end if;
when start => when start =>
sample_count_rst <= '0'; bit_count_rst <= '1';
if bit_sample = '1' then if bit_sample = '1' then
state_next <= shift; state_next <= shift;
end if; end if;
when shift => when shift =>
shiftreg_en <= '1'; shiftreg_en <= '1';
sample_count_rst <= '0';
bit_count_rst <= '0';
if bit_count = 8 then if bit_count = 8 then
state_next <= stop; state_next <= stop;
end if; end if;
when stop => when stop =>
state_next <= idle; if bit_sample = '1' then
data_valid <= '1'; state_next <= idle;
data_valid <= '1';
end if;
when others => when others =>
state_next <= idle; state_next <= idle;
@@ -141,7 +135,7 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
shiftreg <= (others => '0'); shiftreg <= (others => '0');
elsif shiftreg_en = '1' and bit_sample = '1' and en_16_x_baud = '1' then elsif shiftreg_en = '1' and bit_sample = '1' then
shiftreg <= ser_in & shiftreg(shiftreg'left downto 1); shiftreg <= ser_in & shiftreg(shiftreg'left downto 1);
end if; end if;
end if; end if;
@@ -151,10 +145,18 @@ sample_counter:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
bit_sample <= '0';
if sample_count_rst = '1' then if sample_count_rst = '1' then
sample_count <= (sample_count'left downto 1 => '0') & '1'; sample_count <= 0;
elsif en_16_x_baud = '1' then elsif en_16_x_baud = '1' then
sample_count <= sample_count(sample_count'left-1 downto 0) & sample_count(sample_count'left); if sample_count /= OVERSAMPLING-1 then
sample_count <= sample_count + 1;
else
sample_count <= 0;
end if;
if sample_count = OVERSAMPLING/2-1 then
bit_sample <= '1';
end if;
end if; end if;
end if; end if;
end process; end process;
@@ -165,24 +167,12 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
if bit_count_rst = '1' then if bit_count_rst = '1' then
bit_count <= 0; bit_count <= 0;
elsif bit_count /= bit_count_t'high and bit_sample = '1' and en_16_x_baud = '1' then elsif bit_count /= bit_count_t'high and bit_sample = '1' then
bit_count <= bit_count + 1; bit_count <= bit_count + 1;
end if; end if;
end if; end if;
end process; end process;
idle_detector:
process(clk)
begin
if rising_edge(clk) then
if ser_in = '0' then
idle_count <= idle_count_t'high;
elsif idle_count /= 0 and en_16_x_baud = '1' then
idle_count <= idle_count - 1;
end if;
end if;
end process;
end behavior; end behavior;
------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------
lib/uart/sim/tb_juart_rx.wdo
+1 -3
View File
@@ -11,16 +11,14 @@ add wave -noupdate -format Logic /tb_juart_rx/dut/bit_sample
add wave -noupdate -format Literal -radix unsigned /tb_juart_rx/dut/bit_count add wave -noupdate -format Literal -radix unsigned /tb_juart_rx/dut/bit_count
add wave -noupdate -format Literal -radix unsigned /tb_juart_rx/dut/shiftreg add wave -noupdate -format Literal -radix unsigned /tb_juart_rx/dut/shiftreg
add wave -noupdate -format Literal /tb_juart_rx/dut/sample_count add wave -noupdate -format Literal /tb_juart_rx/dut/sample_count
add wave -noupdate -format Logic /tb_juart_rx/dut/is_idle
add wave -noupdate -format Literal /tb_juart_rx/dut/state add wave -noupdate -format Literal /tb_juart_rx/dut/state
add wave -noupdate -format Literal /tb_juart_rx/dut/state_next add wave -noupdate -format Literal /tb_juart_rx/dut/state_next
add wave -noupdate -format Literal /tb_juart_rx/dut/idle_count
add wave -noupdate -format Logic /tb_juart_rx/dut/bit_count_rst add wave -noupdate -format Logic /tb_juart_rx/dut/bit_count_rst
add wave -noupdate -format Logic /tb_juart_rx/dut/sample_count_rst add wave -noupdate -format Logic /tb_juart_rx/dut/sample_count_rst
add wave -noupdate -format Logic /tb_juart_rx/dut/dout_vld add wave -noupdate -format Logic /tb_juart_rx/dut/dout_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_juart_rx/dout add wave -noupdate -format Literal -radix hexadecimal /tb_juart_rx/dout
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {5936632 ps} 0} WaveRestoreCursors {{Cursor 1} {3761310 ps} 0}
configure wave -namecolwidth 150 configure wave -namecolwidth 150
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left