- Cleaned up

git-svn-id: http://moon:8086/svn/vhdl/trunk@122 cc03376c-175c-47c8-b038-4cd826a8556b
2008-10-25 18:09:39 +00:00
parent 9954268b22
commit 84255df928
4 changed files with 2455 additions and 2455 deletions
@@ -27,9 +27,9 @@ vhdl work "../../src/bootloader.ROM_ld.vhd"
 vhdl work "../../../../lib/uart/uart_tx.vhd"
 vhdl work "../../../../lib/uart/uart_rx.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/linefifo.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
 vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
 vhdl work "../../../../lib/uart/uart_wb.vhd"
 vhdl work "../../../../lib/misc/rom_wb.vhd"
@@ -38,6 +38,6 @@ vhdl work "../../../../lib/misc/lcd_port.vhd"
 vhdl work "../../../../lib/misc/gpio_wb.vhd"
 vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
 vhdl work "../../../../lib/misc/async_port_wb.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
 vhdl work "../../src/mips_sys.vhd"
@@ -27,9 +27,9 @@ vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\linefifo.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
 vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
@@ -38,6 +38,6 @@ vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
 vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
 vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
 vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend_wb.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"