From 83a9b4c4172eb9b6956b2a8a70daafadef96c32f Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 6 Jan 2009 21:20:29 +0000 Subject: [PATCH] - changed iterative CFIR wirh semi-parallel version git-svn-id: http://moon:8086/svn/vhdl/trunk@212 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/radio/ddc/sim/tb_ddc.fdo | 7 +- lib/radio/ddc/sim/tb_ddc.wdo | 16 ++-- lib/radio/ddc/src/ddc.vhd | 166 ++++++++++++++++++++--------------- 3 files changed, 107 insertions(+), 82 deletions(-) diff --git a/lib/radio/ddc/sim/tb_ddc.fdo b/lib/radio/ddc/sim/tb_ddc.fdo index c6f3d19..f19c02a 100644 --- a/lib/radio/ddc/sim/tb_ddc.fdo +++ b/lib/radio/ddc/sim/tb_ddc.fdo @@ -3,11 +3,12 @@ vmap ieee_proposed ../../../../Common/sim/ieee_proposed vlib work vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd" vcom -explicit -93 "../../../misc/utils_pkg.vhd" +vcom -explicit -93 "../../../misc/dpram_1w1r.vhd" vcom -explicit -93 "../../../filter/src/filter_pkg.vhd" -vcom -explicit -93 "../../../filter/src/fir_stage_pkg.vhd" -vcom -explicit -93 "../../../filter/src/fir_iterative_pkg.vhd" +vcom -explicit -93 "../../../filter/src/fir_pkg.vhd" vcom -explicit -93 "../../../filter/src/fir_stage_sys.vhd" -vcom -explicit -93 "../../../filter/src/fir_iterative.vhd" +vcom -explicit -93 "../../../filter/src/delay_line.vhd" +vcom -explicit -93 "../../../filter/src/fir_semi_parallel.vhd" vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" vcom -explicit -93 "../../cordic/src/cordic_pkg.vhd" diff --git a/lib/radio/ddc/sim/tb_ddc.wdo b/lib/radio/ddc/sim/tb_ddc.wdo index e515c3e..a849e62 100644 --- a/lib/radio/ddc/sim/tb_ddc.wdo +++ b/lib/radio/ddc/sim/tb_ddc.wdo @@ -77,18 +77,22 @@ add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_q_out_ add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_i_out_f add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_q_out_f add wave -noupdate -divider CFIR -add wave -noupdate -format Literal /tb_ddc/uut/cfir_dout_i -add wave -noupdate -format Literal /tb_ddc/uut/cfir_dout_q +add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_dout_i +add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_dout_q add wave -noupdate -format Logic /tb_ddc/uut/cfir_vld_i add wave -noupdate -format Logic /tb_ddc/uut/cfir_vld_q add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_i add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_q -add wave -noupdate -format Literal /tb_ddc/uut/dec_dout_i -add wave -noupdate -format Literal /tb_ddc/uut/dec_dout_q +add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_i +add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_q add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_i add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_q +add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_h_data +add wave -noupdate -format Literal /tb_ddc/uut/cfir_h_addr +add wave -noupdate -format Logic /tb_ddc/uut/cfir_h_we +add wave -noupdate -format Logic /tb_ddc/uut/hclr_mode TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {199990000 ps} 0} +WaveRestoreCursors {{Cursor 1} {186030000 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -102,4 +106,4 @@ configure wave -gridperiod 100 configure wave -griddelta 40 configure wave -timeline 1 update -WaveRestoreZoom {1566606200 ps} {2022810200 ps} +WaveRestoreZoom {183411575 ps} {200873075 ps} diff --git a/lib/radio/ddc/src/ddc.vhd b/lib/radio/ddc/src/ddc.vhd index 2f3edc1..0c948a6 100644 --- a/lib/radio/ddc/src/ddc.vhd +++ b/lib/radio/ddc/src/ddc.vhd @@ -21,10 +21,10 @@ use ieee_proposed.math_utility_pkg.all; use ieee_proposed.fixed_pkg.all; library work; +use work.utils_pkg.all; use work.fixed_util_pkg.all; use work.filter_pkg.all; -use work.fir_stage_pkg.all; -use work.fir_iterative_pkg.all; +use work.fir_pkg.all; ENTITY ddc IS Generic @@ -111,31 +111,31 @@ ARCHITECTURE behavior OF ddc IS ); END COMPONENT; - COMPONENT fir_iterative + COMPONENT fir_semi_parallel GENERIC ( - ntaps : integer; + ntaps_per_stage : integer; + nstages : integer; + mul_latency : integer; nbits_in : integer; nbits_in_frac : integer; nbits_stages : integer; nbits_stages_frac : integer; nbits_out : integer; - nbits_out_frac : integer; - fir_mode : fir_iterative_mode_t; - rounding : boolean; - saturating : boolean + nbits_out_frac : integer ); PORT ( - srst : in std_logic; - clk : in std_logic; - h_din : in sfixed; - h_addr_out : out natural; - ready : out std_logic; - x_valid : in std_logic; - x_din : in sfixed; - y_dout_valid : out std_logic; - y_dout : out sfixed + rst : in std_logic; + clk : in std_logic; + h_addr : in natural range 0 to nstages*ntaps_per_stage-1; + h_we : in std_logic; + h_in : in sfixed; + din_vld : in std_logic; + din : in sfixed; + dout_vld : out std_logic; + rdy : out std_logic; + dout : out sfixed ); END COMPONENT; @@ -149,8 +149,9 @@ ARCHITECTURE behavior OF ddc IS constant cic_nbits_out : integer := nbits_out+1; constant cic_nbits_out_frac : integer := nbits_out_frac+1; - constant cfir_mode : fir_iterative_mode_t := symmetric; - constant cfir_ntaps : integer := 31; + constant cfir_mul_latency : integer := 2; + constant cfir_ntaps : integer := 63; + constant cfir_nstages : integer := 2; constant cfir_nbits_in : integer := cic_nbits_out; constant cfir_nbits_in_frac : integer := cic_nbits_out_frac; constant cfir_nbits_out : integer := nbits_out; @@ -158,20 +159,19 @@ ARCHITECTURE behavior OF ddc IS constant cfir_nbits_stages : integer := cfir_nbits_in; constant cfir_nbits_stages_frac : integer := cfir_nbits_in_frac; - constant ntaps_needed : integer := ntaps_addr(cfir_ntaps, cfir_mode); + constant cfir_ntaps_per_stage : integer := NextPowerOfTwo(cfir_ntaps)/cfir_nstages; - SIGNAL cfir_h_din_i : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac)); - SIGNAL cfir_h_din_q : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac)); - SIGNAL cfir_h_addr_i : natural range 0 to ntaps_needed-1; - SIGNAL cfir_h_addr_q : natural range 0 to ntaps_needed-1; + SIGNAL cfir_h_data : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac)); + SIGNAL cfir_h_addr : natural range 0 to NextPowerOfTwo(cfir_ntaps)-1; SIGNAL cfir_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); SIGNAL cfir_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); + SIGNAL cfir_h_we : std_logic; SIGNAL cfir_vld_i : std_logic; SIGNAL cfir_vld_q : std_logic; SIGNAL cfir_ready_i : std_logic; SIGNAL cfir_ready_q : std_logic; - constant cfir_coef : real_array_t(0 to ntaps_addr(cfir_ntaps, cfir_mode)-1) := FilterCoef_Lowpass(cfir_ntaps, 0.1, 1.0)(0 to ntaps_addr(cfir_ntaps, cfir_mode)-1); + constant cfir_coef : real_array_t(0 to cfir_ntaps-1) := FilterCoef_Lowpass(cfir_ntaps, 0.1, 1.0); type h_mem_t is array (0 to cfir_ntaps-1) of sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac)); @@ -185,8 +185,8 @@ ARCHITECTURE behavior OF ddc IS return res; end to_h_mem; - CONSTANT h_mem_i : h_mem_t := to_h_mem(cfir_coef, ntaps_needed, cfir_h_din_i); - CONSTANT h_mem_q : h_mem_t := to_h_mem(cfir_coef, ntaps_needed, cfir_h_din_q); + SIGNAL hclr_mode : std_logic; + CONSTANT h_mem : h_mem_t := to_h_mem(cfir_coef, cfir_ntaps, cfir_h_data); SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); @@ -277,74 +277,94 @@ BEGIN vld_out => dec_dout_vld_q ); - cfir_I: entity work.fir_iterative + cfir_I : entity work.fir_semi_parallel GENERIC MAP ( - ntaps => cfir_ntaps, + ntaps_per_stage => cfir_ntaps_per_stage, + nstages => cfir_nstages, + mul_latency => cfir_mul_latency, nbits_in => cfir_nbits_in, nbits_in_frac => cfir_nbits_in_frac, - nbits_out => cfir_nbits_out, - nbits_out_frac => cfir_nbits_out_frac, nbits_stages => cfir_nbits_stages, nbits_stages_frac => cfir_nbits_stages_frac, - fir_mode => cfir_mode, - rounding => false, - saturating => false + nbits_out => cfir_nbits_out, + nbits_out_frac => cfir_nbits_out_frac ) PORT MAP ( - srst => rst, - clk => clk, - h_din => cfir_h_din_i, - h_addr_out => cfir_h_addr_i, - ready => cfir_ready_i, - x_valid => dec_dout_vld_i, - x_din => dec_dout_i, - y_dout_valid => cfir_vld_i, - y_dout => cfir_dout_i + rst => rst, + clk => clk, + h_addr => cfir_h_addr, + h_we => cfir_h_we, + h_in => cfir_h_data, + din_vld => dec_dout_vld_i, + din => dec_dout_i, + dout_vld => cfir_vld_i, + rdy => cfir_ready_i, + dout => cfir_dout_i ); - - cfir_Q: entity work.fir_iterative + + cfir_Q : entity work.fir_semi_parallel GENERIC MAP ( - ntaps => cfir_ntaps, + ntaps_per_stage => cfir_ntaps_per_stage, + nstages => cfir_nstages, + mul_latency => cfir_mul_latency, nbits_in => cfir_nbits_in, nbits_in_frac => cfir_nbits_in_frac, - nbits_out => cfir_nbits_out, - nbits_out_frac => cfir_nbits_out_frac, nbits_stages => cfir_nbits_stages, nbits_stages_frac => cfir_nbits_stages_frac, - fir_mode => cfir_mode, - rounding => false, - saturating => false + nbits_out => cfir_nbits_out, + nbits_out_frac => cfir_nbits_out_frac ) PORT MAP ( - srst => rst, - clk => clk, - h_din => cfir_h_din_q, - h_addr_out => cfir_h_addr_q, - ready => cfir_ready_q, - x_valid => dec_dout_vld_q, - x_din => dec_dout_q, - y_dout_valid => cfir_vld_q, - y_dout => cfir_dout_q + rst => rst, + clk => clk, + h_addr => cfir_h_addr, + h_we => cfir_h_we, + h_in => cfir_h_data, + din_vld => dec_dout_vld_q, + din => dec_dout_q, + dout_vld => cfir_vld_q, + rdy => cfir_ready_q, + dout => cfir_dout_q ); - -cfir_coef_mem_i: + +coef_load_counter: process(clk) + variable count : natural range 0 to NextPowerOfTwo(cfir_ntaps)-1; + variable we : std_logic; begin if rising_edge(clk) then - cfir_h_din_i <= h_mem_i(cfir_h_addr_i); - end if; - end process; - -cfir_coef_mem_q: - process(clk) - begin - if rising_edge(clk) then - cfir_h_din_q <= h_mem_q(cfir_h_addr_q); - end if; - end process; + cfir_h_addr <= count; + cfir_h_we <= we; + if rst = '1' then + we := '1'; + hclr_mode <= '1'; + count := 0; + else + if hclr_mode = '1' then + cfir_h_data <= to_sfixed(0.0, cfir_h_data); + if count /= NextPowerOfTwo(cfir_ntaps)-1 then + we := '1'; + count := count + 1; + else + count := 0; + hclr_mode <= '0'; + end if; + else + cfir_h_data <= h_mem(count); + if count /= cfir_ntaps-1 then + we := '1'; + count := count + 1; + else + we := '0'; + end if; + end if; + end if; + end if; + end process; + END;