diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
index e3a7e5e..1a09d8e 100644
--- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
@@ -772,12 +772,12 @@ proc_stage_MEM_mux:
 	variable be : unsigned(3 downto 0);
 	begin
 		data	:= MEM_stage.ex_result;
-		be		:= load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp);
 		if MEM_stage.ctrl.reg_link = '1' then
 			data		:= MEM_stage.epc + 8;
 		elsif MEM_stage.ctrl.dmem_en = '1' then
 			temp1		:= load_shift(dmem_din,  MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp);
 			temp2		:= load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en);
+			be			:= load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp);
 			if be(0) = '1' then
 				data(7 downto 0)	:= temp2(7 downto 0);
 			end if;