diff --git a/lib/CPUs/MIPS/dist/tmpl/notes.txt b/lib/CPUs/MIPS/dist/tmpl/notes.txt
index e059343..04057c7 100644
--- a/lib/CPUs/MIPS/dist/tmpl/notes.txt
+++ b/lib/CPUs/MIPS/dist/tmpl/notes.txt
@@ -28,6 +28,12 @@ Changes in release 12
 - Status register bit 'RE'= 1 (bit 25) reverses endianess in user-mode
 - Status register bit 'TS' (TLB Shutdown, bit 21) is tied high to indicate the absence of a MMU.
 - uart_wb.vhd: added interrupt enable
+- Interrupt pending flags (IP) are not anymore masked by Interrupt mask flags (IM) in H/W. 
+  Masking has to be done in S/W. H/W masking was removed because it isn't MIPS-compliant. 
+- added NMI pin (more MIPS compliant). Asserting causes exception. Exception vector is reset (0xBFC00000). 
+  Using NMI as reset is dangerous because periphery is not reseted. 
+  Unitialized/unreseted periphery may cause trouble (e.g. firing unwanted interrupts) 
+- Bootloader: Startup now invalidates I/D-Caches at boot
 
 -----------------------------------------------------------------
 Changes in release 11