diff --git a/lib/CPUs/MIPS/dist/tmpl/notes.txt b/lib/CPUs/MIPS/dist/tmpl/notes.txt
index 04057c7..4008125 100644
--- a/lib/CPUs/MIPS/dist/tmpl/notes.txt
+++ b/lib/CPUs/MIPS/dist/tmpl/notes.txt
@@ -34,6 +34,14 @@ Changes in release 12
   Using NMI as reset is dangerous because periphery is not reseted. 
   Unitialized/unreseted periphery may cause trouble (e.g. firing unwanted interrupts) 
 - Bootloader: Startup now invalidates I/D-Caches at boot
+- Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect. Newlib's memcpy() (MIPS-optimized) uses this.
+  Consectutive load instructions without nops (which is legal) using same target register like
+   lw $1, 0(mem)
+   lwl $1, 1(mem)
+  or
+   lwl $1, 0(mem)
+   lwr $1, 1(mem)
+  or similar, lead to incorrect result. Now it'S fixed.
 
 -----------------------------------------------------------------
 Changes in release 11