diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd
index 67194a1..34e36a0 100644
--- a/projects/mips_sys/src/mips_sys_sim.vhd
+++ b/projects/mips_sys/src/mips_sys_sim.vhd
@@ -32,7 +32,6 @@ use UNISIM.vcomponents.all;
 
 library work;
 use work.mips_types.all;
---use work.fifo_ctrl_pkg.all;
 use work.sdram_config.all;
 use work.sdram_types.all;
 use work.vga_types.all;
@@ -44,8 +43,7 @@ ENTITY mips_sys IS
 GENERIC
 (
 	sys_freq_in			: real		    	:= 100.0;
-	sys_freq			: real				:= 125.0;
-	sdram_freq			: real				:= 125.0;
+	sys_freq			: real				:= 100.0;
 	sdram_phaseshift	: integer			:= 0;
 	tsvga				: vga_timespec_t 	:= ts_vga_800_600_72
 
@@ -1014,7 +1012,7 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
 	(
 		BL				=> BURST_LEN,
 		f_sysclk		=> sys_freq,
-		f_sdrclk		=> sdram_freq,
+		f_sdrclk		=> sys_freq,
 		fifo_depth		=> 5
 	)
 	PORT MAP