diff --git a/projects/mips_sys/sim/tb_mips_sys.fdo b/projects/mips_sys/sim/tb_mips_sys.fdo
index e4c7d53..2b6b81f 100644
--- a/projects/mips_sys/sim/tb_mips_sys.fdo
+++ b/projects/mips_sys/sim/tb_mips_sys.fdo
@@ -23,6 +23,7 @@ vcom -explicit  -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
 vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync.vhd"
 vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync_dist.vhd"
 vcom -explicit  -93 "../../../lib/FIFO/src/async_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_async.vhd"
 
 # CPU
 vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd"
@@ -45,14 +46,12 @@ vcom -explicit  -93 "../../../lib/misc/rom_wb.vhd"
 # VGA
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/dpram.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/linefifo.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_frontend.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
 
 # UART
 vcom -explicit  -93 "../../../lib/uart/bbfifo_16x8.vhd"
@@ -85,7 +84,7 @@ vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
 vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
 vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
 vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
 
 # Top and TB
 vcom -explicit  -93 "../src/mips_sys_sim.vhd"
diff --git a/projects/mips_sys/sim/tb_mips_sys.wdo b/projects/mips_sys/sim/tb_mips_sys.wdo
index e1f1514..5b90b51 100644
--- a/projects/mips_sys/sim/tb_mips_sys.wdo
+++ b/projects/mips_sys/sim/tb_mips_sys.wdo
@@ -13,11 +13,11 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
 add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
 add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
 add wave -noupdate -format Logic /tb_mips_sys/refresh
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr
 add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
 add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
 add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
@@ -31,15 +31,15 @@ add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
 add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_dm_wr_in
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_tag_in
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_tag_rd
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_tag_wr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_data_r
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_data_vld
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/u_data_req_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/read_fifo_data_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/read_fifo_data_out
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/u_dm_wr_in
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/u_tag_in
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/u_tag_rd
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/u_tag_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/u_data_r
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/u_data_vld
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/inst_sdram_ctrl/u_data_req_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/read_fifo_data_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/read_fifo_data_out
 add wave -noupdate -format Literal /tb_mips_sys/sys_error
 add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
@@ -83,20 +83,33 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_vga
 add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_vga
 add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga
 add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_full
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_empty
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_almost_empty
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_almost_full
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/request_cnt
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/read_cnt
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/s
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/vga_master_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/vga_scan_rdy
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_color_re
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_color_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/fifo_color_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/fifo_color_in
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/scan_rdy
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/fifo_full
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/fifo_empty
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/fifo_almost_empty
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/fifo_almost_full
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend64/request_cnt
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend64/read_cnt
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend64/s
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/vga_master_en
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/vga_scan_rdy
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/fifo_color_re
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/fifo_color_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend64/fifo_color_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend64/fifo_color_in
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/scan_rdy
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_vga_frontend64/color_in
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/stat_scan
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend64/stat_hpos
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend64/stat_vpos
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend64/odd_pixel
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/we_w
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/re_r
+add wave -noupdate -format Literal -radix unsigned /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/ptr_w
+add wave -noupdate -format Literal -radix unsigned /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/ptr_r
+add wave -noupdate -format Literal -radix unsigned /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/inst_fifo_ctrl/gcnt_r
+add wave -noupdate -format Literal -radix unsigned /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/inst_fifo_ctrl/bcnt_r
+add wave -noupdate -format Literal -radix unsigned /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/inst_fifo_ctrl/gnxt_r
+add wave -noupdate -format Literal -radix unsigned /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/inst_fifo_ctrl/bnxt_r
 add wave -noupdate -divider BUI
 add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_icache
@@ -253,10 +266,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_din
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_rdy
 add wave -noupdate -divider {User ROM}
-add wave -noupdate -format Logic /tb_mips_sys/sys_user_rom_clk
-add wave -noupdate -format Logic /tb_mips_sys/sys_user_rom_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_addr
 add wave -noupdate -divider UUT
 add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
@@ -331,7 +340,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_re
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_we
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {971060308 ps} 0}
+WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {2346072600 ps} 0}
 configure wave -namecolwidth 218
 configure wave -valuecolwidth 130
 configure wave -justifyvalue left
@@ -345,4 +354,4 @@ configure wave -gridperiod 100
 configure wave -griddelta 40
 configure wave -timeline 1
 update
-WaveRestoreZoom {970843856 ps} {971236215 ps}
+WaveRestoreZoom {8083733091 ps} {8083879943 ps}