From 8054aedcb58e4a37afd4b3837d5ed2e9e8c37ccc Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Fri, 20 Mar 2009 20:27:23 +0000 Subject: [PATCH] - Update Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@408 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/sim/tb_mips_top.wdo | 246 ++++++++++++++++++++++++++---- 1 file changed, 219 insertions(+), 27 deletions(-) diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo index a7a3287..0588232 100644 --- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo +++ b/lib/CPUs/MIPS/sim/tb_mips_top.wdo @@ -44,31 +44,223 @@ add wave -noupdate -divider PC add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc add wave -noupdate -divider COP0 -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/inst_cop/events -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/inst_cop/ctrl_in -add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_pipeline/inst_cop/ctrl_out -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_cop/epc -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_cop/cause -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_cop/status -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_cop/badvaddr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_cop/exc_code -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/stat_reg_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/eflags_reg_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/epc_reg_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/code_reg_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/ip_reg_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/bd -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/status_save -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/status_rest -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/exception -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/exception_end -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/inst_cop/eflags -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/exc_enable -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/cop_ex_en -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/inst_cop/cop_pipe_id -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/inst_cop/cop_pipe_ex -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/inst_cop/exc_state -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/inst_cop/exc_staten +add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/ir_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ir +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/test_reg +add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/test_reg_we +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/icache_info +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dcache_info +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_id +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_ex +add wave -noupdate -divider Pipestages +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage +add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst +add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem +add wave -noupdate -divider I-Cache +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/s +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_busy +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_miss +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/word_index_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_index_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_index_reg +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_reg_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/was_miss +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count +add wave -noupdate -divider D-Cache +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcached +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/tram_addr_rd +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/tram_addr_wr +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tram_we +add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_busy +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/word_index_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/addr_windex_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_index_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_index_reg +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_rdy +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_rdy +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_rdy +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_reg_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/was_miss +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw +add wave -noupdate -divider {TOP interface} +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal /tb_mips_top/debug +add wave -noupdate -format Logic /tb_mips_top/stb_o +add wave -noupdate -format Logic /tb_mips_top/ack_i +add wave -noupdate -format Logic /tb_mips_top/srdy_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o +add wave -noupdate -format Logic /tb_mips_top/we_o +add wave -noupdate -format Literal /tb_mips_top/sel_o +add wave -noupdate -format Logic /tb_mips_top/cyc_o +add wave -noupdate -format Logic /tb_mips_top/mrdy_o +add wave -noupdate -format Literal /tb_mips_top/int +add wave -noupdate -divider {External components} +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1 +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic /tb_mips_top/rx +add wave -noupdate -format Logic /tb_mips_top/tx +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal /tb_mips_top/mem_area +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d +add wave -noupdate -format Logic /tb_mips_top/flash_cs_n +add wave -noupdate -format Logic /tb_mips_top/flash_oe_n +add wave -noupdate -format Literal /tb_mips_top/flash_be_n +add wave -noupdate -format Logic /tb_mips_top/sram_cs_n +add wave -noupdate -format Literal /tb_mips_top/sram_wr_n +add wave -noupdate -format Logic /tb_mips_top/sram_oe_n +add wave -noupdate -format Literal /tb_mips_top/sram_be_n +add wave -noupdate -divider ALU +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu +add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_pipeline/sdu +add wave -noupdate -divider PC +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc +add wave -noupdate -divider COP0 +add wave -noupdate -divider Pipestages +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage +add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst +add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem +add wave -noupdate -divider I-Cache +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/s +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_busy +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_miss +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/word_index_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_index_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_index_reg +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_reg_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/was_miss +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count +add wave -noupdate -divider D-Cache +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/tram_addr_rd +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/tram_addr_wr +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tram_we +add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_busy +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/word_index_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/addr_windex_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_index_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_index_reg +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_rdy +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_rdy +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_rdy +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_reg_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/was_miss +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw +add wave -noupdate -divider {TOP interface} +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal /tb_mips_top/debug +add wave -noupdate -format Logic /tb_mips_top/stb_o +add wave -noupdate -format Logic /tb_mips_top/ack_i +add wave -noupdate -format Logic /tb_mips_top/srdy_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o +add wave -noupdate -format Logic /tb_mips_top/we_o +add wave -noupdate -format Literal /tb_mips_top/sel_o +add wave -noupdate -format Logic /tb_mips_top/cyc_o +add wave -noupdate -format Logic /tb_mips_top/mrdy_o +add wave -noupdate -format Literal /tb_mips_top/int +add wave -noupdate -divider {External components} +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1 +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic /tb_mips_top/rx +add wave -noupdate -format Logic /tb_mips_top/tx +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal /tb_mips_top/mem_area +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d +add wave -noupdate -format Logic /tb_mips_top/flash_cs_n +add wave -noupdate -format Logic /tb_mips_top/flash_oe_n +add wave -noupdate -format Literal /tb_mips_top/flash_be_n +add wave -noupdate -format Logic /tb_mips_top/sram_cs_n +add wave -noupdate -format Literal /tb_mips_top/sram_wr_n +add wave -noupdate -format Logic /tb_mips_top/sram_oe_n +add wave -noupdate -format Literal /tb_mips_top/sram_be_n +add wave -noupdate -divider ALU +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu +add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_pipeline/sdu +add wave -noupdate -divider PC +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc +add wave -noupdate -divider COP0 add wave -noupdate -divider Pipestages add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage @@ -130,7 +322,7 @@ add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/was_miss add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {2127774 ps} 0} +WaveRestoreCursors {{Cursor 1} {2248160 ps} 0} configure wave -namecolwidth 188 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -144,4 +336,4 @@ configure wave -gridperiod 100 configure wave -griddelta 40 configure wave -timeline 1 update -WaveRestoreZoom {0 ps} {5031559 ps} +WaveRestoreZoom {2141949 ps} {2449858 ps}