diff --git a/lib/JBUS/src/busmaster_sync.vhd b/lib/JBUS/src/busmaster_sync.vhd
index b003685..692f636 100644
--- a/lib/JBUS/src/busmaster_sync.vhd
+++ b/lib/JBUS/src/busmaster_sync.vhd
@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.4 2013-07-21 09:10:13 jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.5 2013-07-21 09:21:17 jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -123,9 +123,9 @@ proc_bus_read_counter:
 		if rising_edge(clk) then
 			if rst = '1' then
 				read_cnt	<= 0;
-			elsif cmd_read_en = '1' and dout_re = '0' then
+			elsif cmd_read_en = '1' and read_fifo_empty = '1' then
 				read_cnt <= read_cnt + 1;
-			elsif cmd_read_en = '0' and dout_re = '1' and read_fifo_empty = '0' then
+			elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then
 				read_cnt <= read_cnt - 1;
 			end if;	
 		end if;