From 7f91449b9440e46931b1441bbceef59a319f73f9 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 7 Jan 2017 15:34:40 +0000 Subject: [PATCH] [DE0-Nano] - added 2nd uart git-svn-id: http://moon:8086/svn/vhdl/trunk@1364 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_de0_nano/quartus/mips/JMips.qsf | 6 +- .../mips_de0_nano/quartus/mips/mips_sys.vhd | 87 ++++++++++++++----- 2 files changed, 67 insertions(+), 26 deletions(-) diff --git a/projects/mips_de0_nano/quartus/mips/JMips.qsf b/projects/mips_de0_nano/quartus/mips/JMips.qsf index c77e7b6..790b662 100644 --- a/projects/mips_de0_nano/quartus/mips/JMips.qsf +++ b/projects/mips_de0_nano/quartus/mips/JMips.qsf @@ -307,6 +307,8 @@ set_global_assignment -name VHDL_FILE mips_sys.vhd set_global_assignment -name VHDL_FILE ../../../../../repos/lib/misc/jtag_reg_alt.vhd set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_rx set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_tx -set_location_assignment PIN_D3 -to uart_rx -set_location_assignment PIN_C3 -to uart_tx +set_location_assignment PIN_D3 -to uart_rx[0] +set_location_assignment PIN_A3 -to uart_rx[1] +set_location_assignment PIN_C3 -to uart_tx[0] +set_location_assignment PIN_B4 -to uart_tx[1] set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/projects/mips_de0_nano/quartus/mips/mips_sys.vhd b/projects/mips_de0_nano/quartus/mips/mips_sys.vhd index 0ec0d2c..bac2d21 100644 --- a/projects/mips_de0_nano/quartus/mips/mips_sys.vhd +++ b/projects/mips_de0_nano/quartus/mips/mips_sys.vhd @@ -60,8 +60,8 @@ ENTITY mips_sys IS spi_miso : in std_logic; spi_mosi : out std_logic; - uart_rx : in std_logic; - uart_tx : out std_logic; + uart_rx : in unsigned(1 downto 0); + uart_tx : out unsigned(1 downto 0); sys_leds : out unsigned(7 downto 0) ); @@ -100,10 +100,15 @@ ARCHITECTURE behavior OF mips_sys IS signal SRDY_O_gpio : std_logic; signal DAT_O_gpio : unsigned(31 downto 0); - signal CYC_I_uart : std_logic; - signal ACK_O_uart : std_logic; - signal SRDY_O_uart : std_logic; - signal DAT_O_uart : unsigned(31 downto 0); + signal CYC_I_uart0 : std_logic; + signal ACK_O_uart0 : std_logic; + signal SRDY_O_uart0 : std_logic; + signal DAT_O_uart0 : unsigned(31 downto 0); + + signal CYC_I_uart1 : std_logic; + signal ACK_O_uart1 : std_logic; + signal SRDY_O_uart1 : std_logic; + signal DAT_O_uart1 : unsigned(31 downto 0); signal CYC_I_flash : std_logic; signal ACK_O_flash : std_logic; @@ -115,10 +120,11 @@ ARCHITECTURE behavior OF mips_sys IS signal cpu_tx_data_vld : std_logic; signal int_timer : std_logic; - signal int_uart : std_logic; + signal int_uart0 : std_logic; + signal int_uart1 : std_logic; signal int_flash : std_logic; - type mem_area_t is (mem_dead, mem_flash, mem_ram, mem_rom, mem_gpio, mem_uart); + type mem_area_t is (mem_dead, mem_flash, mem_ram, mem_rom, mem_gpio, mem_uart0, mem_uart1); signal mem_area : mem_area_t; signal gpo0 : unsigned(31 downto 0); @@ -205,7 +211,9 @@ mem_mux: if ADDR_O(18 downto 16) = "000" then mem_area <= mem_gpio; elsif ADDR_O(18 downto 16) = "001" then - mem_area <= mem_uart; + mem_area <= mem_uart0; + elsif ADDR_O(18 downto 16) = "011" then + mem_area <= mem_uart1; end if; elsif ADDR_O(27 downto 26) = "01" then mem_area <= mem_flash; @@ -222,7 +230,8 @@ signal_mux: begin CYC_I_gpio <= '0'; - CYC_I_uart <= '0'; + CYC_I_uart0 <= '0'; + CYC_I_uart1 <= '0'; CYC_I_flash <= '0'; CYC_I_rom <= '0'; CYC_I_ram <= '0'; @@ -232,8 +241,11 @@ signal_mux: when mem_gpio => CYC_I_gpio <= CYC_O; - when mem_uart => - CYC_I_uart <= CYC_O; + when mem_uart0 => + CYC_I_uart0 <= CYC_O; + + when mem_uart1 => + CYC_I_uart1 <= CYC_O; when mem_flash => CYC_I_flash <= CYC_O; @@ -250,11 +262,12 @@ signal_mux: end process; - SRDY_I <= SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_flash or SRDY_O_gpio; - ACK_I <= ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_flash or ACK_O_gpio; + SRDY_I <= SRDY_O_ram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_flash or SRDY_O_gpio; + ACK_I <= ACK_O_ram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_flash or ACK_O_gpio; DAT_I <= DAT_O_ram when CYC_I_ram = '1' else DAT_O_rom when CYC_I_rom = '1' else - DAT_O_uart when CYC_I_uart = '1' else + DAT_O_uart0 when CYC_I_uart0 = '1' else + DAT_O_uart1 when CYC_I_uart1 = '1' else DAT_O_flash when CYC_I_flash = '1' else DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; @@ -286,7 +299,7 @@ inst_mips_top: entity work.mips_top INT => INT ); - INT <= "000" & int_flash & int_uart & int_timer; + INT <= "00" & int_flash & int_uart1 & int_uart0 & int_timer; inst_rom : entity work.rom_wb PORT MAP @@ -327,7 +340,7 @@ inst_gpio : entity work.gpio_wb sys_gpo_0 => gpo0 ); -inst_uart : entity work.uart_wb +inst_uart0 : entity work.uart_wb GENERIC MAP ( f_sysclk => F_SYSCLK, @@ -338,19 +351,45 @@ inst_uart : entity work.uart_wb ( CLK_I => sys_clk, RST_I => sys_rst, - CYC_I => CYC_I_uart, + CYC_I => CYC_I_uart0, STB_I => STB_O, SEL_I => SEL_O, WE_I => WE_O, - ACK_O => ACK_O_uart, - SRDY_O => SRDY_O_uart, + ACK_O => ACK_O_uart0, + SRDY_O => SRDY_O_uart0, MRDY_I => MRDY_O, ADDR_I => ADDR_O, DAT_I => DAT_O, - DAT_O => DAT_O_uart, - INT_O => int_uart, - ser_rx => uart_rx, - ser_tx => uart_tx + DAT_O => DAT_O_uart0, + INT_O => int_uart0, + ser_rx => uart_rx(0), + ser_tx => uart_tx(0) + ); + +inst_uart1 : entity work.uart_wb + GENERIC MAP + ( + f_sysclk => F_SYSCLK, + baudrate_default => 115200.0, + fifo_depth_bits => 1 + ) + PORT MAP + ( + CLK_I => sys_clk, + RST_I => sys_rst, + CYC_I => CYC_I_uart1, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_O_uart1, + SRDY_O => SRDY_O_uart1, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_O_uart1, + INT_O => int_uart1, + ser_rx => uart_rx(1), + ser_tx => uart_tx(1) ); inst_spi_flash : entity work.spi_flash_wb