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- added asynchronous BUS FIFOs

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- added cpu_clk
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git-svn-id: http://moon:8086/svn/vhdl/trunk@724 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 19:01:33 +00:00
parent fd84fecaec
commit 7f8a82d9ba
2 changed files with 29 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/src/core/mips_bui.vhd
+24 -21
View File
@@ -51,6 +51,7 @@ entity biu is
STB_O : out STD_LOGIC; STB_O : out STD_LOGIC;
MRDY_O : out STD_LOGIC; MRDY_O : out STD_LOGIC;
cop0_ctrl_in : in cop0_ctrl_out_t; cop0_ctrl_in : in cop0_ctrl_out_t;
cpu_clk : in STD_LOGIC;
cpu_imem_err : out STD_LOGIC; cpu_imem_err : out STD_LOGIC;
cpu_imem_rdy : out STD_LOGIC; cpu_imem_rdy : out STD_LOGIC;
cpu_imem_en : in STD_LOGIC; cpu_imem_en : in STD_LOGIC;
@@ -206,9 +207,9 @@ architecture behavior of biu is
begin begin
read_cyc_register: read_cyc_register:
process(CLK_I) process(cpu_clk)
begin begin
if rising_edge(CLK_I) then if rising_edge(cpu_clk) then
if RST_I = '1' then if RST_I = '1' then
read_cycle <= '0'; read_cycle <= '0';
else else
@@ -239,7 +240,7 @@ inst_icache : icache
) )
PORT MAP PORT MAP
( (
CLK_I => CLK_I, CLK_I => cpu_clk,
RST_I => RST_I, RST_I => RST_I,
STB_O => STB_O_icache, STB_O => STB_O_icache,
CYC_O => CYC_O_icache, CYC_O => CYC_O_icache,
@@ -264,7 +265,7 @@ inst_dcache : dcache
) )
PORT MAP PORT MAP
( (
CLK_I => CLK_I, CLK_I => cpu_clk,
RST_I => RST_I, RST_I => RST_I,
CYC_O => CYC_O_dcache, CYC_O => CYC_O_dcache,
STB_O => STB_O_dcache, STB_O => STB_O_dcache,
@@ -289,7 +290,7 @@ inst_dcache : dcache
dcache_en <= dcached and cpu_dmem_en and dcache_en2; -- or write_busy); dcache_en <= dcached and cpu_dmem_en and dcache_en2; -- or write_busy);
-- Instantiate synchronous FIFO -- Instantiate synchronous FIFO
inst_bin_fifo: entity work.fifo_sync inst_bin_fifo: entity work.fifo_async
GENERIC MAP GENERIC MAP
( (
addr_width => 4, addr_width => 4,
@@ -298,7 +299,8 @@ inst_bin_fifo: entity work.fifo_sync
PORT MAP PORT MAP
( (
rst => RST_I, rst => RST_I,
clk => CLK_I, clk_w => CLK_I,
clk_r => cpu_clk,
we => bin_fifo_we, we => bin_fifo_we,
re => bin_fifo_re, re => bin_fifo_re,
fifo_full => bin_fifo_full, fifo_full => bin_fifo_full,
@@ -316,7 +318,7 @@ inst_bin_fifo: entity work.fifo_sync
bin_fifo_re <= read_cycle; bin_fifo_re <= read_cycle;
-- Instantiate synchronous FIFO -- Instantiate synchronous FIFO
inst_bout_fifo: entity work.fifo_sync inst_bout_fifo: entity work.fifo_async
GENERIC MAP GENERIC MAP
( (
addr_width => 4, addr_width => 4,
@@ -325,7 +327,8 @@ inst_bout_fifo: entity work.fifo_sync
PORT MAP PORT MAP
( (
rst => RST_I, rst => RST_I,
clk => CLK_I, clk_w => cpu_clk,
clk_r => CLK_I,
we => bout_fifo_we, we => bout_fifo_we,
re => bout_fifo_re, re => bout_fifo_re,
fifo_full => bout_fifo_full, fifo_full => bout_fifo_full,
@@ -362,7 +365,7 @@ inst_write_fifo: entity work.fifo_sync
PORT MAP PORT MAP
( (
rst => RST_I, rst => RST_I,
clk => CLK_I, clk => cpu_clk,
we => write_fifo_we, we => write_fifo_we,
re => write_fifo_re, re => write_fifo_re,
fifo_full => write_busy, fifo_full => write_busy,
@@ -385,9 +388,9 @@ inst_write_fifo: entity work.fifo_sync
write_fifo_we <= cpu_dmem_en and not busy and cpu_dmem_we; write_fifo_we <= cpu_dmem_en and not busy and cpu_dmem_we;
dmem_rd_flags: dmem_rd_flags:
process(CLK_I) process(cpu_clk)
begin begin
if rising_edge(CLK_I) then if rising_edge(cpu_clk) then
uncached_access <= '0'; uncached_access <= '0';
if RST_I = '1' then if RST_I = '1' then
CYC_O_dmem_rd <= '0'; CYC_O_dmem_rd <= '0';
@@ -409,9 +412,9 @@ dmem_rd_flags:
end process; end process;
dmem_rd_data: dmem_rd_data:
process(CLK_I) process(cpu_clk)
begin begin
if rising_edge(CLK_I) then if rising_edge(cpu_clk) then
if RST_I = '1' then if RST_I = '1' then
DAT_I_dmem_rd <= (others => '0'); DAT_I_dmem_rd <= (others => '0');
elsif ACK = '1' and CYC_O_dmem_rd = '1' then elsif ACK = '1' and CYC_O_dmem_rd = '1' then
@@ -421,9 +424,9 @@ dmem_rd_data:
end process; end process;
dmem_rd_regs: dmem_rd_regs:
process(CLK_I) process(cpu_clk)
begin begin
if rising_edge(CLK_I) then if rising_edge(cpu_clk) then
if cpu_dmem_en = '1' and busy = '0' then if cpu_dmem_en = '1' and busy = '0' then
ADDR_O_dmem_rd <= cpu_dmem_addr; ADDR_O_dmem_rd <= cpu_dmem_addr;
SEL_O_dmem_rd <= cpu_dmem_be; SEL_O_dmem_rd <= cpu_dmem_be;
@@ -432,9 +435,9 @@ dmem_rd_regs:
end process; end process;
bus_state_next: bus_state_next:
process(CLK_I) process(cpu_clk)
begin begin
if rising_edge(CLK_I) then if rising_edge(cpu_clk) then
if RST_I = '1' then if RST_I = '1' then
s <= init; s <= init;
else else
@@ -506,9 +509,9 @@ bus_state:
end process; end process;
bus_timeout_counter: bus_timeout_counter:
process(CLK_I) process(cpu_clk)
begin begin
if rising_edge(CLK_I) then if rising_edge(cpu_clk) then
if bus_idle = '0' then if bus_idle = '0' then
if bus_timeout_cnt /= 0 then if bus_timeout_cnt /= 0 then
bus_timeout_cnt <= bus_timeout_cnt - 1; bus_timeout_cnt <= bus_timeout_cnt - 1;
@@ -523,9 +526,9 @@ bus_timeout_counter:
end process; end process;
bus_err: bus_err:
process(CLK_I) process(cpu_clk)
begin begin
if rising_edge(CLK_I) then if rising_edge(cpu_clk) then
if RST_I = '1' then if RST_I = '1' then
cpu_imem_err <= '0'; cpu_imem_err <= '0';
cpu_dmem_err <= '0'; cpu_dmem_err <= '0';
lib/CPUs/MIPS/src/core/mips_top.vhd
+5 -2
View File
@@ -41,6 +41,7 @@ entity mips_top is
debug : out unsigned(1 downto 0); debug : out unsigned(1 downto 0);
eb : in STD_LOGIC; eb : in STD_LOGIC;
nmi : in STD_LOGIC; nmi : in STD_LOGIC;
cpu_clk : in STD_LOGIC;
RST_I : in STD_LOGIC; RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC; CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC; ACK_I : in STD_LOGIC;
@@ -168,6 +169,7 @@ architecture rtl of mips_top is
STB_O : out STD_LOGIC; STB_O : out STD_LOGIC;
MRDY_O : out STD_LOGIC; MRDY_O : out STD_LOGIC;
cop0_ctrl_in : in cop0_ctrl_out_t; cop0_ctrl_in : in cop0_ctrl_out_t;
cpu_clk : in STD_LOGIC;
cpu_imem_err : out STD_LOGIC; cpu_imem_err : out STD_LOGIC;
cpu_imem_rdy : out STD_LOGIC; cpu_imem_rdy : out STD_LOGIC;
cpu_imem_en : in STD_LOGIC; cpu_imem_en : in STD_LOGIC;
@@ -218,7 +220,7 @@ inst_pipeline: pipeline
PORT MAP PORT MAP
( (
rst => cpu_rst, rst => cpu_rst,
clk => CLK_I, clk => cpu_clk,
ce => cpu_run, ce => cpu_run,
imem_err => imem_err, imem_err => imem_err,
imem_rdy => imem_rdy, imem_rdy => imem_rdy,
@@ -252,7 +254,7 @@ inst_cop: cop
PORT MAP PORT MAP
( (
rst => cpu_rst, rst => cpu_rst,
clk => CLK_I, clk => cpu_clk,
nmi => nmi, nmi => nmi,
eb => eb, eb => eb,
int => INT, int => INT,
@@ -287,6 +289,7 @@ inst_biu: biu
STB_O => STB_O, STB_O => STB_O,
MRDY_O => MRDY_O, MRDY_O => MRDY_O,
cop0_ctrl_in => pipe_c0_ctrl_in, cop0_ctrl_in => pipe_c0_ctrl_in,
cpu_clk => cpu_clk,
cpu_imem_err => imem_err, cpu_imem_err => imem_err,
cpu_imem_rdy => imem_rdy, cpu_imem_rdy => imem_rdy,
cpu_imem_en => imem_en, cpu_imem_en => imem_en,