jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- added pin fcs_gen_en to append fcs for packet generator

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@896 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-04-09 09:01:10 +00:00
parent e7f4a5642a
commit 7f6678d85a
1 changed files with 7 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/emac/src/tb_emac_top_jb.vhd
+7 -5
View File
@@ -75,6 +75,7 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
signal pktgen_tx_er : std_logic; signal pktgen_tx_er : std_logic;
signal pktgen_en : std_logic := '0'; signal pktgen_en : std_logic := '0';
signal pktgen_gigabit : std_logic := '0'; signal pktgen_gigabit : std_logic := '0';
signal pktgen_fcs_en : std_logic := '0';
signal dat_o_cnt_en : std_logic := '0'; signal dat_o_cnt_en : std_logic := '0';
signal dat_o_cnt_rst : std_logic := '1'; signal dat_o_cnt_rst : std_logic := '1';
signal dat_o_cnt : natural; signal dat_o_cnt : natural;
@@ -141,6 +142,7 @@ inst_pkt_gen : entity work.pkt_gen
rst => RST, rst => RST,
en => pktgen_en, en => pktgen_en,
gigabit_en => pktgen_gigabit, gigabit_en => pktgen_gigabit,
fcs_gen_en => pktgen_fcs_en,
mii_tx_clk => mii_tx_clk_board, mii_tx_clk => mii_tx_clk_board,
mii_tx_en => pktgen_tx_en, mii_tx_en => pktgen_tx_en,
mii_tx_er => pktgen_tx_er, mii_tx_er => pktgen_tx_er,
@@ -201,7 +203,7 @@ STIMULUS: process
CYC_I <= '1'; CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"8000_0000"; DAT_I <= X"A000_0000";
STB_I <= '1'; STB_I <= '1';
WE_I <= '1'; WE_I <= '1';
ADDR_I <= TX_STATUS_REG_ADDR; ADDR_I <= TX_STATUS_REG_ADDR;
@@ -216,7 +218,7 @@ STIMULUS: process
CYC_I <= '1'; CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"8000_0000"; DAT_I <= X"A000_0000";
STB_I <= '1'; STB_I <= '1';
WE_I <= '1'; WE_I <= '1';
ADDR_I <= RX_STATUS_REG_ADDR; ADDR_I <= RX_STATUS_REG_ADDR;
@@ -231,7 +233,7 @@ STIMULUS: process
CYC_I <= '1'; CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"C000_0000"; DAT_I <= X"E000_0000";
STB_I <= '1'; STB_I <= '1';
WE_I <= '1'; WE_I <= '1';
ADDR_I <= TX_STATUS_REG_ADDR; ADDR_I <= TX_STATUS_REG_ADDR;
@@ -246,7 +248,7 @@ STIMULUS: process
CYC_I <= '1'; CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"C000_0000"; DAT_I <= X"E000_0000";
STB_I <= '1'; STB_I <= '1';
WE_I <= '1'; WE_I <= '1';
ADDR_I <= RX_STATUS_REG_ADDR; ADDR_I <= RX_STATUS_REG_ADDR;
@@ -505,7 +507,7 @@ STIMULUS: process
emac_rx_reset_1000mbps; emac_rx_reset_1000mbps;
emac_tx_reset_1000mbps; emac_tx_reset_1000mbps;
pktgen_gigabit <= '1'; pktgen_gigabit <= '1';
pktgen_fcs_en <= '1';
wait for 60*CLK_PERIOD; wait for 60*CLK_PERIOD;
emac_alloc (1004); emac_alloc (1004);