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- fixed cpu_rst

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1567 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-29 09:10:34 +00:00
parent 51899a014d
commit 7efce56819
3 changed files with 19 additions and 23 deletions
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projects/vga_ctrl/ghdl/tb_vga_ctrl.make
+1 -1
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@@ -19,7 +19,7 @@ SRCS += ../src/tb_vga_ctrl.vhd
# Compile # Compile
TARGET := tb_vga_ctrl TARGET := tb_vga_ctrl
ENTITY := tb_vga_ctrl ENTITY := tb_vga_ctrl
RUN_TIME := 2500us RUN_TIME := 250us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
projects/vga_ctrl/src/tb_vga_ctrl.vhd
+2 -2
View File
@@ -68,7 +68,7 @@ ARCHITECTURE behavior OF tb_vga_ctrl IS
END COMPONENT; END COMPONENT;
--Constants --Constants
constant PERIOD : time := 9.9304865938430983118172790466733 ns; constant PERIOD : time := 10 ns;
--Inputs --Inputs
SIGNAL sys_rst_in : std_logic := '1'; SIGNAL sys_rst_in : std_logic := '1';
@@ -139,7 +139,7 @@ BEGIN
BEGIN BEGIN
-- Wait 100 ns for global reset to finish -- Wait 100 ns for global reset to finish
wait for 20*PERIOD; wait for 100*PERIOD;
sys_rst_in <= '0'; sys_rst_in <= '0';
wait for PERIOD; wait for PERIOD;
projects/vga_ctrl/src/vga_ctrl_top.vhd
+16 -20
View File
@@ -61,15 +61,8 @@ architecture Behavioral of vga_ctrl_top is
signal vga_clk : std_logic; signal vga_clk : std_logic;
-- Timing -- Timing
signal scan_rdy_h : std_logic;
signal scan_rdy_v : std_logic;
signal vga_scan_x : std_logic;
signal vga_scan_y : std_logic;
signal src_pos_x : natural range 0 to tsvga.ts_h.ncyc_scan-1; signal src_pos_x : natural range 0 to tsvga.ts_h.ncyc_scan-1;
signal src_pos_y : natural range 0 to tsvga.ts_v.ncyc_scan-1; signal src_pos_y : natural range 0 to tsvga.ts_v.ncyc_scan-1;
signal vga_pos_x : natural range 0 to tsvga.ts_h.ncyc_scan-1;
signal vga_pos_y : natural range 0 to tsvga.ts_v.ncyc_scan-1;
-- Backend signals -- Backend signals
signal scan_rdy : std_logic; signal scan_rdy : std_logic;
@@ -246,9 +239,10 @@ inst_vga_backend : entity work.vga_backend
rst <= sys_rst_in; rst <= sys_rst_in;
clk <= sys_clk_in; clk <= sys_clk_in;
scan_rdy <= scan_rdy_h and scan_rdy_v; scan_rdy <= stat_vga_rdy;
cg_en <= vga_scan_x and vga_scan_y; cg_en <= stat_scan;
cg_draw <= stat_scan;
cpu_ce <= '1'; cpu_ce <= '1';
--------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------
@@ -343,12 +337,14 @@ cpu_reg_write:
--------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------
--- Test --- Test
--------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------
cpu_start: process (rst, vga_clk) cpu_start: process (clk)
begin begin
if (rst = '1') then if rising_edge(vga_clk) then
cpu_rst <= '1'; if rst = '1' then
elsif rising_edge(vga_clk) and scan_rdy = '1' then cpu_rst <= '1';
cpu_rst <= '0'; else
cpu_rst <= not scan_rdy;
end if;
end if; end if;
end process; end process;
@@ -359,14 +355,14 @@ cpu_reg_write:
end if; end if;
end process; end process;
color_ctrl: process (rst, clk) color_ctrl: process (clk)
variable enable : std_logic; variable enable : std_logic;
begin begin
if (rst = '1') then if rising_edge(clk) then
src_pos_x <= 0; if (rst = '1') then
src_pos_y <= 0; src_pos_x <= 0;
elsif rising_edge(clk) then src_pos_y <= 0;
if stat_scan = '1' then elsif stat_scan = '1' then
if src_pos_x < tsvga.ts_h.ncyc_scan-1 then if src_pos_x < tsvga.ts_h.ncyc_scan-1 then
src_pos_x <= src_pos_x + 1; src_pos_x <= src_pos_x + 1;
else else