diff --git a/lib/CPUs/MIPS/src/core/dcache.vhd b/lib/CPUs/MIPS/src/core/dcache.vhd index a93dd68..c70bc47 100644 --- a/lib/CPUs/MIPS/src/core/dcache.vhd +++ b/lib/CPUs/MIPS/src/core/dcache.vhd @@ -344,13 +344,13 @@ cache_state: sn <= mem_access; end if; when mem_access => - data_write <= '1'; - CYC_O <= '1'; - if SRDY_I = '1' then - mem_index_count_en <= '1'; - STB_O <= '1'; - if mem_index_count = 2**word_index_width-1 then - sn <= mem_data; + data_write <= '1'; + mem_index_count_en <= '1'; + CYC_O <= '1'; + STB_O <= '1'; + if mem_index_count = 2**word_index_width-1 then + if SRDY_I = '1' then + sn <= mem_data; end if; end if; when mem_data => @@ -419,7 +419,7 @@ mem_index_counter: if rising_edge(CLK_I) then if mem_index_count_rst = '1' then mem_index_count <= 0; - elsif mem_index_count_en = '1' then + elsif mem_index_count_en = '1' and SRDY_I = '1' then if mem_index_count /= 2**word_index_width-1 then mem_index_count <= mem_index_count + 1; end if; diff --git a/lib/CPUs/MIPS/src/core/icache.vhd b/lib/CPUs/MIPS/src/core/icache.vhd index 7506aac..81dd77e 100644 --- a/lib/CPUs/MIPS/src/core/icache.vhd +++ b/lib/CPUs/MIPS/src/core/icache.vhd @@ -278,12 +278,12 @@ cache_state: sn <= mem_access; end if; when mem_access => + mem_index_count_en <= '1'; data_write <= '1'; CYC_O <= '1'; - if SRDY_I = '1' then - mem_index_count_en <= '1'; - STB_O <= '1'; - if mem_index_count = 2**word_index_width-1 then + STB_O <= '1'; + if mem_index_count = 2**word_index_width-1 then + if SRDY_I = '1' then sn <= mem_data; end if; end if; @@ -345,7 +345,7 @@ mem_index_counter: if rising_edge(CLK_I) then if mem_index_count_rst = '1' then mem_index_count <= 0; - elsif mem_index_count_en = '1' then + elsif mem_index_count_en = '1' and SRDY_I = '1' then if mem_index_count /= 2**word_index_width-1 then mem_index_count <= mem_index_count + 1; end if;