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- Removed linefifo

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- Uses now lib/FIFO/fifo_async.vhd


git-svn-id: http://moon:8086/svn/vhdl/trunk@107 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-25 11:15:26 +00:00
parent 5abe0f9234
commit 7ccefbab86
1 changed files with 11 additions and 13 deletions
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lib/VGA_ctrl/src/vga_frontend.vhd
+11 -13
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@@ -85,8 +85,8 @@ architecture Behavioral of vga_frontend is
signal fifo_almost_full : std_logic; signal fifo_almost_full : std_logic;
signal fifo_color_re : std_logic; signal fifo_color_re : std_logic;
signal fifo_color_we : std_logic; signal fifo_color_we : std_logic;
signal fifo_color_out : color_t; signal fifo_color_out : unsigned(31 downto 0);
signal fifo_color_in : color_t; signal fifo_color_in : unsigned(31 downto 0);
-- Backend signals -- Backend signals
signal scan_rdy : std_logic; signal scan_rdy : std_logic;
@@ -183,15 +183,16 @@ inst_vga_backend : entity work.vga_backend
ctrl_scan_en <= '1'; ctrl_scan_en <= '1';
color_en(0) <= not fifo_empty; color_en(0) <= not fifo_empty;
color_en(1) <= cg_draw; color_en(1) <= cg_draw;
color_in(0) <= fifo_color_out; color_in(0) <= to_color_t(fifo_color_out);
color_in(1) <= (X"FF", X"FF", X"FF", X"FF"); -- white opaque color_in(1) <= (X"FF", X"FF", X"FF", X"FF"); -- white opaque
color_op <= op_over; color_op <= op_over;
vga_scan_rdy <= stat_hready and stat_vready; vga_scan_rdy <= stat_hready and stat_vready;
inst_linefifo: entity work.linefifo inst_linefifo: entity work.fifo_async
GENERIC MAP GENERIC MAP
( (
depth => fifo_depth, addr_width => NextExpBaseTwo(fifo_depth),
data_width => 32,
almost_full_thresh => fifo_almost_full_thresh, almost_full_thresh => fifo_almost_full_thresh,
almost_empty_thresh => fifo_almost_empty_thresh almost_empty_thresh => fifo_almost_empty_thresh
) )
@@ -202,8 +203,8 @@ inst_linefifo: entity work.linefifo
clk_r => vga_clk, clk_r => vga_clk,
we_w => fifo_color_we, we_w => fifo_color_we,
re_r => fifo_color_re, re_r => fifo_color_re,
color_w => fifo_color_in, data_w => fifo_color_in,
color_r => fifo_color_out, data_r => fifo_color_out,
fifo_full => fifo_full, fifo_full => fifo_full,
fifo_empty => fifo_empty, fifo_empty => fifo_empty,
fifo_afull => fifo_almost_full, fifo_afull => fifo_almost_full,
@@ -211,10 +212,7 @@ inst_linefifo: entity work.linefifo
); );
fifo_color_in(r) <= MDAT_I(7 downto 0); fifo_color_in <= MDAT_I;
fifo_color_in(g) <= MDAT_I(15 downto 8);
fifo_color_in(b) <= MDAT_I(23 downto 16);
fifo_color_in(a) <= MDAT_I(31 downto 24);
fifo_color_re <= stat_scan; fifo_color_re <= stat_scan;
fifo_color_we <= ACK_I and read_bus_en; -- TODO: fifo_color_we <= ACK_I and read_bus_en; -- TODO:
MRDY_O <= not fifo_full; MRDY_O <= not fifo_full;
@@ -342,7 +340,7 @@ pixel_counter:
end if; end if;
end if; end if;
end if; end if;
ADDR_O <= vga_mem_offset + to_unsigned(4*(pixel_cntx + pixel_cnty), 32); ADDR_O <= vga_mem_offset + (to_unsigned(pixel_cntx, 30) & "00") + (to_unsigned(pixel_cnty, 30) & "00");
end if; end if;
end process; end process;
@@ -413,7 +411,7 @@ data_valid_register:
if ADDR_I(8) = '1' then if ADDR_I(8) = '1' then
vga_master_en <= SDAT_I(0); vga_master_en <= SDAT_I(0);
elsif ADDR_I(9) = '1' then elsif ADDR_I(9) = '1' then
vga_mem_offset <= SDAT_I; vga_mem_offset <= SDAT_I(31 downto 2) & "00";
end if; end if;
end if; end if;
end if; end if;