diff --git a/lib/CPUs/MIPS/sim/asm/exception.s b/lib/CPUs/MIPS/sim/asm/exception.s
deleted file mode 100644
index 20c0aaa..0000000
--- a/lib/CPUs/MIPS/sim/asm/exception.s
+++ /dev/null
@@ -1,249 +0,0 @@
-		.file	"exception.s"
-
-		.section .kdata,"a"
-		.align	2
-_k_stack:	.space	256, 0
-_k_msg1:	.asciiz	"Exception at "
-_k_msg2:	.asciiz	"EPC      : "
-_k_msg3:	.asciiz	"Cause    : "
-_k_msg4:	.asciiz	"Status   : "
-_k_msg5:	.asciiz	"BadVAddr : "
-_k_crlf:	.asciiz	"\r\n"
-_k_hextbl:	.ascii "0123456789ABCDEF"
-
-		.section .ktext,"ax"
-		.align	2
-
-		.equ	LED_STAT, 0x80000000
-		.equ	UART_DATA, 0x80000004
-		.equ	UART_STAT, 0x80000008
-	
-		.macro kpush reg
-		addiu	$sp, 4
-		sw		\reg, 0($sp)
-		.endm
-		
-		.macro kpop reg
-		lw		\reg, 0($sp)
-		addiu	$sp, -4
-		.endm
-
-_exc_handler:
-
-		sw		$sp, _k_stack
-		la		$sp, _k_stack
-		kpush	$8
-		kpush	$9
-		kpush	$10
-		kpush	$11
-		kpush	$12
-		kpush	$31
-
-		.set	noreorder
-		# Get BadVAddr
-		mfc0	$10, $8
-		kpush	$10
-		# Get Status
-		mfc0	$10, $12
-		kpush	$10
-		# Get Cause
-		mfc0	$10, $13
-		kpush	$10
-		srl		$10, 29
-		andi	$11, $10, 4
-		# Get EPC
-		mfc0	$10, $14
-		kpush	$10
-
-		# Get real EPC
-		addu	$10, $11
-		kpush	$10
-		
-		# Print CRLF
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-
-		# Print real EPC
-		la		$11, _k_msg1
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print EPC
-		la		$11, _k_msg2
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print Cause
-		la		$11, _k_msg3
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print Status
-		la		$11, _k_msg4
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print BadVAddr
-		la		$11, _k_msg5
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Set Error LED and ExcCode LEDs
-		# Get Cause
-		mfc0	$26, $13
-		li 		$27, LED_STAT
-		srl		$26, 2
-		andi	$26, 0x000F
-		or 		$26, $27
-		sw 		$26, 0($27)
-
-		# wait for exception = 0
-$w4x:	mfc0	$26, $13
-		nop
-		srl		$26, 8
-		andi	$26, 1
-		bnez	$26, $w4x
-		nop
-		
-		# Get return address
-		mfc0	$26, $14
-
-		kpop	$31
-		kpop	$12
-		kpop	$11
-		kpop	$10
-		kpop	$9
-		kpop	$8
-		lw		$sp, _k_stack
-
-		# Return
-		jr	$26
-		rfe
-		.set	reorder
-
-# word = $10
-_kprint_word:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		srl		$10, 16
-		jal		_kprint_halfword
-		nop
-		kpop	$10
-		jal		_kprint_halfword
-		nop
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-# halfword = $10
-_kprint_halfword:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		srl		$10, 8
-		jal		_kprint_byte
-		nop
-		kpop	$10
-		jal		_kprint_byte
-		nop
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-# byte = $10
-_kprint_byte:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		srl		$10, 4
-		jal		_kprint_nibble
-		nop
-		kpop	$10
-		jal		_kprint_nibble
-		nop
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-_kprint_nibble:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		la		$12, _k_hextbl
-		andi	$10, 0xF
-		addu	$12, $10
-		lbu		$10, 0($12)
-		jal		_ksaus
-		nop
-		kpop	$10
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-# char = $10
-_ksaus:
-		.set	noreorder
-		li		$8, UART_STAT
-		lbu		$8, 0($8)
-		li		$9, UART_DATA
-		andi	$8, 0x02
-		bnez	$8, _ksaus
-		nop
-		j		$31
-		sb		$10, 0($9)
-		.set	reorder
-	
-_kputs:
-		.set	noreorder
-		kpush	$11
-		kpush	$31
-$kpl:	lbu		$10, 0($11)
-		addiu	$11, 1
-		blez	$10, $kpex
-		nop
-		jal		_ksaus
-		nop
-		j		$kpl
-		nop
-$kpex:	kpop	$31
-		kpop	$11
-		jr		$31
-		nop		
-		.set	reorder
-	
diff --git a/lib/CPUs/MIPS/sim/asm/faculty.c b/lib/CPUs/MIPS/sim/asm/faculty.c
deleted file mode 100644
index 5419715..0000000
--- a/lib/CPUs/MIPS/sim/asm/faculty.c
+++ /dev/null
@@ -1,96 +0,0 @@
-//#include <stdio.h>
-//#include <stdlib.h>
-//#include <string.h>
-
-int faculty(int f0, int *pDst, int len)
-{
-	int i=0;
-
-	pDst[i++] = f0;
-
-	for (; i < len; i++)
-	{
-		pDst[i] = pDst[i-1] * i;
-	}
-
-	return i;
-}
-
-#define	NUM_ELEMENTS	20
-
-void saus(char c)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while((0x02 & *pUART_stat) != 0);
-
-	*pUART_data = c;
-}
-
-int sputs(char *pStr)
-{
-	char *start;
-	start = pStr;
-
-	while(*pStr)
-		saus(*(pStr++));
-
-	return pStr - start;
-}
-
-void print_word(int word)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 8; i++)
-
-	{
-		nibble = (char)((word >> 28) & 0xF);
-		word <<= 4;
-
-		if (nibble < 10)
-			c = nibble + '0';
-		else
-			c = nibble + 'A' - 10;
-
-		saus(c);
-	}
-
-}
-
-int main (void)
-{
-	int buf[NUM_ELEMENTS], result, i, j, cnt;
-	volatile int *pReg = (int*)0x80000000;
-	volatile char *pUART_data = (char*)0x80000004;
-	volatile char *pUART_ctrl = (char*)0x80000008;
-	volatile char *pUART_baud = (char*)0x80000009;
-	char msg[] = "MIPS R3000 CPU\r\nReady\r\n";
-
-	*pUART_baud = 0x35;
-	*pUART_ctrl = 0x55;
-
-	cnt = 0;
-	memset(buf, 0, sizeof(buf));
-
-	sputs(msg);
-
-	buf[NUM_ELEMENTS-1] = 1;
-	while (1)
-	{
-		result = faculty(buf[NUM_ELEMENTS-1], buf, NUM_ELEMENTS);
-
-		for (i=0; i < NUM_ELEMENTS; i++)
-		{
-			print_word(buf[i]);
-			saus(13);
-			saus(10);
-		}
-		cnt++;
-
-		while(1);
-	}
-}
-
diff --git a/lib/CPUs/MIPS/sim/asm/faculty.s b/lib/CPUs/MIPS/sim/asm/faculty.s
deleted file mode 100644
index 9bbdd09..0000000
--- a/lib/CPUs/MIPS/sim/asm/faculty.s
+++ /dev/null
@@ -1,255 +0,0 @@
-	.file	1 "faculty.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	faculty
-	.ent	faculty
-faculty:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$7,1			# 0x1
-	slt	$2,$7,$6
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L7
-	sw	$4,0($5)
-	.set	macro
-	.set	reorder
-
-	addiu	$5,$5,4
-$L5:
-	lw	$2,-4($5)
-	mult	$2,$7
-	addiu	$7,$7,1
-	slt	$3,$7,$6
-	mflo	$2
-	sw	$2,0($5)
-	.set	noreorder
-	.set	nomacro
-	bne	$3,$0,$L5
-	addiu	$5,$5,4
-	.set	macro
-	.set	reorder
-
-$L7:
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	move	$2,$7
-	.set	macro
-	.set	reorder
-
-	.end	faculty
-	.align	2
-	.globl	saus
-	.ent	saus
-saus:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	sll	$4,$4,24
-	sra	$4,$4,24
-	ori	$5,$2,0x4
-	ori	$3,$2,0x8
-$L10:
-	lbu	$2,0($3)
-	andi	$2,$2,0x2
-	bne	$2,$0,$L10
-	sb	$4,0($5)
-	j	$31
-	.end	saus
-	.align	2
-	.globl	sputs
-	.ent	sputs
-sputs:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	lb	$4,0($4)
-	.set	noreorder
-	.set	nomacro
-	j	$L18
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-$L19:
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-	lb	$4,0($16)
-$L18:
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L19
-	subu	$2,$16,$17
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	sputs
-	.align	2
-	.globl	print_word
-	.ent	print_word
-print_word:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	li	$17,7			# 0x7
-	srl	$3,$16,28
-$L29:
-	sltu	$2,$3,10
-	addiu	$17,$17,-1
-	sll	$16,$16,4
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L25
-	addiu	$4,$3,48
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$3,55
-$L25:
-	jal	saus
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L29
-	srl	$3,$16,28
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_word
-	.section	.rodata.str1.4,"aMS",@progbits,1
-	.align	2
-$LC0:
-	.ascii	"MIPS R3000 CPU\r\n"
-	.ascii	"Ready\r\n\000"
-	.text
-	.align	2
-	.globl	main
-	.ent	main
-main:
-	.frame	$sp,136,$31		# vars= 104, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	lw	$2,$LC0
-	lw	$3,$LC0+4
-	addiu	$sp,$sp,-136
-	sw	$2,96($sp)
-	sw	$3,100($sp)
-	lw	$2,$LC0+8
-	lw	$3,$LC0+12
-	sw	$2,104($sp)
-	sw	$3,108($sp)
-	lw	$2,$LC0+16
-	lw	$3,$LC0+20
-	li	$7,-2147483648			# 0xffffffff80000000
-	ori	$8,$7,0x9
-	sw	$2,112($sp)
-	sw	$3,116($sp)
-	ori	$7,$7,0x8
-	li	$3,85
-	sw	$16,120($sp)
-	li	$2,53
-	addiu	$16,$sp,16
-	sb	$2,0($8)
-	move	$4,$16
-	sb	$3,0($7)
-	move	$5,$0
-	li	$6,80			# 0x50
-	sw	$31,128($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	memset
-	sw	$17,124($sp)
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	addiu	$4,$sp,96
-	.set	macro
-	.set	reorder
-
-	li	$3,1			# 0x1
-	sw	$3,92($sp)
-	li	$4,1			# 0x1
-	move	$5,$16
-	li	$6,20			# 0x14
-	.set	noreorder
-	.set	nomacro
-	jal	faculty
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-	li	$16,19			# 0x13
-$L36:
-	lw	$4,0($17)
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	addiu	$16,$16,-1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,13			# 0xd
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,10			# 0xa
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	bgez	$16,$L36
-	addiu	$17,$17,4
-	.set	macro
-	.set	reorder
-
-$L37:
-	j	$L37
-	.end	main
diff --git a/lib/CPUs/MIPS/sim/asm/fibonacci.c b/lib/CPUs/MIPS/sim/asm/fibonacci.c
deleted file mode 100644
index b707efb..0000000
--- a/lib/CPUs/MIPS/sim/asm/fibonacci.c
+++ /dev/null
@@ -1,179 +0,0 @@
-//#include <stdio.h>
-#include <stdlib.h>
-//#include <string.h>
-
-int fibonacci(int f0, int f1, int *pDst, int len)
-{
-	int i;
-
-	i = 0;
-
-	pDst[i++] = f0;
-	pDst[i++] = f1;
-
-	for (; i < len; i++)
-	{
-		pDst[i] = pDst[i-2] + pDst[i-1];
-	}
-
-	return i;
-}
-
-#define	NUM_ELEMENTS	100
-#define	NUM_RUNS		1000
-
-typedef struct _sstat_t
-{
-	char v1;
-	int v2;
-	char v3;
-	short v4;
-
-} __attribute__ ((__packed__)) stat_t;
-
-void test_func(stat_t *pObj)
-{
-	int *pReg = (int*)0x80000000;
-
-
-	*pReg = (int)pObj->v4;
-
-}
-
-char sein(void)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while(!(0x10 & *pUART_stat));
-
-	return *pUART_data;
-}
-
-void saus(char c)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while((0x02 & *pUART_stat) != 0);
-
-	*pUART_data = c;
-}
-
-int sputs(char *pStr)
-{
-	char *start;
-	start = pStr;
-
-	while(*pStr)
-		saus(*(pStr++));
-
-	return pStr - start;
-}
-
-void print_word(int word)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 8; i++)
-
-	{
-		nibble = (char)((word >> 28) & 0xF);
-		word <<= 4;
-
-		if (nibble < 10)
-			c = nibble + '0';
-		else
-			c = nibble + 'A' - 10;
-
-		saus(c);
-	}
-
-}
-
-int main (void)
-{
-	int buf[NUM_ELEMENTS], result, i, j, diff, num_right_elements, num_right_runs;
-	int fill, cnt, *pReg = (int*)0x80000000;
-	volatile char *pUART_data = (char*)0x80000004;
-	volatile char *pUART_ctrl = (char*)0x80000008;
-	volatile char *pUART_baud = (char*)0x80000009;
-	int testbuf[2] = {0x12345678, 0x5555aaaa};
-	stat_t stat = {0x0D, 0xFF5A3FC1, 0x1E, 0x0F07};
-	char msg[] = "MIPS R3000 CPU\r\nReady\r\n";
-	char msg2[32];
-	char baud;
-	char *pPtr;
-	long long product;
-	int op1, op2;
-
-	div_t div_res;
-
-	*pUART_baud = 0x35;
-	*pUART_ctrl = 0x55;
-
-	cnt = 0;
-	fill = 0xAAAAAAAA;
-	memset(msg2, 0, sizeof(msg2));
-	memcpy(msg2, msg, strlen(msg));
-
-	srand(0x19701031);
-	for (i=0; i < sizeof(msg2)-1; i++)
-		msg2[i] = sein();
-
-	sputs(msg2);
-	test_func(&stat);
-
-//	div_res = div(testbuf[1], testbuf[0]);
-	while (1)
-	{
-		num_right_runs = 0;
-		for (i=0; i < NUM_RUNS; i++)
-		{
-			for (j=0;  j < NUM_ELEMENTS; j++)
-				buf[j] = fill;
-
-			fill = ((fill ^ i) - 1) << 1;
-			num_right_elements = 2;
-			result = fibonacci(i, i+1, buf, NUM_ELEMENTS);
-			for (j=2;  j < NUM_ELEMENTS; j++)
-			{
-				diff = buf[j] - buf[j-1];
-				if (diff == buf[j-2])
-					num_right_elements++;
-			}
-			if (num_right_elements == NUM_ELEMENTS)
-				num_right_runs++;
-		}
-
-		if (num_right_runs == NUM_RUNS)
-		{
-			*pReg = cnt & 0x3FFFFFFF;
-			cnt++;
-		}
-		else
-		{
-			*pReg = 0x40000000 | cnt;
-			saus('X');
-		}
-		op1 = (int)-cnt;
-		op2 = (int)((op1 & 8) << 28) ^ rand();
-		product = (long long)op1 * (long long)op2;
-		print_word((int)op1);
-		saus(' ');
-		saus('x');
-		saus(' ');
-		print_word((int)op2);
-		saus(' ');
-		saus('=');
-		saus(' ');
-		print_word((int)(product >> 32));
-		print_word((int)product);
-		saus(13);
-		saus(10);
-
-	}
-	return 0;
-}
-
diff --git a/lib/CPUs/MIPS/sim/asm/fibonacci.s b/lib/CPUs/MIPS/sim/asm/fibonacci.s
deleted file mode 100644
index e042654..0000000
--- a/lib/CPUs/MIPS/sim/asm/fibonacci.s
+++ /dev/null
@@ -1,555 +0,0 @@
-	.file	1 "fibonacci.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	fibonacci
-	.ent	fibonacci
-fibonacci:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$8,2			# 0x2
-	slt	$2,$8,$7
-	sw	$4,0($6)
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L7
-	sw	$5,4($6)
-	.set	macro
-	.set	reorder
-
-	addiu	$6,$6,8
-$L5:
-	lw	$2,-8($6)
-	lw	$3,-4($6)
-	addiu	$8,$8,1
-	addu	$2,$2,$3
-	slt	$4,$8,$7
-	sw	$2,0($6)
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L5
-	addiu	$6,$6,4
-	.set	macro
-	.set	reorder
-
-$L7:
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	move	$2,$8
-	.set	macro
-	.set	reorder
-
-	.end	fibonacci
-	.align	2
-	.globl	test_func
-	.ent	test_func
-test_func:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	lbu	$2,7($4)
-	lbu	$3,6($4)
-	sll	$2,$2,8
-	or	$2,$2,$3
-	sll	$2,$2,16
-	sra	$2,$2,16
-	li	$3,-2147483648			# 0xffffffff80000000
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	sw	$2,0($3)
-	.set	macro
-	.set	reorder
-
-	.end	test_func
-	.align	2
-	.globl	sein
-	.ent	sein
-sein:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	ori	$4,$2,0x4
-	ori	$3,$2,0x8
-$L11:
-	lbu	$2,0($3)
-	andi	$2,$2,0x10
-	beq	$2,$0,$L11
-	lbu	$2,0($4)
-	sll	$2,$2,24
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	sra	$2,$2,24
-	.set	macro
-	.set	reorder
-
-	.end	sein
-	.align	2
-	.globl	saus
-	.ent	saus
-saus:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	sll	$4,$4,24
-	sra	$4,$4,24
-	ori	$5,$2,0x4
-	ori	$3,$2,0x8
-$L14:
-	lbu	$2,0($3)
-	andi	$2,$2,0x2
-	bne	$2,$0,$L14
-	sb	$4,0($5)
-	j	$31
-	.end	saus
-	.align	2
-	.globl	sputs
-	.ent	sputs
-sputs:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	lb	$4,0($4)
-	.set	noreorder
-	.set	nomacro
-	j	$L22
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-$L23:
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-	lb	$4,0($16)
-$L22:
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L23
-	subu	$2,$16,$17
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	sputs
-	.align	2
-	.globl	print_word
-	.ent	print_word
-print_word:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	li	$17,7			# 0x7
-	srl	$3,$16,28
-$L33:
-	sltu	$2,$3,10
-	addiu	$17,$17,-1
-	sll	$16,$16,4
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L29
-	addiu	$4,$3,48
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$3,55
-$L29:
-	jal	saus
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L33
-	srl	$3,$16,28
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_word
-	.section	.sdata,"aw",@progbits
-	.align	2
-$LC0:
-	.word	305419896
-	.word	1431677610
-	.section	.rodata.str1.4,"aMS",@progbits,1
-	.align	2
-$LC2:
-	.ascii	"MIPS R3000 CPU\r\n"
-	.ascii	"Ready\r\n\000"
-	.section	.sdata
-	.align	2
-$LC1:
-	.byte	13
-	.4byte	-10862655
-	.byte	30
-	.half	3847
-	.text
-	.align	2
-	.globl	main
-	.ent	main
-main:
-	.frame	$sp,536,$31		# vars= 480, regs= 10/0, args= 16, gp= 0
-	.mask	0xc0ff0000,-4
-	.fmask	0x00000000,0
-	lw	$2,$LC0
-	addiu	$sp,$sp,-536
-	lw	$3,$LC0+4
-	sw	$2,416($sp)
-	lw	$2,$LC2
-	lwl	$4,$LC1+3
-	lwl	$5,$LC1+7
-	sw	$3,420($sp)
-	sw	$2,432($sp)
-	lw	$3,$LC2+4
-	lw	$2,$LC2+8
-	lwr	$5,$LC1+4
-	lwr	$4,$LC1
-	sw	$3,436($sp)
-	sw	$2,440($sp)
-	lw	$3,$LC2+12
-	lw	$2,$LC2+16
-	sw	$31,532($sp)
-	sw	$5,428($sp)
-	sw	$23,524($sp)
-	sw	$22,520($sp)
-	sw	$21,516($sp)
-	sw	$20,512($sp)
-	sw	$18,504($sp)
-	sw	$17,500($sp)
-	sw	$16,496($sp)
-	sw	$4,424($sp)
-	sw	$3,444($sp)
-	sw	$fp,528($sp)
-	sw	$19,508($sp)
-	sw	$2,448($sp)
-	lw	$3,$LC2+20
-	li	$23,-2147483648			# 0xffffffff80000000
-	ori	$7,$23,0x9
-	sw	$3,452($sp)
-	ori	$6,$23,0x8
-	li	$3,85
-	addiu	$16,$sp,432
-	li	$2,53
-	sb	$2,0($7)
-	move	$4,$16
-	sb	$3,0($6)
-	li	$2,-1431699456			# 0xffffffffaaaa0000
-	sw	$0,456($sp)
-	sw	$0,460($sp)
-	sw	$0,464($sp)
-	sw	$0,468($sp)
-	sw	$0,472($sp)
-	sw	$0,476($sp)
-	sw	$0,480($sp)
-	sw	$0,484($sp)
-	ori	$20,$2,0xaaaa
-	.set	noreorder
-	.set	nomacro
-	jal	strlen
-	addiu	$18,$sp,456
-	.set	macro
-	.set	reorder
-
-	move	$6,$2
-	move	$5,$16
-	.set	noreorder
-	.set	nomacro
-	jal	memcpy
-	move	$4,$18
-	.set	macro
-	.set	reorder
-
-	li	$4,426770432			# 0x19700000
-	.set	noreorder
-	.set	nomacro
-	jal	srand
-	ori	$4,$4,0x1031
-	.set	macro
-	.set	reorder
-
-	move	$22,$0
-	move	$17,$0
-	addiu	$21,$sp,16
-$L38:
-	addu	$16,$21,$17
-	.set	noreorder
-	.set	nomacro
-	jal	sein
-	addiu	$17,$17,1
-	.set	macro
-	.set	reorder
-
-	sltu	$3,$17,31
-	.set	noreorder
-	.set	nomacro
-	bne	$3,$0,$L38
-	sb	$2,440($16)
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$4,$18
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	test_func
-	addiu	$4,$sp,424
-	.set	macro
-	.set	reorder
-
-	li	$fp,100			# 0x64
-	move	$18,$0
-	move	$17,$0
-$L54:
-	move	$2,$21
-	li	$6,99			# 0x63
-$L47:
-	addiu	$6,$6,-1
-	sw	$20,0($2)
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L47
-	addiu	$2,$2,4
-	.set	macro
-	.set	reorder
-
-	xor	$2,$20,$17
-	addiu	$16,$17,1
-	addiu	$2,$2,-1
-	move	$5,$16
-	addiu	$6,$sp,16
-	li	$7,100			# 0x64
-	move	$4,$17
-	.set	noreorder
-	.set	nomacro
-	jal	fibonacci
-	sll	$20,$2,1
-	.set	macro
-	.set	reorder
-
-	li	$7,2			# 0x2
-	addiu	$5,$21,8
-	.set	noreorder
-	.set	nomacro
-	j	$L52
-	li	$6,97			# 0x61
-	.set	macro
-	.set	reorder
-
-$L50:
-	bltz	$6,$L65
-$L52:
-	lw	$2,0($5)
-	lw	$3,-4($5)
-	lw	$4,-8($5)
-	subu	$2,$2,$3
-	addiu	$6,$6,-1
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$2,$L50
-	addiu	$5,$5,4
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L52
-	addiu	$7,$7,1
-	.set	macro
-	.set	reorder
-
-$L65:
-	beq	$7,$fp,$L66
-$L43:
-	slt	$2,$16,1000
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L54
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-	li	$2,1000			# 0x3e8
-	.set	noreorder
-	.set	nomacro
-	bne	$18,$2,$L55
-	li	$3,1073676288			# 0x3fff0000
-	.set	macro
-	.set	reorder
-
-	ori	$3,$3,0xffff
-	and	$2,$22,$3
-	sw	$2,0($23)
-	addiu	$22,$22,1
-	subu	$16,$0,$22
-$L67:
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	andi	$17,$16,0x8
-	.set	macro
-	.set	reorder
-
-	sll	$17,$17,28
-	xor	$17,$17,$2
-	mult	$16,$17
-	mflo	$18
-	mfhi	$19
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$16
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,32			# 0x20
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,120			# 0x78
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,32			# 0x20
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,32			# 0x20
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,61			# 0x3d
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,32			# 0x20
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	sra	$4,$19,0
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$18
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,13			# 0xd
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,10			# 0xa
-	.set	macro
-	.set	reorder
-
-	move	$18,$0
-	.set	noreorder
-	.set	nomacro
-	j	$L54
-	move	$17,$0
-	.set	macro
-	.set	reorder
-
-$L66:
-	.set	noreorder
-	.set	nomacro
-	j	$L43
-	addiu	$18,$18,1
-	.set	macro
-	.set	reorder
-
-$L55:
-	li	$2,1073741824			# 0x40000000
-	or	$2,$22,$2
-	li	$4,88			# 0x58
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	sw	$2,0($23)
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	j	$L67
-	subu	$16,$0,$22
-	.set	macro
-	.set	reorder
-
-	.end	main
diff --git a/lib/CPUs/MIPS/sim/asm/idata.ld b/lib/CPUs/MIPS/sim/asm/idata.ld
deleted file mode 100644
index 5913b2c..0000000
--- a/lib/CPUs/MIPS/sim/asm/idata.ld
+++ /dev/null
@@ -1,24 +0,0 @@
-MEMORY
-{
-  imem       : ORIGIN = 0x00000000, LENGTH = 0x00002000  /*   8K    */
-}
-
-
-SECTIONS
-{
-   .stext 0x00000000 :
-   {
-     *(.stext)
-   }  > imem
-   
-   .ktext 0x00000180 :
-   {
-     *(.ktext)
-   }  > imem
-
-   .text 0x00000200 :
-   {
-     *(.text)
-   }  > imem
-
-}
diff --git a/lib/CPUs/MIPS/sim/asm/init.s b/lib/CPUs/MIPS/sim/asm/init.s
deleted file mode 100644
index 41a35da..0000000
--- a/lib/CPUs/MIPS/sim/asm/init.s
+++ /dev/null
@@ -1,28 +0,0 @@
-		.file	"init.s"
-	
-		.text
-		.align	2
-		.globl _init
-		.extern end
-	
-_init:
-		.set	noreorder
-
-		# set uart
-		la	$26, sys_uart_baud
-		addiu	$27, $0, baudrate
-		sb	$27, 0($26)
-		
-		# set stack pointer 
-		la $sp, end
-
-		# jump main
-		la $26, main
-		jalr $26
-
-_terminate:
-		nop
-		j		_terminate
-		nop
-		
-		.set	reorder
diff --git a/lib/CPUs/MIPS/sim/asm/jtag.sh b/lib/CPUs/MIPS/sim/asm/jtag.sh
deleted file mode 100644
index f03567f..0000000
--- a/lib/CPUs/MIPS/sim/asm/jtag.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/sh
-
-TARGET=$(basename $1 .c)
-
-xtclsh.exe $TARGET.RAM.tcl
-xtclsh.exe $TARGET.ROM.tcl
-
diff --git a/lib/CPUs/MIPS/sim/asm/kernel.s b/lib/CPUs/MIPS/sim/asm/kernel.s
deleted file mode 100644
index 7ec783f..0000000
--- a/lib/CPUs/MIPS/sim/asm/kernel.s
+++ /dev/null
@@ -1,251 +0,0 @@
-		.file	"exception.s"
-
-		.section .kdata,"a"
-		.align	2
-_k_stack:	.space	256, 0
-_k_msg1:	.asciiz	"Exception at "
-_k_msg2:	.asciiz	"EPC      : "
-_k_msg3:	.asciiz	"Cause    : "
-_k_msg4:	.asciiz	"Status   : "
-_k_msg5:	.asciiz	"BadVAddr : "
-_k_crlf:	.asciiz	"\r\n"
-_k_hextbl:	.ascii "0123456789ABCDEF"
-
-		.section .ktext,"ax"
-		.align	2
-		.globl _kputs
-
-		.macro kpush reg
-		addiu	$sp, 4
-		sw		\reg, 0($sp)
-		.endm
-		
-		.macro kpop reg
-		lw		\reg, 0($sp)
-		addiu	$sp, -4
-		.endm
-
-_exc_handler:
-
-		sw		$sp, _k_stack
-		la		$sp, _k_stack
-		kpush	$8
-		kpush	$9
-		kpush	$10
-		kpush	$11
-		kpush	$12
-		kpush	$31
-
-		.set	noreorder
-		# Get BadVAddr
-		mfc0	$10, $8
-		kpush	$10
-		# Get Status
-		mfc0	$10, $12
-		kpush	$10
-		# Get Cause
-		mfc0	$10, $13
-		kpush	$10
-		srl		$10, 29
-		andi	$11, $10, 4
-		# Get EPC
-		mfc0	$10, $14
-		kpush	$10
-
-		# Get real EPC
-		addu	$10, $11
-		kpush	$10
-		
-		# set uart
-		la	$26, sys_uart_baud
-		addiu	$27, $0, baudrate
-		sb	$27, 0($26)
-
-		# Print CRLF
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-
-		# Print real EPC
-		la		$11, _k_msg1
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print EPC
-		la		$11, _k_msg2
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print Cause
-		la		$11, _k_msg3
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print Status
-		la		$11, _k_msg4
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print BadVAddr
-		la		$11, _k_msg5
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Set Error LED and ExcCode LEDs
-		# Get Cause
-		mfc0	$26, $13
-		la 		$27, sys_led_port
-		srl		$26, 2
-		andi	$26, 0x000F
-		or 		$26, $27
-		sw 		$26, 0($27)
-
-		# wait for all interrupts = 0
-$w4x:	mfc0	$26, $13
-		nop
-		srl		$26, 8
-		andi	$26, 0xFF
-		bnez	$26, $w4x
-		nop
-		
-		# Get return address
-		mfc0	$26, $14
-
-		kpop	$31
-		kpop	$12
-		kpop	$11
-		kpop	$10
-		kpop	$9
-		kpop	$8
-		lw		$sp, _k_stack
-
-		# Return
-		jr	$26
-		rfe
-		.set	reorder
-
-# word = $10
-_kprint_word:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		srl		$10, 16
-		jal		_kprint_halfword
-		nop
-		kpop	$10
-		jal		_kprint_halfword
-		nop
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-# halfword = $10
-_kprint_halfword:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		srl		$10, 8
-		jal		_kprint_byte
-		nop
-		kpop	$10
-		jal		_kprint_byte
-		nop
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-# byte = $10
-_kprint_byte:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		srl		$10, 4
-		jal		_kprint_nibble
-		nop
-		kpop	$10
-		jal		_kprint_nibble
-		nop
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-_kprint_nibble:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		la		$12, _k_hextbl
-		andi	$10, 0xF
-		addu	$12, $10
-		lbu		$10, 0($12)
-		jal		_ksaus
-		nop
-		kpop	$10
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-# char = $10
-_ksaus:
-		.set	noreorder
-		la		$8, sys_uart_stat
-		lbu		$8, 0($8)
-		la		$9, sys_uart_data
-		andi	$8, 0x02
-		bnez	$8, _ksaus
-		nop
-		j		$31
-		sb		$10, 0($9)
-		.set	reorder
-	
-_kputs:
-		.set	noreorder
-		kpush	$11
-		kpush	$31
-$kpl:	lbu		$10, 0($11)
-		addiu	$11, 1
-		blez	$10, $kpex
-		nop
-		jal		_ksaus
-		nop
-		j		$kpl
-		nop
-$kpex:	kpop	$31
-		kpop	$11
-		jr		$31
-		nop		
-		.set	reorder
-	
diff --git a/lib/CPUs/MIPS/sim/asm/link.ld b/lib/CPUs/MIPS/sim/asm/link.ld
deleted file mode 100644
index e175fa8..0000000
--- a/lib/CPUs/MIPS/sim/asm/link.ld
+++ /dev/null
@@ -1,47 +0,0 @@
-MEMORY
-{
-  imem       : ORIGIN = 0x00400000, LENGTH = 0x00004000  /*   8K    */
-  dmem       : ORIGIN = 0x00000000, LENGTH = 0x00002000  /*   8K    */
-}
-
-end = 0x7FFFEFFC;
-baudrate = 0x0D;
-sys_led_port = 0x80000000;
-sys_uart_baud = 0x80000009;
-sys_uart_stat = 0x80000008;
-sys_uart_data = 0x80000004;
-sys_timer_sec = 0x80000014;
-sys_timer_usec = 0x80000010;
-
-SECTIONS
-{
-   .stext 0x00400000 :
-   {
-     *(.stext)
-   }  > imem
-   
-   .ktext 0x00400180 :
-   {
-     *(.ktext)
-   }  > imem
-
-   .text . :
-   {
-     *(.text)
-   }  > imem
-
-   .data 0x00000000 : ALIGN(2)
-   {
-      *(.rodata*) *(.data) *(.sdata) *(.sbss) *(.kdata)
-   }  > dmem
-
-   .bss . :
-   {
-      *(.bss)
-   }  > dmem
-
-   .eh_frame . :
-   {
-      *(.eh_frame)
-   }  > dmem
-}
diff --git a/lib/CPUs/MIPS/sim/asm/load_store.c b/lib/CPUs/MIPS/sim/asm/load_store.c
deleted file mode 100644
index b39630e..0000000
--- a/lib/CPUs/MIPS/sim/asm/load_store.c
+++ /dev/null
@@ -1,64 +0,0 @@
-//#include <stdio.h>
-//#include <stdlib.h>
-//#include <string.h>
-
-int main (void)
-{
-
-
-__asm
-(
-	".set	noreorder\n"
-	"li		$8, 0x81234678\n"
-	"li		$15, 0x10000000\n"
-	"li		$16, 0xAAAAAAAA\n"
-	"li		$17, 0xBBBBBBBB\n"
-	"li		$18, 0xCCCCCCCC\n"
-	"li		$19, 0xDDDDDDDD\n"
-	"li		$24, 0x11111111\n"
-	"li		$25, 0x22222222\n"
-	"li		$26, 0x33333333\n"
-	"li		$27, 0x44444444\n"
-	"sw		$8, 0($15)\n"
-	"nop\n"
-	"lwl	$16, 0($15)\n"
-	"lwl	$17, 1($15)\n"
-	"lwl	$18, 2($15)\n"
-	"lwl	$19, 3($15)\n"
-	"nop\n"
-	"lwr	$24, 0($15)\n"
-	"lwr	$25, 1($15)\n"
-	"lwr	$26, 2($15)\n"
-	"lwr	$27, 3($15)\n"
-	"nop\n"
-	"lbu	$16, 0($15)\n"
-	"lbu	$17, 1($15)\n"
-	"lbu	$18, 2($15)\n"
-	"lbu	$19, 3($15)\n"
-	"nop\n"
-	"lb		$16, 0($15)\n"
-	"lb		$17, 1($15)\n"
-	"lb		$18, 2($15)\n"
-	"lb		$19, 3($15)\n"
-	"nop\n"
-	"swl	$8, 4($15)\n"
-	"swl	$8, 9($15)\n"
-	"swl	$8, 14($15)\n"
-	"swl	$8, 19($15)\n"
-	"nop\n"
-	"swr	$8, 20($15)\n"
-	"swr	$8, 25($15)\n"
-	"swr	$8, 30($15)\n"
-	"swr	$8, 35($15)\n"
-	"nop\n"
-	"sb		$8, 4($15)\n"
-	"sb		$8, 5($15)\n"
-	"sb		$8, 6($15)\n"
-	"sb		$8, 7($15)\n"
-	"nop\n"
-	".set	reorder\n"
-
-);
-
-}
-
diff --git a/lib/CPUs/MIPS/sim/asm/load_store.s b/lib/CPUs/MIPS/sim/asm/load_store.s
deleted file mode 100644
index 9aa8fca..0000000
--- a/lib/CPUs/MIPS/sim/asm/load_store.s
+++ /dev/null
@@ -1,64 +0,0 @@
-	.file	1 "load_store.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	main
-	.ent	main
-main:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
- #APP
-	.set	noreorder
-li		$8, 0x81234678
-li		$15, 0x10000000
-li		$16, 0xAAAAAAAA
-li		$17, 0xBBBBBBBB
-li		$18, 0xCCCCCCCC
-li		$19, 0xDDDDDDDD
-li		$24, 0x11111111
-li		$25, 0x22222222
-li		$26, 0x33333333
-li		$27, 0x44444444
-sw		$8, 0($15)
-nop
-lwl	$16, 0($15)
-lwl	$17, 1($15)
-lwl	$18, 2($15)
-lwl	$19, 3($15)
-nop
-lwr	$24, 0($15)
-lwr	$25, 1($15)
-lwr	$26, 2($15)
-lwr	$27, 3($15)
-nop
-lbu	$16, 0($15)
-lbu	$17, 1($15)
-lbu	$18, 2($15)
-lbu	$19, 3($15)
-nop
-lb		$16, 0($15)
-lb		$17, 1($15)
-lb		$18, 2($15)
-lb		$19, 3($15)
-nop
-swl	$8, 4($15)
-swl	$8, 9($15)
-swl	$8, 14($15)
-swl	$8, 19($15)
-nop
-swr	$8, 20($15)
-swr	$8, 25($15)
-swr	$8, 30($15)
-swr	$8, 35($15)
-nop
-sb		$8, 4($15)
-sb		$8, 5($15)
-sb		$8, 6($15)
-sb		$8, 7($15)
-nop
-.set	reorder
-
- #NO_APP
-	j	$31
-	.end	main
diff --git a/lib/CPUs/MIPS/sim/asm/make.sh b/lib/CPUs/MIPS/sim/asm/make.sh
deleted file mode 100644
index 2f39996..0000000
--- a/lib/CPUs/MIPS/sim/asm/make.sh
+++ /dev/null
@@ -1,30 +0,0 @@
-#!/bin/sh
-
-TARGET=$(basename $1 .c)
-TARGET_CPU=r3000
-ROM_WORDADDR_WIDTH=12
-RAM_WORDADDR_WIDTH=11
-
-echo Building $TARGET...
-
-mipsel-elf-as.exe -march=$TARGET_CPU startup.s -o startup.o
-mipsel-elf-as.exe -march=$TARGET_CPU init.s -o init.o
-mipsel-elf-as.exe -march=$TARGET_CPU kernel.s -o kernel.o
-
-#mipsel-elf-gcc -O2 -march=$TARGET_CPU $TARGET.c -o $TARGET.s -L $LIBDIR
-
-mipsel-elf-gcc -msoft-float -O2 -c utils.c -o utils.o
-mipsel-elf-gcc -msoft-float -O2 -c $TARGET.c -o $TARGET.o
-mipsel-elf-ld.exe -G 0 -M -T link.ld startup.o init.o kernel.o utils.o $TARGET.o -o $TARGET.elf -L /usr/local/mipsel-elf/lib -L /usr/local/lib/gcc/mipsel-elf/3.4.6 -lc -lgcc >$TARGET.map
-mipsel-elf-objdump.exe -d $TARGET.elf > $TARGET.dis
-
-mipsel-elf-objcopy.exe -j .stext -j .ktext -j .text $TARGET.elf -O binary $TARGET.ROM.bin
-mipsel-elf-objcopy.exe -j .data $TARGET.elf -O binary $TARGET.RAM.bin
-
-./romgen.exe $TARGET.ROM.bin $ROM_WORDADDR_WIDTH
-./ramgen.exe $TARGET.RAM.bin $RAM_WORDADDR_WIDTH
-
-#xtclsh.exe $TARGET.RAM.tcl
-#xtclsh.exe $TARGET.ROM.tcl
-
-echo done.
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/mips_exception.s b/lib/CPUs/MIPS/sim/asm/mips_exception.s
deleted file mode 100644
index c8c88a1..0000000
--- a/lib/CPUs/MIPS/sim/asm/mips_exception.s
+++ /dev/null
@@ -1,31 +0,0 @@
-main:
-		j	lab
-#		nop
-#		break 52
-lab:			
-		li, $8, 0x81234678
-
-# SB
-		li, $15, 0x10000000
-		li  $16, 0x00400014
-		mtc0, $16, $14
-		nop
-		nop
-		rfe
-
-# Address error exception
-		sw	$8, 1($15)
-		sw	$8, 2($15)
-		sw	$8, 3($15)
-		
-# Address error exception
-		sh  $8, 1($15)
-
-# Address error exception
-		sh  $8, 3($15)
-
-
-		nop
-		nop
-		nop
-		
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/mips_load_store_.txt b/lib/CPUs/MIPS/sim/asm/mips_load_store_.txt
deleted file mode 100644
index 30b75bc..0000000
--- a/lib/CPUs/MIPS/sim/asm/mips_load_store_.txt
+++ /dev/null
@@ -1,86 +0,0 @@
-SB (tested by SPIM)
-VA(1..0)       DMEM_WE        ROL
-0              0001            0
-1              0010            1
-2              0100            2
-3              1000            3
-
-SH (tested by SPIM)
-VA(1..0)       DMEM_WE        ROL
-0              0011            0
-2              1100            2
-
-SWL (tested by SPIM)
-VA(1..0)       DMEM_WE        ROL
-0              0001            1 
-1              0011            2
-2              0111            3
-3              1111            0
-
-SWR (tested by SPIM)
-VA(1..0)       DMEM_WE        ROL
-0              1111            0
-1              1110            1
-2              1100            2
-3              1000            3
-
-LB (tested by SPIM)
-VA(1..0)       REG_WE         ROR
-0              1111            0   
-1              1111            1   
-2              1111            2   
-3              1111            3   
-
-LH (tested by SPIM)
-VA(1..0)       REG_WE         ROR
-0              1111            0      
-2              1111            2   
-
-LWL (tested by SPIM)
-VA(1..0)       REG_WE         ROR
-0              1000            1
-1              1100            2
-2              1110            3
-3              1111            0
-
-LWR (tested by SPIM)
-VA(1..0)       REG_WE         ROR
-0              1111            0   
-1              0111            1   
-2              0011            2   
-3              0001            3   
-
-
-
-*SHIFTER*        SB      SH      SWL      SWR     SW
-shift_byp        0       0        0        0      1               
-shift_off        0       0        1        0      x
-
-SHL = VA + shift_off
-
-*Byte Enable*    SB      SH      SWL      SWR     SW
-be_byp           0       0        0        0      1               
-quarter_word_en  1       0        0        0      x
-half_word_en     0       1        0        0      x
-align_left       x       x        0        1      x  
-
-
-*SHIFTER*        LB      LH      LWL      LWR     LW
-shift_byp        0       0        0        0      1               
-shift_off        0       0        1        0      x 
-
-SHL = VA + shift_off
-
-*Byte Enable*    LB      LH      LWL      LWR     LW
-be_byp           1       1        0        0      1
-align_left       x       x        1        0      x
-
-
-* Sign ext*    
-se_byp =  shift_byp and (shift_byp and not be_byp)
-
-
-00 11
-01 10
-10 01
-11 00
diff --git a/lib/CPUs/MIPS/sim/asm/muldiv.c b/lib/CPUs/MIPS/sim/asm/muldiv.c
deleted file mode 100644
index 1f15755..0000000
--- a/lib/CPUs/MIPS/sim/asm/muldiv.c
+++ /dev/null
@@ -1,134 +0,0 @@
-//#include <stdio.h>
-#include <stdlib.h>
-//#include <string.h>
-
-#define	NUM_ELEMENTS	100
-#define	NUM_RUNS		1000
-
-char sein(void)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while(!(0x10 & *pUART_stat));
-
-	return *pUART_data;
-}
-
-void saus(char c)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while((0x02 & *pUART_stat) != 0);
-
-	*pUART_data = c;
-}
-
-int sputs(char *pStr)
-{
-	char *start;
-	start = pStr;
-
-	while(*pStr)
-		saus(*(pStr++));
-
-	return pStr - start;
-}
-
-void print_byte(char byte)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 2; i++)
-	{
-		nibble = (char)((byte >> 4) & 0xF);
-		byte <<= 4;
-
-		if (nibble < 10)
-			c = nibble + '0';
-		else
-			c = nibble + 'A' - 10;
-
-		saus(c);
-	}
-}
-
-void print_word(int word)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 4; i++)
-	{
-		c = (char) (word >> 24);
-		print_byte(c);
-		word <<= 8;
-	}
-}
-
-int main (void)
-{
-	int cnt, i, j;
-	int mix, *pReg = (int*)0x80000000;
-	volatile char *pUART_data = (char*)0x80000004;
-	volatile char *pUART_ctrl = (char*)0x80000008;
-	volatile char *pUART_baud = (char*)0x80000009;
-	char msg[] = "MIPS R3000 CPU\r\nMul/Div Test\r\n";
-	int s1, s2, sp, st;
-
-	div_t div_res;
-
-	*pUART_baud = 0x35;
-	*pUART_ctrl = 0x55;
-
-	srand(0x19701031);
-
-	sputs(msg);
-
-	cnt = 0;
-	while(1)
-	{
-		for (i=0; i < 1000; i++)
-		{
-			for (j=1; j < 1000; j++)
-			{
-				mix = (int)rand();
-				mix = (mix << 8) ^ (mix << 16);
-				s1 = (int)rand() ^ mix;
-				mix = (int)rand();
-				mix = (mix << 8) ^ (mix << 16);
-				s2 = (int)rand() ^ mix;
-	//			s1 = i;
-	//			s2 = j;
-
-				div_res = div(s1, s2);
-
-	//			print_word(s1);
-	//			sputs(" / ");
-	//			print_word(s2);
-	//			sputs(" = ");
-	//			print_word(div_res.quot);
-	//			sputs(" R: ");
-	//			print_word(div_res.rem);
-	//			sputs(" -- ");
-
-				sp = s2*div_res.quot;
-				st = div_res.rem + sp;
-				if (st != s1)
-				{
-					sputs("Failed: ");
-					sputs("d*quot = ");
-					print_word(sp);
-					sputs("\r\n");
-					return -1;
-				}
-			}
-		}
-		sputs("Iteration ");
-		print_word(cnt++);
-		sputs(": Passed\r\n");
-	}
-}
-
diff --git a/lib/CPUs/MIPS/sim/asm/muldiv.s b/lib/CPUs/MIPS/sim/asm/muldiv.s
deleted file mode 100644
index c6de7d9..0000000
--- a/lib/CPUs/MIPS/sim/asm/muldiv.s
+++ /dev/null
@@ -1,391 +0,0 @@
-	.file	1 "muldiv.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	sein
-	.ent	sein
-sein:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	ori	$4,$2,0x4
-	ori	$3,$2,0x8
-$L2:
-	lbu	$2,0($3)
-	andi	$2,$2,0x10
-	beq	$2,$0,$L2
-	lbu	$2,0($4)
-	sll	$2,$2,24
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	sra	$2,$2,24
-	.set	macro
-	.set	reorder
-
-	.end	sein
-	.align	2
-	.globl	saus
-	.ent	saus
-saus:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	sll	$4,$4,24
-	sra	$4,$4,24
-	ori	$5,$2,0x4
-	ori	$3,$2,0x8
-$L6:
-	lbu	$2,0($3)
-	andi	$2,$2,0x2
-	bne	$2,$0,$L6
-	sb	$4,0($5)
-	j	$31
-	.end	saus
-	.align	2
-	.globl	sputs
-	.ent	sputs
-sputs:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	lb	$4,0($4)
-	.set	noreorder
-	.set	nomacro
-	j	$L14
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-$L15:
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-	lb	$4,0($16)
-$L14:
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L15
-	subu	$2,$16,$17
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	sputs
-	.align	2
-	.globl	print_byte
-	.ent	print_byte
-print_byte:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$16,16($sp)
-	sll	$16,$4,24
-	sw	$17,20($sp)
-	sw	$31,24($sp)
-	sra	$16,$16,24
-	li	$17,1			# 0x1
-	sra	$2,$16,4
-$L25:
-	andi	$5,$2,0xf
-	sll	$2,$16,4
-	sll	$16,$2,24
-	sltu	$3,$5,10
-	addiu	$17,$17,-1
-	sra	$16,$16,24
-	.set	noreorder
-	.set	nomacro
-	bne	$3,$0,$L21
-	addiu	$4,$5,48
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$5,55
-$L21:
-	jal	saus
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L25
-	sra	$2,$16,4
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_byte
-	.align	2
-	.globl	print_word
-	.ent	print_word
-print_word:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	li	$17,3			# 0x3
-$L30:
-	sra	$4,$16,24
-	.set	noreorder
-	.set	nomacro
-	jal	print_byte
-	addiu	$17,$17,-1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L30
-	sll	$16,$16,8
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_word
-	.section	.rodata.str1.4,"aMS",@progbits,1
-	.align	2
-$LC0:
-	.ascii	"MIPS R3000 CPU\r\n"
-	.ascii	"Mul/Div Test\r\n\000"
-	.align	2
-$LC1:
-	.ascii	"Failed: \000"
-	.align	2
-$LC2:
-	.ascii	"d*quot = \000"
-	.align	2
-$LC3:
-	.ascii	"\r\n\000"
-	.align	2
-$LC4:
-	.ascii	"Iteration \000"
-	.align	2
-$LC5:
-	.ascii	": Passed\r\n\000"
-	.text
-	.align	2
-	.globl	main
-	.ent	main
-main:
-	.frame	$sp,88,$31		# vars= 40, regs= 7/0, args= 16, gp= 0
-	.mask	0x803f0000,-8
-	.fmask	0x00000000,0
-	lw	$2,$LC0
-	addiu	$sp,$sp,-88
-	sw	$2,16($sp)
-	lw	$3,$LC0+4
-	lw	$2,$LC0+8
-	sw	$3,20($sp)
-	sw	$2,24($sp)
-	lw	$3,$LC0+12
-	lw	$2,$LC0+16
-	sw	$3,28($sp)
-	sw	$2,32($sp)
-	lw	$3,$LC0+20
-	lw	$2,$LC0+24
-	sw	$3,36($sp)
-	sw	$2,40($sp)
-	lhu	$3,$LC0+28
-	lbu	$2,$LC0+30
-	li	$5,-2147483648			# 0xffffffff80000000
-	ori	$6,$5,0x9
-	sh	$3,44($sp)
-	sb	$2,46($sp)
-	ori	$5,$5,0x8
-	li	$3,53
-	li	$2,85
-	li	$4,426770432			# 0x19700000
-	sb	$3,0($6)
-	ori	$4,$4,0x1031
-	sb	$2,0($5)
-	sw	$31,80($sp)
-	sw	$21,76($sp)
-	sw	$19,68($sp)
-	sw	$20,72($sp)
-	sw	$18,64($sp)
-	sw	$17,60($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	srand
-	sw	$16,56($sp)
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	addiu	$4,$sp,16
-	.set	macro
-	.set	reorder
-
-	move	$21,$0
-	addiu	$19,$sp,48
-	move	$20,$0
-$L44:
-	.set	noreorder
-	.set	nomacro
-	j	$L43
-	li	$18,1			# 0x1
-	.set	macro
-	.set	reorder
-
-$L51:
-	beq	$3,$0,$L50
-$L43:
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	addiu	$18,$18,1
-	.set	macro
-	.set	reorder
-
-	sll	$3,$2,16
-	sll	$2,$2,8
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	xor	$16,$2,$3
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	xor	$17,$2,$16
-	.set	macro
-	.set	reorder
-
-	sll	$3,$2,16
-	sll	$2,$2,8
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	xor	$16,$2,$3
-	.set	macro
-	.set	reorder
-
-	xor	$16,$2,$16
-	move	$6,$16
-	move	$4,$19
-	.set	noreorder
-	.set	nomacro
-	jal	div
-	move	$5,$17
-	.set	macro
-	.set	reorder
-
-	lw	$2,48($sp)
-	mult	$2,$16
-	lw	$2,52($sp)
-	mflo	$16
-	addu	$2,$2,$16
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$17,$L51
-	slt	$3,$18,1000
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC1
-	jal	sputs
-	la	$4,$LC2
-	jal	sputs
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$16
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC3
-	jal	sputs
-	lw	$31,80($sp)
-	lw	$21,76($sp)
-	lw	$20,72($sp)
-	lw	$19,68($sp)
-	lw	$18,64($sp)
-	lw	$17,60($sp)
-	lw	$16,56($sp)
-	li	$2,-1			# 0xffffffffffffffff
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,88
-	.set	macro
-	.set	reorder
-
-$L50:
-	addiu	$20,$20,1
-	slt	$2,$20,1000
-	bne	$2,$0,$L44
-	la	$4,$LC4
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$20,$0
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$21
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC5
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	addiu	$21,$21,1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	j	$L43
-	li	$18,1			# 0x1
-	.set	macro
-	.set	reorder
-
-	.end	main
diff --git a/lib/CPUs/MIPS/sim/asm/mult.txt b/lib/CPUs/MIPS/sim/asm/mult.txt
deleted file mode 100644
index 72f9226..0000000
--- a/lib/CPUs/MIPS/sim/asm/mult.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-0x12345678 x 0x87654321
-HI      = f76c768d   LO      = 70b88d78		signed
-HI      = 09a0cd05   LO      = 70b88d78		unsigned
-
-0x87654321 x 0x12345678
-HI      = f76c768d   LO      = 70b88d78		signed
-HI      = 09a0cd05   LO      = 70b88d78		unsigned
-
-0x12345678 x 0x12345678
-HI      = 014b66dc   LO      = 1df4d840		signed
-HI      = 014b66dc   LO      = 1df4d840		unsigned
-
-0x87654321 x 0x87654321
-HI      = 38d16e98   LO      = d7a44a41		signed
-HI      = 479bf4da   LO      = d7a44a41		unsigned
-
-
-p1 * n2 = not(p1 * (1 + not(n2)))
-
-n1 * p1 = not((1 + not(n1)) * p2)
-
-p1 * p2 = p1 * p2
-
-n1 * n2 = not(n1) * not(n2);
-
-
-12345678 * ( 87654321 not and FFFFFFFF ) = + 12345677 =
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/rmd160.s b/lib/CPUs/MIPS/sim/asm/rmd160.s
deleted file mode 100644
index 6028ab9..0000000
--- a/lib/CPUs/MIPS/sim/asm/rmd160.s
+++ /dev/null
@@ -1,2482 +0,0 @@
-	.file	1 "rmd160.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	MDinit
-	.ent	MDinit
-MDinit:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-1009647616			# 0xffffffffc3d20000
-	ori	$2,$2,0xe1f0
-	sw	$2,16($4)
-	li	$3,1732575232			# 0x67450000
-	li	$2,-271777792			# 0xffffffffefcd0000
-	ori	$3,$3,0x2301
-	ori	$2,$2,0xab89
-	sw	$3,0($4)
-	sw	$2,4($4)
-	li	$3,-1732640768			# 0xffffffff98ba0000
-	li	$2,271712256			# 0x10320000
-	ori	$3,$3,0xdcfe
-	ori	$2,$2,0x5476
-	sw	$3,8($4)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	sw	$2,12($4)
-	.set	macro
-	.set	reorder
-
-	.end	MDinit
-	.align	2
-	.globl	compress
-	.ent	compress
-compress:
-	.frame	$sp,128,$31		# vars= 88, regs= 9/0, args= 0, gp= 0
-	.mask	0x40ff0000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-128
-	sw	$19,100($sp)
-	lw	$19,12($4)
-	sw	$20,104($sp)
-	lw	$24,4($4)
-	lw	$20,8($4)
-	sw	$fp,120($sp)
-	sw	$23,116($sp)
-	sw	$22,112($sp)
-	sw	$21,108($sp)
-	sw	$18,96($sp)
-	sw	$17,92($sp)
-	sw	$16,88($sp)
-	nor	$2,$0,$19
-	lw	$6,20($5)
-	lw	$7,0($5)
-	lw	$21,0($4)
-	xor	$3,$24,$20
-	or	$2,$2,$20
-	xor	$3,$3,$19
-	xor	$2,$2,$24
-	addu	$3,$3,$7
-	move	$17,$21
-	addu	$2,$2,$6
-	li	$11,1352794112			# 0x50a20000
-	ori	$11,$11,0x8be6
-	addu	$21,$21,$3
-	addu	$2,$2,$17
-	addu	$17,$2,$11
-	lw	$25,16($4)
-	sw	$6,12($sp)
-	srl	$3,$21,21
-	srl	$8,$20,22
-	sll	$6,$20,10
-	sll	$2,$21,11
-	or	$23,$6,$8
-	or	$2,$2,$3
-	srl	$7,$17,24
-	sll	$3,$17,8
-	addu	$21,$2,$25
-	or	$3,$3,$7
-	nor	$2,$0,$23
-	addu	$17,$3,$25
-	lw	$8,56($5)
-	lw	$6,4($5)
-	xor	$3,$21,$24
-	or	$2,$2,$24
-	xor	$3,$3,$23
-	xor	$2,$2,$17
-	move	$fp,$25
-	addu	$3,$3,$6
-	addu	$2,$2,$8
-	addu	$25,$25,$3
-	addu	$2,$2,$fp
-	addu	$fp,$2,$11
-	sw	$8,36($sp)
-	srl	$3,$25,18
-	srl	$8,$24,22
-	sll	$6,$24,10
-	sll	$2,$25,14
-	or	$22,$6,$8
-	or	$2,$2,$3
-	srl	$7,$fp,23
-	sll	$3,$fp,9
-	addu	$25,$2,$19
-	or	$3,$3,$7
-	nor	$2,$0,$22
-	addu	$fp,$3,$19
-	lw	$7,8($5)
-	lw	$8,28($5)
-	xor	$3,$25,$21
-	or	$2,$2,$17
-	xor	$3,$3,$22
-	xor	$2,$2,$fp
-	move	$18,$19
-	addu	$3,$3,$7
-	addu	$2,$2,$8
-	addu	$19,$19,$3
-	addu	$2,$2,$18
-	addu	$18,$2,$11
-	sw	$7,0($sp)
-	srl	$6,$17,22
-	srl	$7,$19,17
-	sll	$3,$19,15
-	sll	$2,$17,10
-	or	$17,$2,$6
-	or	$3,$3,$7
-	srl	$2,$18,23
-	sll	$6,$18,9
-	addu	$19,$3,$23
-	or	$6,$6,$2
-	srl	$7,$21,22
-	nor	$2,$0,$17
-	sll	$3,$21,10
-	addu	$18,$6,$23
-	or	$21,$3,$7
-	lw	$6,0($5)
-	lw	$7,12($5)
-	xor	$3,$19,$25
-	or	$2,$2,$fp
-	xor	$3,$3,$21
-	xor	$2,$2,$18
-	addu	$3,$3,$7
-	addu	$2,$2,$6
-	addu	$20,$23,$3
-	addu	$2,$2,$23
-	addu	$23,$2,$11
-	sw	$6,8($sp)
-	srl	$7,$20,20
-	srl	$6,$fp,22
-	sll	$3,$20,12
-	sll	$2,$fp,10
-	or	$fp,$2,$6
-	or	$3,$3,$7
-	srl	$2,$23,21
-	sll	$6,$23,11
-	addu	$20,$3,$22
-	or	$6,$6,$2
-	srl	$7,$25,22
-	nor	$2,$0,$fp
-	sll	$3,$25,10
-	addu	$23,$6,$22
-	or	$25,$3,$7
-	lw	$6,16($5)
-	sw	$8,20($sp)
-	xor	$3,$20,$19
-	lw	$8,36($5)
-	or	$2,$2,$18
-	xor	$3,$3,$25
-	xor	$2,$2,$23
-	addu	$3,$3,$6
-	addu	$2,$2,$8
-	addu	$24,$22,$3
-	addu	$2,$2,$22
-	addu	$22,$2,$11
-	srl	$7,$24,27
-	srl	$6,$18,22
-	sll	$3,$24,5
-	sll	$2,$18,10
-	or	$18,$2,$6
-	or	$3,$3,$7
-	srl	$2,$22,19
-	sll	$6,$22,13
-	addu	$24,$3,$21
-	or	$6,$6,$2
-	srl	$7,$19,22
-	nor	$2,$0,$18
-	sll	$3,$19,10
-	addu	$22,$6,$17
-	or	$19,$3,$7
-	or	$2,$2,$23
-	lw	$7,0($sp)
-	sw	$8,16($sp)
-	xor	$3,$24,$20
-	lw	$8,20($5)
-	xor	$2,$2,$22
-	xor	$3,$3,$19
-	addu	$2,$2,$7
-	addu	$3,$3,$8
-	addu	$2,$2,$17
-	addu	$17,$2,$11
-	addu	$21,$21,$3
-	srl	$6,$23,22
-	sll	$2,$23,10
-	or	$23,$2,$6
-	sw	$7,28($sp)
-	srl	$2,$17,17
-	srl	$7,$21,24
-	sll	$3,$21,8
-	sll	$6,$17,15
-	or	$3,$3,$7
-	or	$6,$6,$2
-	srl	$7,$20,22
-	sll	$2,$20,10
-	or	$20,$2,$7
-	lw	$2,44($5)
-	addu	$21,$3,$25
-	nor	$3,$0,$23
-	sw	$2,44($sp)
-	addu	$17,$6,$fp
-	lw	$7,44($sp)
-	lw	$6,24($5)
-	xor	$2,$21,$24
-	or	$3,$3,$22
-	xor	$2,$2,$20
-	xor	$3,$3,$17
-	addu	$2,$2,$6
-	addu	$3,$3,$7
-	addu	$25,$25,$2
-	addu	$3,$3,$fp
-	addu	$fp,$3,$11
-	srl	$7,$25,25
-	srl	$6,$22,22
-	sll	$3,$25,7
-	sll	$2,$22,10
-	or	$22,$2,$6
-	or	$3,$3,$7
-	srl	$2,$fp,17
-	sll	$6,$fp,15
-	addu	$25,$3,$19
-	or	$6,$6,$2
-	srl	$7,$24,22
-	nor	$2,$0,$22
-	sll	$3,$24,10
-	addu	$fp,$6,$18
-	or	$24,$3,$7
-	lw	$8,16($5)
-	lw	$6,28($5)
-	xor	$3,$25,$21
-	or	$2,$2,$17
-	xor	$3,$3,$24
-	xor	$2,$2,$fp
-	addu	$3,$3,$6
-	addu	$2,$2,$8
-	addu	$19,$19,$3
-	addu	$2,$2,$18
-	addu	$18,$2,$11
-	srl	$7,$19,23
-	srl	$6,$17,22
-	sll	$3,$19,9
-	sll	$2,$17,10
-	or	$17,$2,$6
-	or	$3,$3,$7
-	srl	$2,$18,27
-	sll	$6,$18,5
-	addu	$19,$3,$20
-	or	$6,$6,$2
-	srl	$7,$21,22
-	nor	$3,$0,$17
-	sll	$2,$21,10
-	addu	$18,$6,$23
-	or	$21,$2,$7
-	sw	$8,4($sp)
-	lw	$7,52($5)
-	lw	$8,32($5)
-	xor	$2,$19,$25
-	or	$3,$3,$fp
-	xor	$2,$2,$21
-	xor	$3,$3,$18
-	addu	$2,$2,$8
-	addu	$3,$3,$7
-	addu	$20,$20,$2
-	addu	$3,$3,$23
-	addu	$23,$3,$11
-	sw	$7,52($sp)
-	srl	$6,$fp,22
-	srl	$7,$20,21
-	sll	$3,$20,11
-	sll	$2,$fp,10
-	or	$fp,$2,$6
-	or	$3,$3,$7
-	srl	$2,$23,25
-	sll	$6,$23,7
-	addu	$20,$3,$24
-	or	$6,$6,$2
-	srl	$7,$25,22
-	nor	$3,$0,$fp
-	sll	$2,$25,10
-	lw	$12,24($5)
-	addu	$23,$6,$22
-	or	$25,$2,$7
-	lw	$6,36($5)
-	xor	$2,$20,$19
-	or	$3,$3,$18
-	xor	$2,$2,$25
-	xor	$3,$3,$23
-	addu	$2,$2,$6
-	addu	$3,$3,$12
-	addu	$24,$24,$2
-	addu	$3,$3,$22
-	addu	$22,$3,$11
-	srl	$7,$24,19
-	srl	$6,$18,22
-	sll	$3,$24,13
-	sll	$2,$18,10
-	or	$18,$2,$6
-	or	$3,$3,$7
-	srl	$2,$22,25
-	sll	$6,$22,7
-	addu	$24,$3,$21
-	or	$6,$6,$2
-	srl	$7,$19,22
-	nor	$3,$0,$18
-	sll	$2,$19,10
-	addu	$22,$6,$17
-	or	$19,$2,$7
-	lw	$8,40($5)
-	lw	$7,60($5)
-	xor	$2,$24,$20
-	or	$3,$3,$23
-	xor	$2,$2,$19
-	xor	$3,$3,$22
-	addu	$2,$2,$8
-	addu	$3,$3,$7
-	addu	$21,$21,$2
-	addu	$3,$3,$17
-	sw	$7,48($sp)
-	addu	$17,$3,$11
-	srl	$7,$21,18
-	srl	$6,$23,22
-	sll	$3,$21,14
-	sll	$2,$23,10
-	or	$23,$2,$6
-	or	$3,$3,$7
-	srl	$2,$17,24
-	sll	$6,$17,8
-	addu	$21,$3,$25
-	or	$6,$6,$2
-	srl	$7,$20,22
-	nor	$3,$0,$23
-	sll	$2,$20,10
-	lw	$13,32($5)
-	addu	$17,$6,$fp
-	or	$20,$2,$7
-	lw	$6,44($5)
-	xor	$2,$21,$24
-	or	$3,$3,$22
-	xor	$2,$2,$20
-	xor	$3,$3,$17
-	addu	$2,$2,$6
-	addu	$3,$3,$13
-	addu	$25,$25,$2
-	addu	$3,$3,$fp
-	addu	$fp,$3,$11
-	srl	$7,$25,17
-	srl	$6,$22,22
-	sll	$3,$25,15
-	sll	$2,$22,10
-	or	$22,$2,$6
-	or	$3,$3,$7
-	srl	$2,$fp,21
-	sll	$6,$fp,11
-	addu	$25,$3,$19
-	or	$6,$6,$2
-	srl	$7,$24,22
-	nor	$2,$0,$22
-	sll	$3,$24,10
-	addu	$fp,$6,$18
-	or	$24,$3,$7
-	lw	$8,48($5)
-	lw	$7,4($5)
-	xor	$3,$25,$21
-	or	$2,$2,$17
-	xor	$3,$3,$24
-	xor	$2,$2,$fp
-	addu	$3,$3,$8
-	addu	$2,$2,$7
-	addu	$19,$19,$3
-	addu	$2,$2,$18
-	sw	$7,40($sp)
-	addu	$18,$2,$11
-	srl	$7,$19,26
-	srl	$6,$17,22
-	sll	$3,$19,6
-	sll	$2,$17,10
-	or	$17,$2,$6
-	or	$3,$3,$7
-	srl	$2,$18,18
-	sll	$6,$18,14
-	addu	$19,$3,$20
-	or	$6,$6,$2
-	srl	$7,$21,22
-	nor	$2,$0,$17
-	sll	$3,$21,10
-	addu	$18,$6,$23
-	or	$21,$3,$7
-	lw	$6,40($5)
-	lw	$7,52($5)
-	xor	$3,$19,$25
-	or	$2,$2,$fp
-	xor	$3,$3,$21
-	xor	$2,$2,$18
-	addu	$3,$3,$7
-	addu	$2,$2,$6
-	addu	$20,$20,$3
-	addu	$2,$2,$23
-	sw	$6,32($sp)
-	addu	$23,$2,$11
-	srl	$7,$20,25
-	srl	$6,$fp,22
-	sll	$3,$20,7
-	sll	$2,$fp,10
-	or	$fp,$2,$6
-	or	$3,$3,$7
-	srl	$2,$23,18
-	sll	$6,$23,14
-	addu	$20,$3,$24
-	or	$6,$6,$2
-	srl	$7,$25,22
-	nor	$3,$0,$fp
-	sll	$2,$25,10
-	lw	$16,12($5)
-	addu	$23,$6,$22
-	or	$25,$2,$7
-	lw	$8,56($5)
-	xor	$2,$20,$19
-	or	$3,$3,$18
-	xor	$2,$2,$25
-	xor	$3,$3,$23
-	addu	$2,$2,$8
-	addu	$3,$3,$16
-	addu	$24,$24,$2
-	addu	$3,$3,$22
-	addu	$22,$3,$11
-	srl	$7,$24,23
-	sll	$3,$24,9
-	or	$3,$3,$7
-	srl	$6,$18,22
-	sll	$2,$18,10
-	addu	$24,$3,$21
-	or	$18,$2,$6
-	srl	$7,$19,22
-	srl	$2,$22,20
-	sll	$6,$22,12
-	sll	$3,$19,10
-	or	$19,$3,$7
-	or	$6,$6,$2
-	lw	$7,60($5)
-	xor	$3,$24,$20
-	nor	$2,$0,$18
-	addu	$22,$6,$17
-	or	$2,$2,$23
-	lw	$6,48($5)
-	xor	$3,$3,$19
-	addu	$3,$3,$7
-	xor	$2,$2,$22
-	addu	$21,$21,$3
-	addu	$2,$2,$6
-	sw	$6,24($sp)
-	srl	$3,$21,24
-	addu	$2,$2,$17
-	sll	$6,$21,8
-	addu	$17,$2,$11
-	or	$6,$6,$3
-	srl	$7,$23,22
-	sll	$2,$23,10
-	or	$23,$2,$7
-	addu	$21,$6,$25
-	srl	$8,$17,26
-	sll	$3,$17,6
-	srl	$7,$20,22
-	sll	$2,$20,10
-	or	$20,$2,$7
-	or	$3,$3,$8
-	nor	$6,$0,$21
-	addu	$17,$3,$fp
-	lw	$8,28($5)
-	and	$6,$6,$20
-	and	$2,$21,$24
-	nor	$7,$0,$23
-	and	$7,$7,$22
-	and	$3,$17,$23
-	or	$2,$2,$6
-	or	$3,$3,$7
-	addu	$2,$2,$8
-	li	$11,1518469120			# 0x5a820000
-	ori	$11,$11,0x7999
-	addu	$2,$2,$25
-	addu	$3,$3,$12
-	li	$10,1548550144			# 0x5c4d0000
-	ori	$10,$10,0xd124
-	addu	$25,$2,$11
-	addu	$3,$3,$fp
-	addu	$fp,$3,$10
-	srl	$8,$25,25
-	sll	$3,$25,7
-	srl	$9,$fp,23
-	or	$3,$3,$8
-	srl	$7,$22,22
-	sll	$6,$fp,9
-	sll	$2,$22,10
-	addu	$25,$3,$19
-	or	$22,$2,$7
-	or	$6,$6,$9
-	srl	$3,$24,22
-	sll	$2,$24,10
-	addu	$fp,$6,$18
-	or	$24,$2,$3
-	nor	$6,$0,$25
-	and	$6,$6,$24
-	and	$2,$25,$21
-	nor	$7,$0,$22
-	and	$7,$7,$17
-	and	$3,$fp,$22
-	or	$2,$2,$6
-	lw	$6,44($sp)
-	or	$3,$3,$7
-	lw	$7,16($5)
-	addu	$3,$3,$6
-	addu	$3,$3,$18
-	addu	$2,$2,$7
-	addu	$18,$3,$10
-	addu	$2,$2,$19
-	addu	$19,$2,$11
-	srl	$7,$18,19
-	srl	$6,$17,22
-	sll	$3,$18,13
-	sll	$2,$17,10
-	or	$17,$2,$6
-	or	$3,$3,$7
-	srl	$6,$19,26
-	sll	$2,$19,6
-	addu	$18,$3,$23
-	or	$2,$2,$6
-	nor	$6,$0,$17
-	addu	$19,$2,$20
-	and	$6,$6,$fp
-	and	$2,$18,$17
-	srl	$7,$21,22
-	sll	$3,$21,10
-	or	$2,$2,$6
-	or	$21,$3,$7
-	addu	$2,$2,$16
-	nor	$3,$0,$19
-	lw	$8,52($5)
-	and	$3,$3,$21
-	and	$6,$19,$25
-	addu	$2,$2,$23
-	addu	$23,$2,$10
-	or	$6,$6,$3
-	addu	$6,$6,$8
-	srl	$7,$fp,22
-	srl	$8,$23,17
-	sll	$3,$23,15
-	sll	$2,$fp,10
-	or	$fp,$2,$7
-	or	$3,$3,$8
-	addu	$6,$6,$20
-	addu	$23,$3,$22
-	addu	$20,$6,$11
-	nor	$2,$0,$fp
-	srl	$7,$20,24
-	and	$2,$2,$18
-	and	$3,$23,$fp
-	sll	$6,$20,8
-	or	$6,$6,$7
-	or	$3,$3,$2
-	srl	$7,$25,22
-	sll	$2,$25,10
-	or	$25,$2,$7
-	lw	$2,20($sp)
-	addu	$20,$6,$24
-	addu	$3,$3,$2
-	addu	$3,$3,$22
-	nor	$2,$0,$20
-	addu	$22,$3,$10
-	and	$2,$2,$25
-	lw	$3,4($5)
-	and	$6,$20,$19
-	or	$6,$6,$2
-	srl	$8,$22,25
-	addu	$6,$6,$3
-	srl	$7,$18,22
-	sll	$3,$22,7
-	sll	$2,$18,10
-	or	$18,$2,$7
-	or	$3,$3,$8
-	addu	$22,$3,$17
-	nor	$7,$0,$18
-	and	$7,$7,$23
-	and	$3,$22,$18
-	addu	$6,$6,$24
-	addu	$24,$6,$11
-	or	$3,$3,$7
-	lw	$7,8($sp)
-	srl	$6,$24,19
-	sll	$2,$24,13
-	or	$2,$2,$6
-	addu	$3,$3,$7
-	addu	$24,$2,$21
-	srl	$6,$19,22
-	sll	$2,$19,10
-	addu	$3,$3,$17
-	or	$19,$2,$6
-	addu	$17,$3,$10
-	nor	$2,$0,$24
-	and	$2,$2,$19
-	and	$3,$24,$20
-	srl	$8,$17,20
-	sll	$7,$17,12
-	or	$7,$7,$8
-	or	$3,$3,$2
-	lw	$8,40($5)
-	srl	$6,$23,22
-	sll	$2,$23,10
-	or	$23,$2,$6
-	addu	$17,$7,$fp
-	addu	$3,$3,$8
-	nor	$6,$0,$23
-	and	$6,$6,$22
-	and	$2,$17,$23
-	addu	$3,$3,$21
-	addu	$21,$3,$11
-	or	$2,$2,$6
-	lw	$6,52($sp)
-	srl	$7,$21,21
-	sll	$3,$21,11
-	or	$3,$3,$7
-	addu	$2,$2,$6
-	addu	$21,$3,$25
-	addu	$2,$2,$fp
-	srl	$6,$20,22
-	sll	$3,$20,10
-	or	$20,$3,$6
-	addu	$fp,$2,$10
-	nor	$7,$0,$21
-	and	$7,$7,$20
-	srl	$9,$fp,24
-	and	$6,$21,$24
-	srl	$8,$22,22
-	sll	$3,$fp,8
-	sll	$2,$22,10
-	or	$22,$2,$8
-	or	$3,$3,$9
-	or	$6,$6,$7
-	addu	$fp,$3,$18
-	addu	$6,$6,$12
-	nor	$3,$0,$22
-	lw	$8,12($sp)
-	and	$3,$3,$17
-	and	$2,$fp,$22
-	addu	$6,$6,$25
-	addu	$25,$6,$11
-	or	$2,$2,$3
-	srl	$7,$25,23
-	addu	$2,$2,$8
-	sll	$3,$25,9
-	or	$3,$3,$7
-	addu	$2,$2,$18
-	addu	$25,$3,$19
-	addu	$18,$2,$10
-	srl	$3,$24,22
-	sll	$2,$24,10
-	or	$24,$2,$3
-	srl	$6,$17,22
-	nor	$3,$0,$25
-	sll	$2,$17,10
-	or	$17,$2,$6
-	srl	$8,$18,23
-	and	$3,$3,$24
-	and	$2,$25,$21
-	sll	$7,$18,9
-	or	$7,$7,$8
-	or	$2,$2,$3
-	lw	$3,60($5)
-	addu	$18,$7,$23
-	nor	$6,$0,$17
-	and	$6,$6,$fp
-	addu	$2,$2,$3
-	and	$3,$18,$17
-	or	$3,$3,$6
-	lw	$6,32($sp)
-	addu	$2,$2,$19
-	addu	$19,$2,$11
-	addu	$3,$3,$6
-	addu	$3,$3,$23
-	srl	$6,$19,25
-	sll	$2,$19,7
-	addu	$23,$3,$10
-	or	$2,$2,$6
-	addu	$19,$2,$20
-	srl	$9,$23,21
-	srl	$8,$21,22
-	srl	$7,$fp,22
-	sll	$3,$23,11
-	sll	$6,$21,10
-	sll	$2,$fp,10
-	or	$fp,$2,$7
-	or	$21,$6,$8
-	or	$3,$3,$9
-	nor	$2,$0,$19
-	addu	$23,$3,$22
-	and	$2,$2,$21
-	and	$3,$19,$25
-	nor	$6,$0,$fp
-	lw	$8,36($sp)
-	and	$6,$6,$18
-	or	$3,$3,$2
-	and	$2,$23,$fp
-	or	$2,$2,$6
-	addu	$3,$3,$16
-	addu	$3,$3,$20
-	addu	$2,$2,$8
-	addu	$20,$3,$11
-	addu	$2,$2,$22
-	addu	$22,$2,$10
-	srl	$3,$20,17
-	sll	$6,$20,15
-	or	$6,$6,$3
-	srl	$8,$22,25
-	srl	$7,$18,22
-	sll	$3,$22,7
-	sll	$2,$18,10
-	or	$18,$2,$7
-	addu	$20,$6,$24
-	or	$3,$3,$8
-	srl	$7,$25,22
-	sll	$2,$25,10
-	or	$25,$2,$7
-	addu	$22,$3,$17
-	nor	$6,$0,$20
-	nor	$7,$0,$18
-	and	$6,$6,$25
-	and	$7,$7,$23
-	and	$2,$20,$19
-	and	$3,$22,$18
-	or	$2,$2,$6
-	or	$3,$3,$7
-	lw	$6,48($5)
-	lw	$7,48($sp)
-	addu	$2,$2,$6
-	addu	$3,$3,$7
-	addu	$2,$2,$24
-	addu	$3,$3,$17
-	addu	$24,$2,$11
-	addu	$17,$3,$10
-	srl	$8,$24,25
-	srl	$9,$17,25
-	srl	$7,$23,22
-	sll	$3,$24,7
-	sll	$6,$17,7
-	sll	$2,$23,10
-	or	$23,$2,$7
-	or	$3,$3,$8
-	or	$6,$6,$9
-	addu	$24,$3,$21
-	addu	$17,$6,$fp
-	srl	$3,$19,22
-	nor	$7,$0,$23
-	sll	$2,$19,10
-	or	$19,$2,$3
-	and	$7,$7,$22
-	and	$3,$17,$23
-	nor	$6,$0,$24
-	lw	$8,0($5)
-	and	$6,$6,$19
-	and	$2,$24,$20
-	or	$3,$3,$7
-	or	$2,$2,$6
-	addu	$3,$3,$13
-	addu	$3,$3,$fp
-	addu	$2,$2,$8
-	addu	$fp,$3,$10
-	addu	$2,$2,$21
-	addu	$21,$2,$11
-	srl	$7,$fp,20
-	srl	$6,$22,22
-	sll	$3,$fp,12
-	sll	$2,$22,10
-	or	$22,$2,$6
-	or	$3,$3,$7
-	srl	$6,$21,20
-	sll	$2,$21,12
-	addu	$fp,$3,$18
-	or	$2,$2,$6
-	nor	$6,$0,$22
-	addu	$21,$2,$25
-	and	$6,$6,$17
-	and	$2,$fp,$22
-	srl	$7,$20,22
-	sll	$3,$20,10
-	or	$2,$2,$6
-	lw	$6,24($sp)
-	or	$20,$3,$7
-	nor	$3,$0,$21
-	lw	$7,36($5)
-	and	$3,$3,$20
-	addu	$2,$2,$6
-	and	$6,$21,$24
-	or	$6,$6,$3
-	addu	$2,$2,$18
-	addu	$18,$2,$10
-	addu	$6,$6,$7
-	srl	$8,$18,25
-	addu	$6,$6,$25
-	srl	$7,$17,22
-	sll	$3,$18,7
-	sll	$2,$17,10
-	or	$17,$2,$7
-	addu	$25,$6,$11
-	or	$3,$3,$8
-	addu	$18,$3,$23
-	srl	$7,$25,17
-	sll	$6,$25,15
-	nor	$2,$0,$17
-	or	$6,$6,$7
-	and	$2,$2,$fp
-	and	$3,$18,$17
-	addu	$25,$6,$19
-	lw	$8,4($sp)
-	or	$3,$3,$2
-	srl	$7,$24,22
-	sll	$2,$24,10
-	or	$24,$2,$7
-	nor	$2,$0,$25
-	and	$2,$2,$24
-	and	$6,$25,$21
-	addu	$3,$3,$8
-	addu	$3,$3,$23
-	or	$6,$6,$2
-	lw	$2,20($5)
-	addu	$23,$3,$10
-	srl	$8,$23,26
-	addu	$6,$6,$2
-	srl	$7,$fp,22
-	sll	$3,$23,6
-	sll	$2,$fp,10
-	or	$fp,$2,$7
-	or	$3,$3,$8
-	addu	$23,$3,$22
-	addu	$6,$6,$19
-	nor	$7,$0,$fp
-	addu	$19,$6,$11
-	and	$7,$7,$18
-	and	$3,$23,$fp
-	srl	$6,$19,23
-	sll	$2,$19,9
-	or	$3,$3,$7
-	lw	$7,16($sp)
-	or	$2,$2,$6
-	addu	$19,$2,$20
-	srl	$6,$21,22
-	addu	$3,$3,$7
-	sll	$2,$21,10
-	or	$21,$2,$6
-	addu	$3,$3,$22
-	nor	$2,$0,$19
-	addu	$22,$3,$10
-	and	$2,$2,$21
-	and	$3,$19,$25
-	srl	$8,$22,17
-	or	$3,$3,$2
-	srl	$6,$18,22
-	sll	$7,$22,15
-	sll	$2,$18,10
-	or	$18,$2,$6
-	or	$7,$7,$8
-	lw	$8,0($sp)
-	addu	$22,$7,$17
-	nor	$6,$0,$18
-	and	$6,$6,$23
-	and	$2,$22,$18
-	addu	$3,$3,$8
-	addu	$3,$3,$20
-	or	$2,$2,$6
-	lw	$6,40($sp)
-	addu	$20,$3,$11
-	srl	$7,$20,21
-	sll	$3,$20,11
-	addu	$2,$2,$6
-	or	$3,$3,$7
-	addu	$2,$2,$17
-	addu	$20,$3,$24
-	addu	$17,$2,$10
-	srl	$6,$25,22
-	sll	$3,$25,10
-	or	$25,$3,$6
-	srl	$9,$17,19
-	nor	$7,$0,$20
-	srl	$8,$23,22
-	sll	$3,$17,13
-	sll	$2,$23,10
-	or	$23,$2,$8
-	and	$7,$7,$25
-	and	$6,$20,$19
-	or	$3,$3,$9
-	addu	$17,$3,$fp
-	or	$6,$6,$7
-	nor	$3,$0,$23
-	lw	$7,56($5)
-	lw	$8,28($sp)
-	and	$3,$3,$22
-	and	$2,$17,$23
-	addu	$6,$6,$7
-	or	$2,$2,$3
-	addu	$6,$6,$24
-	addu	$2,$2,$8
-	addu	$24,$6,$11
-	addu	$2,$2,$fp
-	addu	$fp,$2,$10
-	srl	$7,$24,25
-	sll	$3,$24,7
-	srl	$6,$19,22
-	sll	$2,$19,10
-	or	$19,$2,$6
-	or	$3,$3,$7
-	sll	$6,$fp,11
-	srl	$7,$fp,21
-	addu	$24,$3,$21
-	or	$6,$6,$7
-	addu	$fp,$6,$18
-	nor	$3,$0,$24
-	srl	$7,$22,22
-	sll	$6,$22,10
-	or	$22,$6,$7
-	and	$3,$3,$19
-	lw	$6,44($5)
-	and	$2,$24,$20
-	or	$2,$2,$3
-	nor	$3,$0,$17
-	lw	$7,48($sp)
-	or	$3,$3,$fp
-	addu	$2,$2,$6
-	addu	$2,$2,$21
-	xor	$3,$3,$22
-	addu	$21,$2,$11
-	addu	$3,$3,$7
-	li	$10,1836056576			# 0x6d700000
-	ori	$10,$10,0x3ef3
-	srl	$6,$21,19
-	addu	$3,$3,$18
-	sll	$2,$21,13
-	addu	$18,$3,$10
-	or	$2,$2,$6
-	addu	$21,$2,$25
-	srl	$8,$18,23
-	srl	$6,$20,22
-	sll	$3,$18,9
-	sll	$2,$20,10
-	or	$20,$2,$6
-	or	$3,$3,$8
-	nor	$7,$0,$21
-	addu	$18,$3,$23
-	and	$8,$7,$20
-	and	$3,$21,$24
-	srl	$9,$17,22
-	nor	$2,$0,$fp
-	sll	$6,$17,10
-	or	$17,$6,$9
-	or	$3,$3,$8
-	lw	$6,12($sp)
-	or	$2,$2,$18
-	xor	$2,$2,$17
-	addu	$3,$3,$13
-	addu	$3,$3,$25
-	addu	$2,$2,$6
-	addu	$25,$3,$11
-	addu	$2,$2,$23
-	addu	$23,$2,$10
-	srl	$3,$25,20
-	sll	$2,$25,12
-	or	$2,$2,$3
-	srl	$6,$23,25
-	sll	$3,$23,7
-	addu	$25,$2,$19
-	or	$3,$3,$6
-	sll	$2,$24,10
-	srl	$6,$24,22
-	addu	$23,$3,$22
-	or	$24,$2,$6
-	or	$7,$7,$25
-	srl	$6,$fp,22
-	nor	$2,$0,$18
-	sll	$3,$fp,10
-	or	$fp,$3,$6
-	xor	$7,$7,$24
-	lw	$3,40($sp)
-	or	$2,$2,$23
-	xor	$2,$2,$fp
-	addu	$7,$7,$16
-	li	$9,1859715072			# 0x6ed90000
-	ori	$9,$9,0xeba1
-	addu	$7,$7,$19
-	addu	$2,$2,$3
-	addu	$19,$7,$9
-	addu	$2,$2,$22
-	addu	$22,$2,$10
-	srl	$3,$19,21
-	sll	$2,$19,11
-	or	$2,$2,$3
-	srl	$6,$22,17
-	sll	$3,$22,15
-	addu	$19,$2,$20
-	or	$3,$3,$6
-	srl	$7,$21,22
-	sll	$2,$21,10
-	addu	$22,$3,$17
-	or	$21,$2,$7
-	nor	$6,$0,$25
-	srl	$7,$18,22
-	sll	$3,$18,10
-	or	$18,$3,$7
-	or	$6,$6,$19
-	lw	$7,40($5)
-	nor	$2,$0,$23
-	xor	$6,$6,$21
-	or	$2,$2,$22
-	xor	$2,$2,$18
-	addu	$6,$6,$7
-	addu	$6,$6,$20
-	addu	$2,$2,$16
-	addu	$20,$6,$9
-	addu	$2,$2,$17
-	addu	$17,$2,$10
-	srl	$3,$20,19
-	sll	$2,$20,13
-	or	$2,$2,$3
-	srl	$6,$17,21
-	sll	$3,$17,11
-	addu	$20,$2,$24
-	or	$3,$3,$6
-	srl	$7,$25,22
-	nor	$6,$0,$19
-	sll	$2,$25,10
-	addu	$17,$3,$fp
-	or	$25,$2,$7
-	lw	$8,56($5)
-	or	$6,$6,$20
-	srl	$7,$23,22
-	nor	$2,$0,$22
-	sll	$3,$23,10
-	or	$23,$3,$7
-	xor	$6,$6,$25
-	lw	$3,20($sp)
-	or	$2,$2,$17
-	xor	$2,$2,$23
-	addu	$6,$6,$8
-	addu	$6,$6,$24
-	addu	$2,$2,$3
-	addu	$24,$6,$9
-	addu	$2,$2,$fp
-	addu	$fp,$2,$10
-	srl	$3,$24,26
-	sll	$2,$24,6
-	or	$2,$2,$3
-	srl	$6,$fp,24
-	sll	$3,$fp,8
-	addu	$24,$2,$21
-	or	$3,$3,$6
-	srl	$7,$19,22
-	sll	$2,$19,10
-	addu	$fp,$3,$18
-	or	$19,$2,$7
-	nor	$6,$0,$20
-	srl	$7,$22,22
-	sll	$3,$22,10
-	or	$22,$3,$7
-	or	$6,$6,$24
-	lw	$7,16($5)
-	nor	$2,$0,$17
-	xor	$6,$6,$19
-	or	$2,$2,$fp
-	xor	$2,$2,$22
-	addu	$6,$6,$7
-	addu	$6,$6,$21
-	addu	$2,$2,$8
-	addu	$21,$6,$9
-	addu	$2,$2,$18
-	addu	$18,$2,$10
-	srl	$3,$21,25
-	sll	$2,$21,7
-	or	$2,$2,$3
-	srl	$6,$18,26
-	sll	$3,$18,6
-	addu	$21,$2,$25
-	or	$3,$3,$6
-	srl	$7,$20,22
-	sll	$2,$20,10
-	addu	$18,$3,$23
-	or	$20,$2,$7
-	nor	$6,$0,$24
-	srl	$7,$17,22
-	sll	$3,$17,10
-	or	$17,$3,$7
-	or	$6,$6,$21
-	lw	$3,36($5)
-	nor	$2,$0,$fp
-	xor	$6,$6,$20
-	or	$2,$2,$18
-	xor	$2,$2,$17
-	addu	$6,$6,$3
-	addu	$6,$6,$25
-	addu	$2,$2,$12
-	addu	$25,$6,$9
-	addu	$2,$2,$23
-	addu	$23,$2,$10
-	srl	$3,$25,18
-	sll	$2,$25,14
-	or	$2,$2,$3
-	srl	$6,$23,26
-	sll	$3,$23,6
-	addu	$25,$2,$19
-	or	$3,$3,$6
-	srl	$7,$24,22
-	sll	$2,$24,10
-	addu	$23,$3,$22
-	or	$24,$2,$7
-	nor	$6,$0,$21
-	srl	$7,$fp,22
-	sll	$3,$fp,10
-	or	$fp,$3,$7
-	or	$6,$6,$25
-	lw	$7,60($5)
-	nor	$2,$0,$18
-	lw	$8,16($sp)
-	xor	$6,$6,$24
-	or	$2,$2,$23
-	xor	$2,$2,$fp
-	addu	$6,$6,$7
-	addu	$6,$6,$19
-	addu	$2,$2,$8
-	addu	$19,$6,$9
-	addu	$2,$2,$22
-	addu	$22,$2,$10
-	srl	$3,$19,23
-	sll	$2,$19,9
-	or	$2,$2,$3
-	srl	$6,$22,18
-	sll	$3,$22,14
-	addu	$19,$2,$20
-	or	$3,$3,$6
-	srl	$7,$21,22
-	nor	$6,$0,$25
-	sll	$2,$21,10
-	addu	$22,$3,$17
-	or	$21,$2,$7
-	or	$6,$6,$19
-	srl	$7,$18,22
-	nor	$2,$0,$23
-	sll	$3,$18,10
-	or	$18,$3,$7
-	xor	$6,$6,$21
-	lw	$7,44($sp)
-	or	$2,$2,$22
-	xor	$2,$2,$18
-	addu	$6,$6,$13
-	addu	$6,$6,$20
-	addu	$2,$2,$7
-	addu	$20,$6,$9
-	addu	$2,$2,$17
-	addu	$17,$2,$10
-	srl	$3,$20,19
-	sll	$2,$20,13
-	or	$2,$2,$3
-	srl	$6,$17,20
-	sll	$3,$17,12
-	addu	$20,$2,$24
-	or	$3,$3,$6
-	srl	$7,$25,22
-	nor	$6,$0,$19
-	sll	$2,$25,10
-	addu	$17,$3,$fp
-	or	$25,$2,$7
-	lw	$8,4($5)
-	or	$6,$6,$20
-	srl	$7,$23,22
-	nor	$2,$0,$22
-	sll	$3,$23,10
-	or	$23,$3,$7
-	xor	$6,$6,$25
-	or	$2,$2,$17
-	xor	$2,$2,$23
-	addu	$6,$6,$8
-	addu	$6,$6,$24
-	addu	$2,$2,$13
-	addu	$24,$6,$9
-	addu	$2,$2,$fp
-	addu	$fp,$2,$10
-	srl	$3,$24,17
-	sll	$2,$24,15
-	or	$2,$2,$3
-	srl	$6,$fp,19
-	sll	$3,$fp,13
-	addu	$24,$2,$21
-	or	$3,$3,$6
-	srl	$7,$19,22
-	sll	$2,$19,10
-	addu	$fp,$3,$18
-	or	$19,$2,$7
-	nor	$6,$0,$20
-	srl	$7,$22,22
-	sll	$3,$22,10
-	or	$22,$3,$7
-	or	$6,$6,$24
-	lw	$3,0($sp)
-	nor	$2,$0,$17
-	lw	$7,24($sp)
-	xor	$6,$6,$19
-	or	$2,$2,$fp
-	xor	$2,$2,$22
-	addu	$6,$6,$3
-	addu	$6,$6,$21
-	addu	$2,$2,$7
-	addu	$21,$6,$9
-	addu	$2,$2,$18
-	addu	$18,$2,$10
-	srl	$3,$21,18
-	sll	$2,$21,14
-	or	$2,$2,$3
-	srl	$6,$18,27
-	sll	$3,$18,5
-	addu	$21,$2,$25
-	or	$3,$3,$6
-	srl	$7,$20,22
-	nor	$6,$0,$24
-	sll	$2,$20,10
-	addu	$18,$3,$23
-	or	$20,$2,$7
-	lw	$8,28($5)
-	or	$6,$6,$21
-	srl	$7,$17,22
-	nor	$2,$0,$fp
-	sll	$3,$17,10
-	or	$17,$3,$7
-	xor	$6,$6,$20
-	lw	$3,28($sp)
-	or	$2,$2,$18
-	xor	$2,$2,$17
-	addu	$6,$6,$8
-	addu	$6,$6,$25
-	addu	$2,$2,$3
-	addu	$25,$6,$9
-	addu	$2,$2,$23
-	addu	$23,$2,$10
-	srl	$3,$25,24
-	sll	$2,$25,8
-	or	$2,$2,$3
-	srl	$6,$23,18
-	sll	$3,$23,14
-	addu	$25,$2,$19
-	or	$3,$3,$6
-	srl	$7,$24,22
-	sll	$2,$24,10
-	addu	$23,$3,$22
-	or	$24,$2,$7
-	nor	$6,$0,$21
-	srl	$7,$fp,22
-	sll	$3,$fp,10
-	or	$fp,$3,$7
-	or	$6,$6,$25
-	lw	$7,0($5)
-	nor	$2,$0,$18
-	lw	$8,32($sp)
-	xor	$6,$6,$24
-	or	$2,$2,$23
-	xor	$2,$2,$fp
-	addu	$6,$6,$7
-	addu	$6,$6,$19
-	addu	$2,$2,$8
-	addu	$19,$6,$9
-	addu	$2,$2,$22
-	addu	$22,$2,$10
-	srl	$3,$19,19
-	sll	$2,$19,13
-	or	$2,$2,$3
-	srl	$6,$22,19
-	sll	$3,$22,13
-	addu	$19,$2,$20
-	or	$3,$3,$6
-	srl	$7,$21,22
-	nor	$6,$0,$25
-	sll	$2,$21,10
-	addu	$22,$3,$17
-	or	$21,$2,$7
-	or	$6,$6,$19
-	srl	$7,$18,22
-	nor	$2,$0,$23
-	sll	$3,$18,10
-	or	$18,$3,$7
-	xor	$6,$6,$21
-	lw	$7,8($sp)
-	or	$2,$2,$22
-	xor	$2,$2,$18
-	addu	$6,$6,$12
-	addu	$6,$6,$20
-	addu	$2,$2,$7
-	addu	$20,$6,$9
-	addu	$2,$2,$17
-	addu	$17,$2,$10
-	srl	$3,$20,26
-	sll	$2,$20,6
-	or	$2,$2,$3
-	srl	$6,$17,19
-	sll	$3,$17,13
-	addu	$20,$2,$24
-	lw	$8,16($5)
-	or	$3,$3,$6
-	srl	$7,$25,22
-	sll	$2,$25,10
-	addu	$17,$3,$fp
-	or	$25,$2,$7
-	nor	$6,$0,$19
-	srl	$7,$23,22
-	sll	$3,$23,10
-	sw	$8,56($sp)
-	or	$23,$3,$7
-	or	$6,$6,$20
-	lw	$3,52($5)
-	nor	$2,$0,$22
-	xor	$6,$6,$25
-	or	$2,$2,$17
-	xor	$2,$2,$23
-	addu	$6,$6,$3
-	addu	$6,$6,$24
-	addu	$2,$2,$8
-	addu	$24,$6,$9
-	addu	$2,$2,$fp
-	addu	$fp,$2,$10
-	srl	$3,$24,27
-	sll	$2,$24,5
-	or	$2,$2,$3
-	srl	$6,$fp,25
-	sll	$3,$fp,7
-	addu	$24,$2,$21
-	or	$3,$3,$6
-	srl	$7,$19,22
-	sll	$2,$19,10
-	addu	$fp,$3,$18
-	or	$19,$2,$7
-	nor	$6,$0,$20
-	srl	$7,$22,22
-	nor	$2,$0,$17
-	sll	$3,$22,10
-	or	$22,$3,$7
-	lw	$8,52($sp)
-	lw	$7,44($5)
-	or	$6,$6,$24
-	or	$2,$2,$fp
-	xor	$6,$6,$19
-	xor	$2,$2,$22
-	addu	$6,$6,$7
-	addu	$2,$2,$8
-	addu	$6,$6,$21
-	addu	$2,$2,$18
-	addu	$21,$6,$9
-	addu	$18,$2,$10
-	srl	$3,$21,20
-	srl	$7,$18,27
-	sll	$2,$21,12
-	sll	$6,$18,5
-	or	$2,$2,$3
-	or	$6,$6,$7
-	sll	$3,$20,10
-	srl	$7,$20,22
-	addu	$18,$6,$23
-	addu	$21,$2,$25
-	or	$20,$3,$7
-	nor	$2,$0,$24
-	srl	$6,$17,22
-	sll	$3,$17,10
-	or	$17,$3,$6
-	or	$2,$2,$21
-	lw	$3,20($5)
-	xor	$2,$2,$20
-	nor	$6,$0,$18
-	and	$6,$6,$17
-	addu	$2,$2,$3
-	and	$3,$18,$fp
-	or	$3,$3,$6
-	addu	$2,$2,$25
-	addu	$3,$3,$13
-	li	$11,2053963776			# 0x7a6d0000
-	ori	$11,$11,0x76e9
-	addu	$25,$2,$9
-	addu	$3,$3,$23
-	addu	$23,$3,$11
-	srl	$6,$25,25
-	sll	$2,$25,7
-	or	$2,$2,$6
-	srl	$8,$23,17
-	sll	$6,$23,15
-	addu	$25,$2,$19
-	or	$6,$6,$8
-	srl	$7,$24,22
-	sll	$2,$24,10
-	addu	$23,$6,$22
-	or	$24,$2,$7
-	nor	$3,$0,$21
-	srl	$6,$fp,22
-	sll	$2,$fp,10
-	or	$fp,$2,$6
-	or	$3,$3,$25
-	lw	$6,48($5)
-	xor	$3,$3,$24
-	addu	$3,$3,$6
-	nor	$6,$0,$23
-	and	$6,$6,$fp
-	and	$2,$23,$18
-	addu	$3,$3,$19
-	or	$2,$2,$6
-	addu	$19,$3,$9
-	addu	$2,$2,$12
-	srl	$8,$19,27
-	srl	$7,$21,22
-	sll	$6,$19,5
-	sll	$3,$21,10
-	addu	$2,$2,$22
-	or	$21,$3,$7
-	or	$6,$6,$8
-	addu	$22,$2,$11
-	addu	$19,$6,$20
-	srl	$7,$22,27
-	nor	$6,$0,$21
-	sll	$2,$22,5
-	and	$6,$6,$25
-	and	$3,$19,$21
-	or	$2,$2,$7
-	lw	$7,4($5)
-	or	$3,$3,$6
-	addu	$22,$2,$17
-	addu	$3,$3,$7
-	srl	$6,$18,22
-	sll	$2,$18,10
-	li	$10,-1894055936			# 0xffffffff8f1b0000
-	ori	$10,$10,0xbcdc
-	or	$18,$2,$6
-	addu	$3,$3,$20
-	nor	$2,$0,$22
-	addu	$20,$3,$10
-	and	$2,$2,$18
-	and	$3,$22,$23
-	srl	$8,$20,21
-	or	$3,$3,$2
-	srl	$6,$25,22
-	sll	$7,$20,11
-	sll	$2,$25,10
-	or	$25,$2,$6
-	or	$7,$7,$8
-	lw	$8,56($sp)
-	addu	$20,$7,$24
-	nor	$6,$0,$25
-	and	$6,$6,$19
-	and	$2,$20,$25
-	addu	$3,$3,$8
-	addu	$3,$3,$17
-	or	$2,$2,$6
-	lw	$6,36($5)
-	addu	$17,$3,$11
-	srl	$7,$17,24
-	sll	$3,$17,8
-	addu	$2,$2,$6
-	or	$3,$3,$7
-	addu	$2,$2,$24
-	addu	$17,$3,$fp
-	addu	$24,$2,$10
-	srl	$6,$23,22
-	lw	$2,4($5)
-	sll	$3,$23,10
-	or	$23,$3,$6
-	srl	$9,$24,20
-	sll	$3,$24,12
-	sw	$2,60($sp)
-	or	$3,$3,$9
-	nor	$7,$0,$17
-	addu	$24,$3,$21
-	and	$7,$7,$23
-	lw	$3,60($sp)
-	and	$6,$17,$22
-	srl	$8,$19,22
-	sll	$2,$19,10
-	or	$6,$6,$7
-	or	$19,$2,$8
-	addu	$6,$6,$3
-	addu	$6,$6,$fp
-	nor	$3,$0,$19
-	addu	$fp,$6,$11
-	and	$3,$3,$20
-	lw	$6,44($5)
-	and	$2,$24,$19
-	or	$2,$2,$3
-	addu	$2,$2,$6
-	sll	$3,$fp,11
-	srl	$6,$fp,21
-	or	$3,$3,$6
-	addu	$2,$2,$21
-	addu	$fp,$3,$18
-	addu	$21,$2,$10
-	srl	$3,$22,22
-	sll	$2,$22,10
-	or	$22,$2,$3
-	srl	$8,$21,18
-	srl	$6,$20,22
-	sll	$7,$21,14
-	nor	$3,$0,$fp
-	sll	$2,$20,10
-	or	$20,$2,$6
-	or	$7,$7,$8
-	and	$3,$3,$22
-	and	$2,$fp,$17
-	addu	$21,$7,$25
-	or	$2,$2,$3
-	nor	$6,$0,$20
-	lw	$7,40($5)
-	and	$6,$6,$24
-	and	$3,$21,$20
-	addu	$2,$2,$16
-	or	$3,$3,$6
-	addu	$2,$2,$18
-	addu	$18,$2,$11
-	addu	$3,$3,$7
-	srl	$6,$18,18
-	addu	$3,$3,$25
-	sll	$2,$18,14
-	addu	$25,$3,$10
-	or	$2,$2,$6
-	addu	$18,$2,$23
-	srl	$9,$25,17
-	srl	$7,$24,22
-	srl	$8,$17,22
-	sll	$3,$25,15
-	sll	$2,$24,10
-	sll	$6,$17,10
-	or	$24,$2,$7
-	or	$17,$6,$8
-	or	$3,$3,$9
-	nor	$2,$0,$18
-	addu	$25,$3,$19
-	and	$2,$2,$17
-	and	$3,$18,$fp
-	nor	$6,$0,$24
-	lw	$8,44($sp)
-	and	$6,$6,$21
-	or	$3,$3,$2
-	and	$2,$25,$24
-	or	$2,$2,$6
-	lw	$6,0($5)
-	addu	$3,$3,$8
-	addu	$3,$3,$23
-	addu	$2,$2,$6
-	addu	$23,$3,$11
-	addu	$2,$2,$19
-	addu	$19,$2,$10
-	srl	$3,$23,18
-	sll	$6,$23,14
-	or	$6,$6,$3
-	srl	$8,$19,18
-	srl	$7,$21,22
-	sll	$3,$19,14
-	sll	$2,$21,10
-	addu	$23,$6,$22
-	or	$21,$2,$7
-	or	$3,$3,$8
-	srl	$7,$fp,22
-	sll	$2,$fp,10
-	addu	$19,$3,$20
-	or	$fp,$2,$7
-	nor	$6,$0,$21
-	nor	$7,$0,$23
-	lw	$8,48($sp)
-	and	$6,$6,$25
-	and	$7,$7,$fp
-	and	$2,$19,$21
-	and	$3,$23,$18
-	or	$2,$2,$6
-	or	$3,$3,$7
-	addu	$3,$3,$8
-	addu	$2,$2,$13
-	addu	$2,$2,$20
-	addu	$3,$3,$22
-	addu	$20,$2,$10
-	addu	$22,$3,$11
-	srl	$8,$20,17
-	srl	$9,$22,26
-	srl	$7,$25,22
-	sll	$6,$20,15
-	sll	$3,$22,6
-	sll	$2,$25,10
-	or	$25,$2,$7
-	or	$6,$6,$8
-	or	$3,$3,$9
-	addu	$22,$3,$17
-	addu	$20,$6,$24
-	srl	$3,$18,22
-	nor	$7,$0,$25
-	sll	$2,$18,10
-	or	$18,$2,$3
-	lw	$8,48($5)
-	and	$7,$7,$19
-	and	$3,$20,$25
-	nor	$6,$0,$22
-	and	$6,$6,$18
-	and	$2,$22,$23
-	or	$3,$3,$7
-	lw	$7,0($5)
-	or	$2,$2,$6
-	addu	$3,$3,$8
-	addu	$3,$3,$24
-	addu	$2,$2,$7
-	addu	$24,$3,$10
-	addu	$2,$2,$17
-	addu	$17,$2,$11
-	sw	$7,64($sp)
-	srl	$6,$19,22
-	srl	$7,$24,23
-	sll	$3,$24,9
-	sll	$2,$19,10
-	or	$19,$2,$6
-	or	$3,$3,$7
-	srl	$6,$17,18
-	sll	$2,$17,14
-	addu	$24,$3,$21
-	or	$2,$2,$6
-	nor	$7,$0,$19
-	srl	$6,$23,22
-	sll	$3,$23,10
-	addu	$17,$2,$fp
-	or	$23,$3,$6
-	and	$7,$7,$20
-	lw	$3,16($5)
-	and	$2,$24,$19
-	or	$2,$2,$7
-	nor	$6,$0,$17
-	lw	$15,20($5)
-	and	$6,$6,$23
-	addu	$2,$2,$3
-	and	$3,$17,$22
-	addu	$2,$2,$21
-	or	$3,$3,$6
-	addu	$21,$2,$10
-	addu	$3,$3,$15
-	srl	$8,$21,24
-	addu	$3,$3,$fp
-	srl	$7,$20,22
-	sll	$6,$21,8
-	sll	$2,$20,10
-	or	$20,$2,$7
-	or	$6,$6,$8
-	addu	$fp,$3,$11
-	addu	$21,$6,$25
-	srl	$3,$fp,26
-	nor	$2,$0,$20
-	sll	$6,$fp,6
-	or	$6,$6,$3
-	and	$2,$2,$24
-	and	$3,$21,$20
-	or	$3,$3,$2
-	srl	$7,$22,22
-	sll	$2,$22,10
-	addu	$fp,$6,$18
-	or	$22,$2,$7
-	lw	$6,52($5)
-	lw	$7,48($5)
-	nor	$2,$0,$fp
-	sw	$7,68($sp)
-	and	$2,$2,$22
-	addu	$3,$3,$6
-	and	$6,$fp,$17
-	addu	$3,$3,$25
-	or	$6,$6,$2
-	lw	$2,68($sp)
-	addu	$25,$3,$10
-	srl	$8,$25,23
-	srl	$7,$24,22
-	addu	$6,$6,$2
-	sll	$3,$25,9
-	sll	$2,$24,10
-	or	$24,$2,$7
-	or	$3,$3,$8
-	addu	$6,$6,$18
-	addu	$25,$3,$19
-	addu	$18,$6,$11
-	nor	$7,$0,$24
-	and	$7,$7,$21
-	srl	$6,$18,23
-	and	$2,$25,$24
-	sll	$3,$18,9
-	or	$3,$3,$6
-	or	$2,$2,$7
-	addu	$18,$3,$23
-	addu	$2,$2,$16
-	srl	$6,$17,22
-	sll	$3,$17,10
-	or	$17,$3,$6
-	addu	$2,$2,$19
-	nor	$3,$0,$18
-	addu	$19,$2,$10
-	and	$3,$3,$17
-	and	$6,$18,$fp
-	lw	$14,8($5)
-	srl	$8,$19,18
-	or	$6,$6,$3
-	sll	$7,$19,14
-	srl	$3,$21,22
-	sll	$2,$21,10
-	or	$21,$2,$3
-	or	$7,$7,$8
-	addu	$19,$7,$20
-	nor	$3,$0,$21
-	addu	$6,$6,$14
-	lw	$7,28($5)
-	and	$3,$3,$25
-	and	$2,$19,$21
-	addu	$6,$6,$23
-	addu	$23,$6,$11
-	or	$2,$2,$3
-	srl	$6,$23,20
-	sll	$3,$23,12
-	addu	$2,$2,$7
-	or	$3,$3,$6
-	addu	$2,$2,$20
-	addu	$23,$3,$22
-	addu	$20,$2,$10
-	srl	$6,$fp,22
-	sll	$3,$fp,10
-	or	$fp,$3,$6
-	srl	$9,$20,27
-	nor	$7,$0,$23
-	srl	$8,$25,22
-	sll	$3,$20,5
-	sll	$2,$25,10
-	or	$25,$2,$8
-	and	$7,$7,$fp
-	lw	$8,52($sp)
-	and	$6,$23,$18
-	or	$3,$3,$9
-	addu	$20,$3,$24
-	or	$6,$6,$7
-	nor	$3,$0,$25
-	and	$3,$3,$19
-	and	$2,$20,$25
-	addu	$6,$6,$8
-	addu	$6,$6,$22
-	or	$2,$2,$3
-	lw	$3,60($5)
-	addu	$22,$6,$11
-	srl	$6,$22,23
-	addu	$2,$2,$3
-	sll	$3,$22,9
-	or	$3,$3,$6
-	addu	$2,$2,$24
-	addu	$22,$3,$17
-	addu	$24,$2,$10
-	srl	$3,$18,22
-	sll	$2,$18,10
-	or	$18,$2,$3
-	srl	$8,$24,26
-	srl	$3,$19,22
-	sll	$7,$24,6
-	nor	$6,$0,$22
-	sll	$2,$19,10
-	or	$19,$2,$3
-	or	$7,$7,$8
-	and	$6,$6,$18
-	lw	$8,36($5)
-	and	$3,$22,$23
-	or	$3,$3,$6
-	addu	$3,$3,$8
-	addu	$24,$7,$21
-	nor	$6,$0,$19
-	addu	$3,$3,$17
-	addu	$17,$3,$11
-	and	$6,$6,$20
-	lw	$3,56($5)
-	and	$2,$24,$19
-	or	$2,$2,$6
-	addu	$2,$2,$3
-	srl	$6,$17,20
-	addu	$2,$2,$21
-	sll	$3,$17,12
-	addu	$21,$2,$10
-	sw	$8,72($sp)
-	or	$3,$3,$6
-	srl	$8,$23,22
-	sll	$6,$23,10
-	addu	$17,$3,$fp
-	or	$23,$6,$8
-	srl	$9,$21,24
-	lw	$6,28($5)
-	srl	$7,$20,22
-	sll	$3,$21,8
-	sll	$2,$20,10
-	or	$20,$2,$7
-	or	$3,$3,$9
-	nor	$2,$0,$17
-	sw	$6,76($sp)
-	addu	$21,$3,$25
-	lw	$7,76($sp)
-	and	$2,$2,$23
-	and	$3,$17,$22
-	nor	$6,$0,$20
-	and	$6,$6,$24
-	or	$3,$3,$2
-	and	$2,$21,$20
-	or	$2,$2,$6
-	addu	$3,$3,$7
-	addu	$3,$3,$fp
-	addu	$2,$2,$15
-	addu	$fp,$3,$11
-	addu	$2,$2,$25
-	addu	$25,$2,$10
-	srl	$3,$fp,27
-	sll	$6,$fp,5
-	or	$6,$6,$3
-	srl	$8,$25,26
-	srl	$7,$24,22
-	sll	$3,$25,6
-	sll	$2,$24,10
-	addu	$fp,$6,$18
-	or	$24,$2,$7
-	or	$3,$3,$8
-	srl	$7,$22,22
-	sll	$2,$22,10
-	addu	$25,$3,$19
-	or	$22,$2,$7
-	nor	$6,$0,$24
-	nor	$7,$0,$fp
-	lw	$8,40($5)
-	and	$6,$6,$21
-	and	$7,$7,$22
-	and	$2,$25,$24
-	and	$3,$fp,$17
-	or	$2,$2,$6
-	or	$3,$3,$7
-	addu	$3,$3,$8
-	addu	$2,$2,$12
-	addu	$2,$2,$19
-	addu	$3,$3,$18
-	addu	$19,$2,$10
-	addu	$18,$3,$11
-	sw	$8,80($sp)
-	srl	$9,$18,17
-	srl	$8,$19,27
-	srl	$7,$21,22
-	sll	$6,$19,5
-	sll	$3,$18,15
-	sll	$2,$21,10
-	or	$21,$2,$7
-	or	$6,$6,$8
-	or	$3,$3,$9
-	addu	$18,$3,$23
-	addu	$19,$6,$20
-	srl	$7,$17,22
-	nor	$3,$0,$21
-	sll	$2,$17,10
-	or	$17,$2,$7
-	and	$3,$3,$25
-	and	$2,$19,$21
-	nor	$6,$0,$18
-	lw	$7,56($5)
-	and	$6,$6,$17
-	or	$2,$2,$3
-	and	$3,$18,$fp
-	or	$3,$3,$6
-	addu	$2,$2,$14
-	addu	$2,$2,$20
-	addu	$3,$3,$7
-	addu	$20,$2,$10
-	addu	$3,$3,$23
-	srl	$5,$25,22
-	sll	$2,$25,10
-	or	$25,$2,$5
-	addu	$23,$3,$11
-	srl	$2,$20,20
-	sll	$5,$20,12
-	or	$5,$5,$2
-	srl	$6,$23,24
-	sll	$2,$23,8
-	or	$2,$2,$6
-	addu	$20,$5,$24
-	addu	$23,$2,$22
-	nor	$3,$0,$25
-	srl	$5,$fp,22
-	sll	$2,$fp,10
-	or	$fp,$2,$5
-	or	$3,$3,$19
-	lw	$2,4($sp)
-	lw	$6,68($sp)
-	xor	$5,$23,$18
-	xor	$3,$3,$20
-	addu	$3,$3,$2
-	xor	$5,$5,$fp
-	li	$8,-1454178304			# 0xffffffffa9530000
-	ori	$8,$8,0xfd4e
-	addu	$5,$5,$6
-	addu	$3,$3,$24
-	addu	$24,$3,$8
-	addu	$22,$22,$5
-	srl	$6,$19,22
-	sll	$2,$19,10
-	or	$19,$2,$6
-	sll	$5,$24,9
-	srl	$2,$24,23
-	srl	$6,$22,24
-	sll	$3,$22,8
-	or	$5,$5,$2
-	or	$3,$3,$6
-	addu	$24,$5,$21
-	addu	$22,$3,$17
-	nor	$2,$0,$19
-	srl	$5,$18,22
-	sll	$3,$18,10
-	or	$18,$3,$5
-	or	$2,$2,$20
-	lw	$3,8($sp)
-	xor	$2,$2,$24
-	lw	$5,48($sp)
-	addu	$2,$2,$3
-	xor	$3,$22,$23
-	xor	$3,$3,$18
-	addu	$3,$3,$5
-	addu	$2,$2,$21
-	addu	$21,$2,$8
-	addu	$17,$17,$3
-	srl	$5,$20,22
-	sll	$2,$20,10
-	or	$20,$2,$5
-	srl	$6,$17,27
-	srl	$2,$21,17
-	sll	$5,$21,15
-	sll	$3,$17,5
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$20
-	addu	$21,$5,$25
-	addu	$17,$3,$fp
-	or	$2,$2,$24
-	srl	$5,$23,22
-	sll	$3,$23,10
-	or	$23,$3,$5
-	xor	$2,$2,$21
-	lw	$5,80($sp)
-	xor	$3,$17,$22
-	xor	$3,$3,$23
-	addu	$2,$2,$15
-	addu	$3,$3,$5
-	addu	$2,$2,$25
-	addu	$25,$2,$8
-	addu	$fp,$fp,$3
-	srl	$5,$24,22
-	sll	$2,$24,10
-	or	$24,$2,$5
-	srl	$6,$fp,20
-	srl	$2,$25,27
-	sll	$5,$25,5
-	sll	$3,$fp,12
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$24
-	addu	$25,$5,$19
-	addu	$fp,$3,$18
-	lw	$6,16($sp)
-	or	$2,$2,$21
-	srl	$5,$22,22
-	sll	$3,$22,10
-	or	$22,$3,$5
-	xor	$2,$2,$25
-	lw	$5,56($sp)
-	xor	$3,$fp,$17
-	addu	$2,$2,$6
-	xor	$3,$3,$22
-	addu	$3,$3,$5
-	addu	$2,$2,$19
-	addu	$19,$2,$8
-	addu	$18,$18,$3
-	srl	$5,$21,22
-	sll	$2,$21,10
-	or	$21,$2,$5
-	srl	$6,$18,23
-	srl	$2,$19,21
-	sll	$5,$19,11
-	sll	$3,$18,9
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$21
-	addu	$19,$5,$20
-	addu	$18,$3,$23
-	lw	$6,20($sp)
-	or	$2,$2,$25
-	srl	$5,$17,22
-	sll	$3,$17,10
-	or	$17,$3,$5
-	xor	$2,$2,$19
-	lw	$5,60($sp)
-	xor	$3,$18,$fp
-	addu	$2,$2,$6
-	xor	$3,$3,$17
-	addu	$3,$3,$5
-	addu	$2,$2,$20
-	addu	$20,$2,$8
-	addu	$23,$23,$3
-	srl	$5,$25,22
-	sll	$2,$25,10
-	or	$25,$2,$5
-	srl	$6,$23,20
-	srl	$2,$20,26
-	sll	$5,$20,6
-	sll	$3,$23,12
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$25
-	addu	$20,$5,$24
-	addu	$23,$3,$22
-	lw	$6,24($sp)
-	or	$2,$2,$19
-	srl	$5,$fp,22
-	sll	$3,$fp,10
-	or	$fp,$3,$5
-	xor	$2,$2,$20
-	xor	$3,$23,$18
-	addu	$2,$2,$6
-	xor	$3,$3,$fp
-	addu	$2,$2,$24
-	addu	$3,$3,$15
-	addu	$24,$2,$8
-	addu	$22,$22,$3
-	srl	$5,$19,22
-	sll	$2,$19,10
-	or	$19,$2,$5
-	srl	$6,$22,27
-	srl	$2,$24,24
-	sll	$5,$24,8
-	sll	$3,$22,5
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$19
-	addu	$24,$5,$21
-	addu	$22,$3,$17
-	or	$2,$2,$20
-	srl	$5,$18,22
-	sll	$3,$18,10
-	or	$18,$3,$5
-	xor	$2,$2,$24
-	xor	$3,$22,$23
-	xor	$3,$3,$18
-	addu	$2,$2,$14
-	addu	$2,$2,$21
-	addu	$3,$3,$13
-	addu	$21,$2,$8
-	addu	$17,$17,$3
-	srl	$5,$20,22
-	sll	$2,$20,10
-	or	$20,$2,$5
-	srl	$6,$17,18
-	srl	$2,$21,19
-	sll	$5,$21,13
-	sll	$3,$17,14
-	or	$5,$5,$2
-	or	$3,$3,$6
-	addu	$21,$5,$25
-	addu	$17,$3,$fp
-	nor	$2,$0,$20
-	srl	$5,$23,22
-	sll	$3,$23,10
-	or	$23,$3,$5
-	or	$2,$2,$24
-	lw	$5,32($sp)
-	lw	$6,76($sp)
-	xor	$3,$17,$22
-	xor	$2,$2,$21
-	addu	$2,$2,$5
-	xor	$3,$3,$23
-	addu	$3,$3,$6
-	addu	$2,$2,$25
-	addu	$25,$2,$8
-	addu	$fp,$fp,$3
-	srl	$5,$24,22
-	sll	$2,$24,10
-	or	$24,$2,$5
-	srl	$6,$fp,26
-	srl	$2,$25,20
-	sll	$5,$25,12
-	sll	$3,$fp,6
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$24
-	addu	$25,$5,$19
-	addu	$fp,$3,$18
-	or	$2,$2,$21
-	srl	$5,$22,22
-	sll	$3,$22,10
-	or	$22,$3,$5
-	xor	$2,$2,$25
-	xor	$3,$fp,$17
-	addu	$2,$2,$7
-	xor	$3,$3,$22
-	addu	$2,$2,$19
-	addu	$3,$3,$12
-	addu	$19,$2,$8
-	addu	$18,$18,$3
-	srl	$5,$21,22
-	sll	$2,$21,10
-	or	$21,$2,$5
-	srl	$6,$18,24
-	srl	$2,$19,27
-	sll	$5,$19,5
-	sll	$3,$18,8
-	or	$5,$5,$2
-	or	$3,$3,$6
-	addu	$19,$5,$20
-	addu	$18,$3,$23
-	nor	$2,$0,$21
-	srl	$5,$17,22
-	sll	$3,$17,10
-	or	$17,$3,$5
-	or	$2,$2,$25
-	lw	$5,40($sp)
-	xor	$3,$18,$fp
-	xor	$2,$2,$19
-	addu	$2,$2,$5
-	xor	$3,$3,$17
-	addu	$2,$2,$20
-	addu	$3,$3,$14
-	addu	$20,$2,$8
-	addu	$23,$23,$3
-	srl	$5,$25,22
-	sll	$2,$25,10
-	or	$25,$2,$5
-	srl	$6,$23,19
-	srl	$2,$20,20
-	sll	$5,$20,12
-	sll	$3,$23,13
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$25
-	addu	$20,$5,$24
-	addu	$23,$3,$22
-	or	$2,$2,$19
-	srl	$5,$fp,22
-	sll	$3,$fp,10
-	or	$fp,$3,$5
-	lw	$6,52($sp)
-	xor	$3,$23,$18
-	xor	$2,$2,$20
-	addu	$2,$2,$16
-	xor	$3,$3,$fp
-	addu	$3,$3,$6
-	addu	$2,$2,$24
-	addu	$24,$2,$8
-	addu	$22,$22,$3
-	srl	$5,$19,22
-	sll	$2,$19,10
-	or	$19,$2,$5
-	srl	$6,$22,26
-	srl	$2,$24,19
-	sll	$5,$24,13
-	sll	$3,$22,6
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$19
-	addu	$24,$5,$21
-	addu	$22,$3,$17
-	or	$2,$2,$20
-	srl	$5,$18,22
-	sll	$3,$18,10
-	or	$18,$3,$5
-	xor	$2,$2,$24
-	xor	$3,$22,$23
-	xor	$3,$3,$18
-	addu	$2,$2,$13
-	addu	$3,$3,$7
-	addu	$2,$2,$21
-	addu	$21,$2,$8
-	addu	$17,$17,$3
-	srl	$5,$20,22
-	sll	$2,$20,10
-	or	$20,$2,$5
-	srl	$6,$17,27
-	srl	$2,$21,18
-	sll	$5,$21,14
-	sll	$3,$17,5
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$20
-	addu	$21,$5,$25
-	addu	$17,$3,$fp
-	lw	$7,44($sp)
-	or	$2,$2,$24
-	srl	$5,$23,22
-	sll	$3,$23,10
-	or	$23,$3,$5
-	xor	$2,$2,$21
-	lw	$5,64($sp)
-	xor	$3,$17,$22
-	addu	$2,$2,$7
-	xor	$3,$3,$23
-	addu	$3,$3,$5
-	addu	$2,$2,$25
-	addu	$25,$2,$8
-	addu	$fp,$fp,$3
-	srl	$5,$24,22
-	sll	$2,$24,10
-	or	$24,$2,$5
-	srl	$6,$fp,17
-	srl	$2,$25,21
-	sll	$5,$25,11
-	sll	$3,$fp,15
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$24
-	addu	$25,$5,$19
-	addu	$fp,$3,$18
-	or	$2,$2,$21
-	srl	$5,$22,22
-	sll	$3,$22,10
-	or	$22,$3,$5
-	xor	$2,$2,$25
-	xor	$3,$fp,$17
-	xor	$3,$3,$22
-	addu	$2,$2,$12
-	addu	$3,$3,$16
-	addu	$2,$2,$19
-	addu	$19,$2,$8
-	addu	$18,$18,$3
-	srl	$5,$21,22
-	sll	$2,$21,10
-	or	$21,$2,$5
-	srl	$6,$18,19
-	srl	$2,$19,24
-	sll	$5,$19,8
-	sll	$3,$18,13
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$21
-	addu	$19,$5,$20
-	addu	$18,$3,$23
-	lw	$6,48($sp)
-	or	$2,$2,$25
-	srl	$5,$17,22
-	sll	$3,$17,10
-	or	$17,$3,$5
-	lw	$7,72($sp)
-	xor	$3,$18,$fp
-	xor	$2,$2,$19
-	addu	$2,$2,$6
-	xor	$3,$3,$17
-	addu	$3,$3,$7
-	addu	$2,$2,$20
-	addu	$20,$2,$8
-	addu	$23,$23,$3
-	srl	$5,$25,22
-	sll	$2,$25,10
-	or	$25,$2,$5
-	srl	$3,$20,27
-	srl	$6,$23,21
-	sll	$5,$20,5
-	sll	$2,$23,11
-	or	$5,$5,$3
-	or	$2,$2,$6
-	addu	$20,$5,$24
-	addu	$23,$2,$22
-	srl	$5,$fp,22
-	sll	$2,$fp,10
-	nor	$3,$0,$25
-	or	$fp,$2,$5
-	or	$3,$3,$19
-	lw	$2,52($sp)
-	xor	$3,$3,$20
-	addu	$3,$3,$2
-	addu	$3,$3,$24
-	addu	$24,$3,$8
-	xor	$2,$23,$18
-	lw	$3,44($sp)
-	lw	$6,8($4)
-	srl	$7,$19,22
-	sll	$5,$19,10
-	or	$19,$5,$7
-	xor	$2,$2,$fp
-	addu	$2,$2,$3
-	addu	$6,$6,$19
-	addu	$22,$22,$2
-	addu	$6,$6,$fp
-	srl	$2,$24,26
-	sll	$5,$24,6
-	srl	$3,$22,21
-	lw	$10,4($4)
-	lw	$7,12($4)
-	lw	$8,0($4)
-	or	$5,$5,$2
-	sll	$9,$22,11
-	sw	$6,4($4)
-	lw	$6,16($4)
-	or	$9,$9,$3
-	addu	$24,$5,$21
-	srl	$3,$18,22
-	sll	$2,$18,10
-	addu	$22,$9,$17
-	addu	$10,$10,$20
-	addu	$6,$6,$21
-	or	$18,$2,$3
-	addu	$7,$7,$25
-	addu	$8,$8,$24
-	addu	$18,$18,$10
-	addu	$7,$7,$17
-	addu	$6,$6,$22
-	addu	$8,$8,$23
-	sw	$18,0($4)
-	sw	$7,8($4)
-	sw	$6,12($4)
-	sw	$8,16($4)
-	lw	$fp,120($sp)
-	lw	$23,116($sp)
-	lw	$22,112($sp)
-	lw	$21,108($sp)
-	lw	$20,104($sp)
-	lw	$19,100($sp)
-	lw	$18,96($sp)
-	lw	$17,92($sp)
-	lw	$16,88($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,128
-	.set	macro
-	.set	reorder
-
-	.end	compress
-	.align	2
-	.globl	MDfinish
-	.ent	MDfinish
-MDfinish:
-	.frame	$sp,104,$31		# vars= 64, regs= 6/0, args= 16, gp= 0
-	.mask	0x801f0000,-4
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-104
-	sw	$17,84($sp)
-	addiu	$17,$sp,16
-	sw	$20,96($sp)
-	sw	$18,88($sp)
-	sw	$16,80($sp)
-	move	$18,$6
-	move	$20,$4
-	li	$6,64			# 0x40
-	move	$16,$5
-	move	$4,$17
-	move	$5,$0
-	sw	$19,92($sp)
-	sw	$31,100($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	memset
-	move	$19,$7
-	.set	macro
-	.set	reorder
-
-	andi	$7,$18,0x3f
-	.set	noreorder
-	.set	nomacro
-	beq	$7,$0,$L10
-	move	$6,$0
-	.set	macro
-	.set	reorder
-
-$L7:
-	srl	$5,$6,2
-	sll	$5,$5,2
-	lbu	$4,0($16)
-	addu	$5,$5,$17
-	andi	$2,$6,0x3
-	sll	$2,$2,3
-	lw	$3,0($5)
-	sll	$4,$4,$2
-	addiu	$6,$6,1
-	xor	$3,$3,$4
-	sltu	$2,$6,$7
-	sw	$3,0($5)
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L7
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-$L10:
-	andi	$5,$18,0x3c
-	andi	$3,$18,0x3
-	addu	$5,$5,$17
-	sll	$3,$3,3
-	addiu	$3,$3,7
-	lw	$4,0($5)
-	li	$2,1			# 0x1
-	sll	$2,$2,$3
-	xor	$4,$4,$2
-	sltu	$3,$7,56
-	.set	noreorder
-	.set	nomacro
-	beq	$3,$0,$L12
-	sw	$4,0($5)
-	.set	macro
-	.set	reorder
-
-	sll	$3,$19,3
-	srl	$2,$18,29
-	or	$2,$2,$3
-	move	$4,$20
-	sll	$3,$18,3
-	move	$5,$17
-	sw	$3,72($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	compress
-	sw	$2,76($sp)
-	.set	macro
-	.set	reorder
-
-	lw	$31,100($sp)
-	lw	$20,96($sp)
-	lw	$19,92($sp)
-	lw	$18,88($sp)
-	lw	$17,84($sp)
-	lw	$16,80($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,104
-	.set	macro
-	.set	reorder
-
-$L12:
-	move	$4,$20
-	.set	noreorder
-	.set	nomacro
-	jal	compress
-	move	$5,$17
-	.set	macro
-	.set	reorder
-
-	move	$4,$17
-	move	$5,$0
-	.set	noreorder
-	.set	nomacro
-	jal	memset
-	li	$6,64			# 0x40
-	.set	macro
-	.set	reorder
-
-	sll	$3,$19,3
-	srl	$2,$18,29
-	or	$2,$2,$3
-	move	$4,$20
-	sll	$3,$18,3
-	move	$5,$17
-	sw	$3,72($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	compress
-	sw	$2,76($sp)
-	.set	macro
-	.set	reorder
-
-	lw	$31,100($sp)
-	lw	$20,96($sp)
-	lw	$19,92($sp)
-	lw	$18,88($sp)
-	lw	$17,84($sp)
-	lw	$16,80($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,104
-	.set	macro
-	.set	reorder
-
-	.end	MDfinish
diff --git a/lib/CPUs/MIPS/sim/asm/rmd160_test.s b/lib/CPUs/MIPS/sim/asm/rmd160_test.s
deleted file mode 100644
index ec7382d..0000000
--- a/lib/CPUs/MIPS/sim/asm/rmd160_test.s
+++ /dev/null
@@ -1,556 +0,0 @@
-	.file	1 "rmd160_test.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	saus
-	.ent	saus
-saus:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	sll	$4,$4,24
-	sra	$4,$4,24
-	ori	$5,$2,0x4
-	ori	$3,$2,0x8
-$L2:
-	lbu	$2,0($3)
-	andi	$2,$2,0x2
-	bne	$2,$0,$L2
-	sb	$4,0($5)
-	j	$31
-	.end	saus
-	.align	2
-	.globl	sputs
-	.ent	sputs
-sputs:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	lb	$4,0($4)
-	.set	noreorder
-	.set	nomacro
-	j	$L11
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-$L12:
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-	lb	$4,0($16)
-$L11:
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L12
-	subu	$2,$16,$17
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	sputs
-	.align	2
-	.globl	print_byte
-	.ent	print_byte
-print_byte:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$16,16($sp)
-	sll	$16,$4,24
-	sw	$17,20($sp)
-	sw	$31,24($sp)
-	sra	$16,$16,24
-	li	$17,1			# 0x1
-	sra	$2,$16,4
-$L22:
-	andi	$5,$2,0xf
-	sll	$2,$16,4
-	sll	$16,$2,24
-	sltu	$3,$5,10
-	addiu	$17,$17,-1
-	sra	$16,$16,24
-	.set	noreorder
-	.set	nomacro
-	bne	$3,$0,$L18
-	addiu	$4,$5,48
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$5,55
-$L18:
-	jal	saus
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L22
-	sra	$2,$16,4
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_byte
-	.align	2
-	.globl	print_word
-	.ent	print_word
-print_word:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	li	$17,3			# 0x3
-$L27:
-	sra	$4,$16,24
-	.set	noreorder
-	.set	nomacro
-	jal	print_byte
-	addiu	$17,$17,-1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L27
-	sll	$16,$16,8
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_word
-
-	.lcomm	hashcode.0,20
-	.align	2
-	.globl	RMD
-	.ent	RMD
-RMD:
-	.frame	$sp,128,$31		# vars= 88, regs= 6/0, args= 16, gp= 0
-	.mask	0x801f0000,-4
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-128
-	sw	$16,104($sp)
-	move	$16,$4
-	addiu	$4,$sp,16
-	sw	$31,124($sp)
-	sw	$20,120($sp)
-	sw	$18,112($sp)
-	sw	$17,108($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	MDinit
-	sw	$19,116($sp)
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	strlen
-	move	$4,$16
-	.set	macro
-	.set	reorder
-
-	move	$18,$2
-	sltu	$2,$2,64
-	move	$17,$18
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L44
-	addiu	$20,$sp,16
-	.set	macro
-	.set	reorder
-
-	addiu	$19,$sp,40
-	addiu	$5,$20,24
-$L50:
-	li	$11,15			# 0xf
-$L37:
-	lbu	$2,3($16)
-	lbu	$3,2($16)
-	lbu	$4,1($16)
-	sll	$3,$3,16
-	sll	$2,$2,24
-	or	$2,$2,$3
-	sll	$4,$4,8
-	lbu	$3,0($16)
-	or	$2,$2,$4
-	or	$2,$2,$3
-	addiu	$11,$11,-1
-	sw	$2,0($5)
-	addiu	$16,$16,4
-	.set	noreorder
-	.set	nomacro
-	bgez	$11,$L37
-	addiu	$5,$5,4
-	.set	macro
-	.set	reorder
-
-	addiu	$17,$17,-64
-	addiu	$4,$sp,16
-	.set	noreorder
-	.set	nomacro
-	jal	compress
-	move	$5,$19
-	.set	macro
-	.set	reorder
-
-	sltu	$2,$17,64
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L50
-	addiu	$5,$20,24
-	.set	macro
-	.set	reorder
-
-$L44:
-	move	$5,$16
-	move	$6,$18
-	addiu	$4,$sp,16
-	.set	noreorder
-	.set	nomacro
-	jal	MDfinish
-	move	$7,$0
-	.set	macro
-	.set	reorder
-
-	move	$11,$0
-	la	$15,hashcode.0
-	la	$13,hashcode.0+1
-	la	$14,hashcode.0+2
-	la	$12,hashcode.0+3
-$L42:
-	srl	$2,$11,2
-	sll	$2,$2,2
-	addu	$2,$2,$20
-	lw	$3,0($2)
-	addu	$7,$11,$15
-	addu	$8,$11,$13
-	addu	$9,$11,$14
-	addu	$10,$11,$12
-	addiu	$11,$11,4
-	srl	$6,$3,24
-	srl	$2,$3,8
-	srl	$4,$3,16
-	sltu	$5,$11,20
-	sb	$3,0($7)
-	sb	$2,0($8)
-	sb	$4,0($9)
-	.set	noreorder
-	.set	nomacro
-	bne	$5,$0,$L42
-	sb	$6,0($10)
-	.set	macro
-	.set	reorder
-
-	lw	$31,124($sp)
-	lw	$20,120($sp)
-	lw	$19,116($sp)
-	lw	$18,112($sp)
-	lw	$17,108($sp)
-	lw	$16,104($sp)
-	la	$2,hashcode.0
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,128
-	.set	macro
-	.set	reorder
-
-	.end	RMD
-	.section	.rodata.str1.4,"aMS",@progbits,1
-	.align	2
-$LC0:
-	.ascii	"\r\n\000"
-	.align	2
-$LC1:
-	.ascii	"* message: \000"
-	.align	2
-$LC2:
-	.ascii	"  hashcode: \000"
-	.text
-	.align	2
-	.globl	RMDstring
-	.ent	RMDstring
-RMDstring:
-	.frame	$sp,40,$31		# vars= 8, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	lbu	$3,$LC0+2
-	lhu	$2,$LC0
-	addiu	$sp,$sp,-40
-	sw	$31,32($sp)
-	sb	$3,18($sp)
-	sw	$17,28($sp)
-	sw	$16,24($sp)
-	sh	$2,16($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	RMD
-	move	$16,$5
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$sp,16
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$17,$2
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC1
-	jal	sputs
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$4,$16
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	addiu	$4,$sp,16
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC2
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$16,$0
-	.set	macro
-	.set	reorder
-
-	addu	$2,$17,$16
-$L58:
-	lb	$4,0($2)
-	.set	noreorder
-	.set	nomacro
-	jal	print_byte
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-	sltu	$2,$16,20
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L58
-	addu	$2,$17,$16
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	addiu	$4,$sp,16
-	.set	macro
-	.set	reorder
-
-	lw	$31,32($sp)
-	lw	$17,28($sp)
-	lw	$16,24($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,40
-	.set	macro
-	.set	reorder
-
-	.end	RMDstring
-	.rdata
-	.align	2
-$LC3:
-	.byte	-1
-	.byte	35
-	.byte	-100
-	.byte	-42
-	.byte	89
-	.byte	-118
-	.byte	121
-	.byte	46
-	.byte	-89
-	.byte	-85
-	.byte	108
-	.byte	-8
-	.byte	117
-	.byte	-74
-	.byte	53
-	.byte	94
-	.byte	93
-	.byte	-128
-	.byte	106
-	.byte	54
-	.section	.rodata.str1.4
-	.align	2
-$LC4:
-	.ascii	"MIPS R3000 CPU\000"
-	.align	2
-$LC5:
-	.ascii	"Failed\r\n\000"
-	.text
-	.align	2
-	.globl	main
-	.ent	main
-main:
-	.frame	$sp,88,$31		# vars= 48, regs= 5/0, args= 16, gp= 0
-	.mask	0x800f0000,-8
-	.fmask	0x00000000,0
-	lwl	$2,$LC3+3
-	lwl	$3,$LC3+7
-	lwr	$2,$LC3
-	lwr	$3,$LC3+4
-	lwl	$4,$LC3+11
-	lwl	$5,$LC3+15
-	lwl	$6,$LC3+19
-	addiu	$sp,$sp,-88
-	lwr	$4,$LC3+8
-	lwr	$5,$LC3+12
-	lwr	$6,$LC3+16
-	sw	$2,16($sp)
-	sw	$3,20($sp)
-	lw	$2,$LC4
-	lw	$3,$LC4+4
-	sw	$19,76($sp)
-	sw	$18,72($sp)
-	sw	$17,68($sp)
-	sw	$4,24($sp)
-	sw	$5,28($sp)
-	sw	$2,40($sp)
-	sw	$31,80($sp)
-	sw	$16,64($sp)
-	sw	$6,32($sp)
-	sw	$3,44($sp)
-	lw	$2,$LC4+8
-	lhu	$3,$LC4+12
-	sw	$2,48($sp)
-	lbu	$2,$LC4+14
-	sh	$3,52($sp)
-	sb	$2,54($sp)
-	lbu	$3,$LC0+2
-	lhu	$2,$LC0
-	li	$4,-2147483648			# 0xffffffff80000000
-	sh	$2,56($sp)
-	sb	$3,58($sp)
-	ori	$5,$4,0x9
-	li	$2,53
-	ori	$4,$4,0x8
-	li	$3,85
-	sb	$2,0($5)
-	move	$18,$0
-	sb	$3,0($4)
-	addiu	$19,$sp,56
-	addiu	$17,$sp,40
-$L60:
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$18
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$4,$19
-	.set	macro
-	.set	reorder
-
-	addiu	$18,$18,1
-	.set	noreorder
-	.set	nomacro
-	j	$L66
-	li	$16,32249			# 0x7df9
-	.set	macro
-	.set	reorder
-
-$L64:
-	.set	noreorder
-	.set	nomacro
-	bltz	$16,$L70
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-$L66:
-	.set	noreorder
-	.set	nomacro
-	jal	RMD
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-	move	$4,$2
-	addiu	$5,$sp,16
-	.set	noreorder
-	.set	nomacro
-	jal	memcmp
-	li	$6,20			# 0x14
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC5
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L64
-	addiu	$16,$16,-1
-	.set	macro
-	.set	reorder
-
-	jal	sputs
-	.set	noreorder
-	.set	nomacro
-	bgez	$16,$L66
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-$L70:
-	.set	noreorder
-	.set	nomacro
-	jal	RMDstring
-	move	$5,$17
-	.set	macro
-	.set	reorder
-
-	j	$L60
-	.end	main
diff --git a/lib/CPUs/MIPS/sim/asm/spim_load_store.s b/lib/CPUs/MIPS/sim/asm/spim_load_store.s
deleted file mode 100644
index 864d660..0000000
--- a/lib/CPUs/MIPS/sim/asm/spim_load_store.s
+++ /dev/null
@@ -1,50 +0,0 @@
-main:
-		li, $8, 0x81234678
-
-# SB
-		li, $15, 0x10000000
-		sw	$8, 0($15)
-		
-		
-		mfc0 $9, $12
-		li	$10, 0x02000000
-		or	$9, $9, $10
-		mtc0 $9, $12
-		lwl	$16, 0($15)
-		lwl	$17, 1($15)
-		lwl	$18, 2($15)
-		lwl	$19, 3($15)
-		nop
-		lwr	$24, 0($15)
-		lwr	$25, 1($15)
-		lwr	$26, 2($15)
-		lwr	$27, 3($15)
-		nop
-		lbu	$16, 0($15)
-		lbu	$17, 1($15)
-		lbu	$18, 2($15)
-		lbu	$19, 3($15)
-		nop
-		lb	$24, 0($15)
-		lb	$25, 1($15)
-		lb	$26, 2($15)
-		lb	$27, 3($15)
-		nop
-		swl	$8, 4($15)
-		swl	$8, 9($15)
-		swl	$8, 14($15)
-		swl	$8, 19($15)
-		nop
-		swr	$8, 20($15)
-		swr	$8, 25($15)
-		swr	$8, 30($15)
-		swr	$8, 35($15)
-		nop
-		sb	$8, 0($15)
-		sb	$8, 1($15)
-		sb	$8, 2($15)
-		sb	$8, 3($15)
-		nop
-		nop
-		nop
-		
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/startup.s b/lib/CPUs/MIPS/sim/asm/startup.s
deleted file mode 100644
index a53059e..0000000
--- a/lib/CPUs/MIPS/sim/asm/startup.s
+++ /dev/null
@@ -1,27 +0,0 @@
-		.file	"startup.s"
-	
-		.section .stext,"ax"
-		.extern _init
-		.align	2
-	
-_start:
-		.set	noreorder
-
-		# Set Kernel mode
-		li		$26, 0x1040040C
-		mtc0	$26, $12
-		li		$26, 0x00000000
-		mtc0	$26, $13
-
-		mfc0	$26, $15
-		nop
-		mtc0	$26, $31
-
-		# jump init
-		la $26, _init
-		jr $26
-
-		# set user mode
-		rfe
-	
-		.set	reorder
diff --git a/lib/CPUs/MIPS/sim/asm/test1.s b/lib/CPUs/MIPS/sim/asm/test1.s
deleted file mode 100644
index 73f2ec3..0000000
--- a/lib/CPUs/MIPS/sim/asm/test1.s
+++ /dev/null
@@ -1,39 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		lui $1, 0x1234
-			ori $1, $1, 0x5678
-			andi $1, $1, 0xF00F
-			addi $1, -0x5004
-loop:		addi $1, -1		
-			bgtz $1, loop
-			lui $2, 0
-			ori $2, 1
-			lui $1, 0
-			ori $1, 4
-loop2:		sub	 $1, $1, $2
-			bgtz $1, loop2
-			lui  $31, 0x0040
-			jr   $31
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test2.s b/lib/CPUs/MIPS/sim/asm/test2.s
deleted file mode 100644
index 30353ab..0000000
--- a/lib/CPUs/MIPS/sim/asm/test2.s
+++ /dev/null
@@ -1,40 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		lui $1, 0x1234
-			ori $1, $1, 0x5678
-			lui $3, 0x5555
-			ori $3, $3, 0xAAAA
-			lui $2, 0x1000
-			sw	$1, 0($2)
-			sw	$3, 4($2)
-			sw	$2, 0($2)
-			sw	$1, 4($2)
-			lw  $1, 4($2)
-			lw  $4, 0($2)
-			lui $5, 0x0001
-			lui $6, 0x0002
-			lui $7, 0x0003
-			lui $8, 0x0004
-			add $4, $4, $5
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			j   main
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test3.s b/lib/CPUs/MIPS/sim/asm/test3.s
deleted file mode 100644
index f24d9a4..0000000
--- a/lib/CPUs/MIPS/sim/asm/test3.s
+++ /dev/null
@@ -1,40 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		lui $1, 0x1234
-			ori $1, $1, 0x5A5A
-			sll $1, $1, 1
-			sll $1, $1, 4
-			sll $1, $1, 2
-			sll $1, $1, 1
-			sll $1, $1, 8
-			srl $1, $1, 2
-			srl $1, $1, 5
-			srl $1, $1, 1
-			srl $1, $1, 8
-			xori $1, $1, 0xFFFF
-			lui  $31, 0x0040
-			jr   $31
-			xor $1, $1, $31
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test4.s b/lib/CPUs/MIPS/sim/asm/test4.s
deleted file mode 100644
index 830808f..0000000
--- a/lib/CPUs/MIPS/sim/asm/test4.s
+++ /dev/null
@@ -1,34 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		sll $0, $0, 0
-		lui $1, 0x1000
-		addi $2, $1, 0
-		lui $7, 0x1234
-		lui $5, 0x0001
-		sw	$7, 0($1)
-		lw  $3, 0($2)
-		add $8, $3, $5
-		add $9, $3, $5
-		add $10, $3, $5
-		add $11, $3, $5
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		j   main
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test5.s b/lib/CPUs/MIPS/sim/asm/test5.s
deleted file mode 100644
index 89d8a63..0000000
--- a/lib/CPUs/MIPS/sim/asm/test5.s
+++ /dev/null
@@ -1,39 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		lui $1, 0x8000
-			lui $2, 0
-			lui $3, 0
-			ori $2, 1
-			ori $3, 3
-			srl $1, $1, 1
-			sll $1, $1, 1
-			sra $1, $1, 1
-			sra $1, $1, 3
-			sllv $4, $1, $3
-			srav $5, $1, $2
-			srav $6, $1, $3
-			lui  $31, 0x0040
-			jr   $31
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test6.s b/lib/CPUs/MIPS/sim/asm/test6.s
deleted file mode 100644
index 65809dd..0000000
--- a/lib/CPUs/MIPS/sim/asm/test6.s
+++ /dev/null
@@ -1,31 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		lui $8, 0
-loop:		sll $0, $0, 0	
-			jal subr1
-			la $2, subr2
-			jalr $15, $2
-			sll $0, $0, 0
-			j	loop
-			
-subr1:		addi $8, 1
-			sll $0, $0, 0
-			jr   $31
-subr2:		addi $8, 16
-			sll $0, $0, 0
-			jr   $15
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test7.s b/lib/CPUs/MIPS/sim/asm/test7.s
deleted file mode 100644
index 05d9457..0000000
--- a/lib/CPUs/MIPS/sim/asm/test7.s
+++ /dev/null
@@ -1,17 +0,0 @@
-
-main:		li $2, 0x12345678
-			li $3, 0x87654321
-			mult $2, $3
-			multu $2, $3
-			mult $3, $2
-			multu $3, $2
-			
-			mult $2, $2
-			multu $2, $2
-			mult $3, $3
-			multu $3, $3
-			
-			sll $0, $0, 0
-			j main
-			sll $0, $0, 0
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test_addsub.s b/lib/CPUs/MIPS/sim/asm/test_addsub.s
deleted file mode 100644
index 0e0c700..0000000
--- a/lib/CPUs/MIPS/sim/asm/test_addsub.s
+++ /dev/null
@@ -1,76 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		li $2, 0x12345678
-			li $4, 0x12345678
-			li $6, 0x12345678
-			li $8, 0x12345678
-			li $3, 0x77654321
-			li $5, 0x77654321
-			li $7, 0x77654321
-			li $9, 0x77654321
-			addu $15, $2, $3
-			addu $15, $3, $2
-			addu $15, $2, $2
-			addu $15, $3, $3
-
-			sll $0, $0, 0
-
-			subu $15, $2, $3
-			subu $15, $3, $2
-			subu $15, $2, $2
-			subu $15, $3, $3
-
-			sll $0, $0, 0
-
-			addiu $4, 0x1234
-			addiu $8, -0x1234
-			addiu $5, 0x1234
-			addiu $9, -0x1234
-
-			sll $0, $0, 0
-
-			add $15, $2, $3
-			add $15, $3, $2
-			add $15, $2, $2
-			add $15, $3, $3
-
-			sll $0, $0, 0
-
-			sub $15, $2, $3
-			sub $15, $3, $2
-			sub $15, $2, $2
-			sub $15, $3, $3
-
-			sll $0, $0, 0
-
-			addi $2, 0x1234
-			addi $6, -0x1234
-			addi $3, 0x1234
-			addi $7, -0x1234
-
-			sll $0, $0, 0
-
-			j   main
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test_muldiv.s b/lib/CPUs/MIPS/sim/asm/test_muldiv.s
deleted file mode 100644
index 9c85e8a..0000000
--- a/lib/CPUs/MIPS/sim/asm/test_muldiv.s
+++ /dev/null
@@ -1,17 +0,0 @@
-main:
-		li $8, 0x12345678
-		li $9, 0x87654321
-		mthi $8
-		mfhi $10
-		addu $16, $10, $9
-
-		mtlo $9
-		mflo $11
-		multu $8, $9
-#		addu $17, $11, $8
-
-		nop
-		nop
-		nop
-		nop
-		
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test_slt.s b/lib/CPUs/MIPS/sim/asm/test_slt.s
deleted file mode 100644
index 0f55466..0000000
--- a/lib/CPUs/MIPS/sim/asm/test_slt.s
+++ /dev/null
@@ -1,57 +0,0 @@
-#		.ktext 0x80000180
-		.text 0x00410000
-		.globl	main
-		
-main:		li $2, 0x12345678
-			li $3, 0x23456789
-			li $4, 0x87654321
-			li $5, 0x98765432
-			li $8, 0x10000000
-			sll $0, $0, 0
-
-			sltu $15, $2, $2
-			sltu $15, $2, $3
-			sltu $15, $2, $4
-			sltu $15, $2, $5
-			
-			sltu $15, $3, $2
-			sltu $15, $3, $3
-			sltu $15, $3, $4
-			sltu $15, $3, $5
-
-			sltu $15, $4, $2
-			sltu $15, $4, $3
-			sltu $15, $4, $4
-			sltu $15, $4, $5
-			
-			sltu $15, $5, $2
-			sltu $15, $5, $3
-			sltu $15, $5, $4
-			sltu $15, $5, $5
-
-			sll $0, $0, 0
-
-			slt $15, $2, $2
-			slt $15, $2, $3
-			slt $15, $2, $4
-			slt $15, $2, $5
-			
-			slt $15, $3, $2
-			slt $15, $3, $3
-			slt $15, $3, $4
-			slt $15, $3, $5
-
-			slt $15, $4, $2
-			slt $15, $4, $3
-			slt $15, $4, $4
-			slt $15, $4, $5
-			
-			slt $15, $5, $2
-			slt $15, $5, $3
-			slt $15, $5, $4
-			slt $15, $5, $5
-
-			sll $0, $0, 0
-
-			j   main
-			sll $0, $0, 0
diff --git a/lib/CPUs/MIPS/sim/asm/test_slti.s b/lib/CPUs/MIPS/sim/asm/test_slti.s
deleted file mode 100644
index 7c47f70..0000000
--- a/lib/CPUs/MIPS/sim/asm/test_slti.s
+++ /dev/null
@@ -1,57 +0,0 @@
-#		.ktext 0x80000180
-		.text 0x00410000
-		.globl	main
-		
-main:		li $2, 0x12345678
-			li $3, 0x23456789
-			li $4, 0x87654321
-			li $5, 0x98765432
-			li $8, 0x10000000
-			sll $0, $0, 0
-
-			sltiu $15, $2, 0x1234
-			sltiu $15, $2, 0x2345
-			sltiu $15, $2, -0x1234
-			sltiu $15, $2, -0x2345
-			
-			sltiu $15, $3, 0x1234
-			sltiu $15, $3, 0x2345
-			sltiu $15, $3, -0x1234
-			sltiu $15, $3, -0x2345
-
-			sltiu $15, $4, 0x1234
-			sltiu $15, $4, 0x2345
-			sltiu $15, $4, -0x1234
-			sltiu $15, $4, -0x2345
-			
-			sltiu $15, $5, 0x1234
-			sltiu $15, $5, 0x2345
-			sltiu $15, $5, -0x1234
-			sltiu $15, $5, -0x2345
-
-			sll $0, $0, 0
-
-			slti $15, $2, 0x1234
-			slti $15, $2, 0x2345
-			slti $15, $2, -0x1234
-			slti $15, $2, -0x2345
-			
-			slti $15, $3, 0x1234
-			slti $15, $3, 0x2345
-			slti $15, $3, -0x1234
-			slti $15, $3, -0x2345
-
-			slti $15, $4, 0x1234
-			slti $15, $4, 0x2345
-			slti $15, $4, -0x1234
-			slti $15, $4, -0x2345
-			
-			slti $15, $5, 0x1234
-			slti $15, $5, 0x2345
-			slti $15, $5, -0x1234
-			slti $15, $5, -0x2345
-
-			sll $0, $0, 0
-
-			j   main
-			sll $0, $0, 0
diff --git a/lib/CPUs/MIPS/sim/asm/test_sub.s b/lib/CPUs/MIPS/sim/asm/test_sub.s
deleted file mode 100644
index f3ee61d..0000000
--- a/lib/CPUs/MIPS/sim/asm/test_sub.s
+++ /dev/null
@@ -1,57 +0,0 @@
-#		.ktext 0x80000180
-		.text 0x00410000
-		.globl	main
-		
-main:		li $2, 0x12345678
-			li $3, 0x23456789
-			li $4, 0x87654321
-			li $5, 0x98765432
-			li $8, 0x10000000
-			sll $0, $0, 0
-
-			subu $15, $2, $2
-			subu $15, $2, $3
-			subu $15, $2, $4
-			subu $15, $2, $5
-			
-			subu $15, $3, $2
-			subu $15, $3, $3
-			subu $15, $3, $4
-			subu $15, $3, $5
-
-			subu $15, $4, $2
-			subu $15, $4, $3
-			subu $15, $4, $4
-			subu $15, $4, $5
-			
-			subu $15, $5, $2
-			subu $15, $5, $3
-			subu $15, $5, $4
-			subu $15, $5, $5
-
-			sll $0, $0, 0
-
-			sub $15, $2, $2
-			sub $15, $2, $3
-			sub $15, $2, $4
-			sub $15, $2, $5
-			
-			sub $15, $3, $2
-			sub $15, $3, $3
-			sub $15, $3, $4
-			sub $15, $3, $5
-
-			sub $15, $4, $2
-			sub $15, $4, $3
-			sub $15, $4, $4
-			sub $15, $4, $5
-			
-			sub $15, $5, $2
-			sub $15, $5, $3
-			sub $15, $5, $4
-			sub $15, $5, $5
-
-			sll $0, $0, 0
-
-			j   main
-			sll $0, $0, 0
diff --git a/lib/CPUs/MIPS/sim/asm/testbench.c b/lib/CPUs/MIPS/sim/asm/testbench.c
deleted file mode 100644
index 1cbf3b6..0000000
--- a/lib/CPUs/MIPS/sim/asm/testbench.c
+++ /dev/null
@@ -1,322 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <time.h>
-#include "utils.h"
-
-#define	NO_ERROR		0x00000000
-#define	ERROR			0x80000000
-#define	IS_ERROR(e)		((e & ERROR) == ERROR)
-
-#define	TEST10_ERROR	(ERROR | 0x10)
-#define	TEST11_ERROR	(ERROR | 0x11)
-#define	TEST12_ERROR	(ERROR | 0x12)
-
-int fibonacci(int f0, int f1, int *pDst, int len)
-{
-	int i;
-
-	i = 0;
-
-	pDst[i++] = f0;
-	pDst[i++] = f1;
-
-	for (; i < len; i++)
-	{
-		pDst[i] = pDst[i-2] + pDst[i-1];
-	}
-
-	return i;
-}
-
-int StatusRegister_read(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		"mfc0   $2, $12\n"
-		".set	reorder\n"
-
-	);
-}
-
-int RevisionRegister_read(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		"mfc0   $2, $15\n"
-		".set	reorder\n"
-
-	);
-}
-
-void PrintCPUinfo(void)
-{
-	int result, rev_id;
-
-	char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"};
-
-	// Print Status register
-	result = StatusRegister_read();
-	sputs("Status  : ");
-	print_word(result);
-	sputs("\r\n");
-
-	// Print Revision
-	result = RevisionRegister_read();
-	rev_id = (result >> 8) & 0xFF;
-	sputs("CPU type: ");
-	if ((rev_id > 0) && (rev_id < 0x07))
-	{
-		sputs(cpu_type_str[rev_id]);
-		sputs(" Rev.");
-		rev_id = result & 0xFF;
-		print_byte((char)rev_id);
-	}
-	else
-		sputs("Unknown");
-
-	sputs("\r\n");
-
-}
-
-int Test10_LoadStore()
-{
-	int *buf, i, result, data, err;
-	volatile int *pPtr;
-
-	buf = (int*)malloc(32*sizeof(int));
-	while(1)
-	{
-		err = TEST10_ERROR;
-		// Basic Load/Store
-		pPtr = buf;
-		*pPtr++ = 0x00000000;
-		*pPtr++ = 0x55555555;
-		*pPtr++ = 0xAAAAAAAA;
-		*pPtr++ = 0xFFFFFFFF;
-		pPtr = buf;
-		if (*pPtr++ != 0x00000000)
-			break;
-		if (*pPtr++ != 0x55555555)
-			break;
-		if (*pPtr++ != 0xAAAAAAAA)
-			break;
-		if (*pPtr++ != 0xFFFFFFFF)
-			break;
-
-		// Filling from left
-		pPtr = buf;
-		data = 0x00000000;
-		for (i=0; i < 32; i++)
-		{
-			*pPtr++ = data;
-			data = data >> 1 | 0x80000000;
-
-		}
-		pPtr = buf;
-		data = 0x00000000;
-		for (i=0; i < 32; i++)
-		{
-
-			if (*pPtr++ != data)
-				break;
-
-			data = data >> 1 | 0x80000000;
-		}
-		if (i != 32)
-			break;
-
-		// Filling from right
-		pPtr = buf;
-		data = 0x00000000;
-		for (i=0; i < 32; i++)
-		{
-			*pPtr++ = data;
-			data = data << 1 | 1;
-
-		}
-		pPtr = buf;
-		data = 0x00000000;
-		for (i=0; i < 32; i++)
-		{
-
-			if (*pPtr++ != data)
-				break;
-
-			data = data << 1 | 1;
-		}
-		if (i != 32)
-			break;
-
-		// Walking ones
-		pPtr = buf;
-		data = 0x00000001;
-		for (i=0; i < 32; i++)
-		{
-			*pPtr++ = data;
-			data = data << 1;
-
-		}
-		pPtr = buf;
-		data = 0x00000001;
-		for (i=0; i < 32; i++)
-		{
-
-			if (*pPtr++ != data)
-				break;
-
-			data = data << 1;
-		}
-		if (i != 32)
-			break;
-
-		// Walking zeros
-		pPtr = buf;
-		data = 0xFFFFFFFE;
-		for (i=0; i < 32; i++)
-		{
-			*pPtr++ = data;
-			data = data << 1 | 1;
-
-		}
-		pPtr = buf;
-		data = 0xFFFFFFFE;
-		for (i=0; i < 32; i++)
-		{
-
-			if (*pPtr++ != data)
-				break;
-
-			data = data << 1 | 1;
-
-		}
-		if (i != 32)
-			break;
-
-		err = NO_ERROR;
-		break;
-	}
-	free(buf);
-	return err;
-
-}
-
-
-#define	NUM_ELEMENTS	20
-#define	NUM_RUNS		3
-int Test11_AddSub()
-{
-	int buf[NUM_ELEMENTS], result, i, j, diff, fill, num_right_elements, num_right_runs;
-
-	fill = 0xAAAAAAAA;
-
-	num_right_runs = 0;
-
-	for (i=0; i < NUM_RUNS; i++)
-	{
-		for (j=0;  j < NUM_ELEMENTS; j++)
-			buf[j] = fill;
-
-		fill = ((fill ^ i) - 1) << 1;
-		num_right_elements = 2;
-		result = fibonacci(i, i+1, buf, NUM_ELEMENTS);
-		for (j=2;  j < NUM_ELEMENTS; j++)
-		{
-			diff = buf[j] - buf[j-1];
-			if (diff == buf[j-2])
-				num_right_elements++;
-		}
-		if (num_right_elements == NUM_ELEMENTS)
-			num_right_runs++;
-	}
-
-	if (num_right_runs != NUM_RUNS)
-		return TEST11_ERROR;
-
-	return NO_ERROR;
-}
-
-int Test12_MulDiv()
-{
-	int mix, i, j;
-	int s1, s2, sp, st;
-	div_t div_res;
-
-	srand(0x19701031);
-	for (i=0; i < 100; i++)
-	{
-		for (j=1; j < 1000; j++)
-		{
-			mix = (int)rand();
-			mix = (mix << 8) ^ (mix << 16);
-			s1 = (int)rand() ^ mix;
-			mix = (int)rand();
-			mix = (mix << 8) ^ (mix << 16);
-			s2 = (int)rand() ^ mix;
-
-			div_res = div(s1, s2);
-
-			sp = s2*div_res.quot;
-			st = div_res.rem + sp;
-			if (st != s1)
-				return TEST12_ERROR;
-		}
-	}
-	return NO_ERROR;
-}
-
-int main (void)
-{
-	int result, i, j, cnt;
-	volatile char *pUART_baud = (char*)0x80000009;
-	volatile int *pReg = (int*)0x80000000;
-	volatile int *pReg_usec = (int*)0x80000010;
-	volatile int *pReg_sec = (int*)0x80000014;
-	time_t clock;
-	struct tm *pDate;
-//	*pUART_baud = 0x35/4;
-
-	PrintCPUinfo();
-
-	cnt = 0;
-//	*pReg_sec = 0x12345678;
-	while (1)
-	{
-		*pReg = cnt & 0x3FFFFFFF;
-
-		result = Test10_LoadStore();
-		if (IS_ERROR(result))
-			break;
-
-		result = Test11_AddSub();
-		if (IS_ERROR(result))
-			break;
-
-		result = Test12_MulDiv();
-		if (IS_ERROR(result))
-			break;
-
-//		printf("Iteration %d: Passed\r\n", cnt++);
-		sputs("Iteration ");
-		print_word(cnt++);
-		sputs(": Passed\r\n");
-
-		clock = time(NULL);
-		pDate = gmtime(&clock);
-		print_byte(pDate->tm_hour);
-		sputs(":");
-		print_byte(pDate->tm_min);
-		sputs(":");
-		print_byte(pDate->tm_sec);
-		sputs("\r\n");
-	}
-	*pReg = 0x40000000 | cnt;
-	sputs("Failed with error ");
-	print_word(result);
-	sputs(" \r\n");
-
-	return 1;
-
-}
-
diff --git a/lib/CPUs/MIPS/sim/asm/testbench.s b/lib/CPUs/MIPS/sim/asm/testbench.s
deleted file mode 100644
index acc1d4d..0000000
--- a/lib/CPUs/MIPS/sim/asm/testbench.s
+++ /dev/null
@@ -1,924 +0,0 @@
-	.file	1 "testbench.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	fibonacci
-	.ent	fibonacci
-fibonacci:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$8,2			# 0x2
-	slt	$2,$8,$7
-	sw	$4,0($6)
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L7
-	sw	$5,4($6)
-	.set	macro
-	.set	reorder
-
-	addiu	$6,$6,8
-$L5:
-	lw	$2,-8($6)
-	lw	$3,-4($6)
-	addiu	$8,$8,1
-	addu	$2,$2,$3
-	slt	$4,$8,$7
-	sw	$2,0($6)
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L5
-	addiu	$6,$6,4
-	.set	macro
-	.set	reorder
-
-$L7:
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	move	$2,$8
-	.set	macro
-	.set	reorder
-
-	.end	fibonacci
-	.align	2
-	.globl	StatusRegister_read
-	.ent	StatusRegister_read
-StatusRegister_read:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
- #APP
-	.set	noreorder
-mfc0   $2, $12
-.set	reorder
-
- #NO_APP
-	j	$31
-	.end	StatusRegister_read
-	.align	2
-	.globl	RevisionRegister_read
-	.ent	RevisionRegister_read
-RevisionRegister_read:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
- #APP
-	.set	noreorder
-mfc0   $2, $15
-.set	reorder
-
- #NO_APP
-	j	$31
-	.end	RevisionRegister_read
-	.section	.rodata.str1.4,"aMS",@progbits,1
-	.align	2
-$LC0:
-	.ascii	"invalid\000"
-	.align	2
-$LC1:
-	.ascii	"R2000\000"
-	.align	2
-$LC2:
-	.ascii	"R3000\000"
-	.align	2
-$LC3:
-	.ascii	"R6000\000"
-	.align	2
-$LC4:
-	.ascii	"R4000\000"
-	.align	2
-$LC5:
-	.ascii	"reserved\000"
-	.align	2
-$LC6:
-	.ascii	"R6000A\000"
-	.rdata
-	.align	2
-$LC7:
-	.word	$LC0
-	.word	$LC1
-	.word	$LC2
-	.word	$LC3
-	.word	$LC4
-	.word	$LC5
-	.word	$LC6
-	.section	.rodata.str1.4
-	.align	2
-$LC8:
-	.ascii	"Status  : \000"
-	.align	2
-$LC9:
-	.ascii	"\r\n\000"
-	.align	2
-$LC10:
-	.ascii	"CPU type: \000"
-	.align	2
-$LC12:
-	.ascii	"Unknown\000"
-	.align	2
-$LC11:
-	.ascii	" Rev.\000"
-	.text
-	.align	2
-	.globl	PrintCPUinfo
-	.ent	PrintCPUinfo
-PrintCPUinfo:
-	.frame	$sp,64,$31		# vars= 32, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	lw	$2,$LC7
-	addiu	$sp,$sp,-64
-	lw	$3,$LC7+4
-	sw	$2,16($sp)
-	lw	$2,$LC7+8
-	sw	$3,20($sp)
-	sw	$2,24($sp)
-	lw	$3,$LC7+12
-	lw	$2,$LC7+16
-	sw	$3,28($sp)
-	sw	$2,32($sp)
-	lw	$3,$LC7+20
-	lw	$2,$LC7+24
-	sw	$3,36($sp)
-	sw	$31,56($sp)
-	sw	$17,52($sp)
-	sw	$16,48($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	StatusRegister_read
-	sw	$2,40($sp)
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC8
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$17,$2
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC9
-	jal	sputs
-	jal	RevisionRegister_read
-	sra	$16,$2,8
-	andi	$16,$16,0xff
-	la	$4,$LC10
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$17,$2
-	.set	macro
-	.set	reorder
-
-	sll	$3,$16,2
-	addiu	$16,$16,-1
-	sltu	$16,$16,6
-	la	$4,$LC12
-	.set	noreorder
-	.set	nomacro
-	beq	$16,$0,$L12
-	addu	$2,$sp,$3
-	.set	macro
-	.set	reorder
-
-	lw	$4,16($2)
-	jal	sputs
-	la	$4,$LC11
-	jal	sputs
-	sll	$4,$17,24
-	.set	noreorder
-	.set	nomacro
-	jal	print_byte
-	sra	$4,$4,24
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC9
-	jal	sputs
-	lw	$31,56($sp)
-	lw	$17,52($sp)
-	lw	$16,48($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,64
-	.set	macro
-	.set	reorder
-
-$L12:
-	jal	sputs
-	la	$4,$LC9
-	jal	sputs
-	lw	$31,56($sp)
-	lw	$17,52($sp)
-	lw	$16,48($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,64
-	.set	macro
-	.set	reorder
-
-	.end	PrintCPUinfo
-	.align	2
-	.globl	Test10_LoadStore
-	.ent	Test10_LoadStore
-Test10_LoadStore:
-	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
-	.mask	0x80010000,-4
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-24
-	li	$4,128			# 0x80
-	sw	$31,20($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	malloc
-	sw	$16,16($sp)
-	.set	macro
-	.set	reorder
-
-	move	$4,$2
-	li	$2,1431633920			# 0x55550000
-	li	$3,-1431699456			# 0xffffffffaaaa0000
-	ori	$5,$2,0x5555
-	ori	$6,$3,0xaaaa
-	li	$7,-1			# 0xffffffffffffffff
-	sw	$0,0($4)
-	sw	$5,4($4)
-	sw	$6,8($4)
-	sw	$7,12($4)
-	lw	$3,0($4)
-	li	$2,-2147483648			# 0xffffffff80000000
-	.set	noreorder
-	.set	nomacro
-	bne	$3,$0,$L16
-	ori	$16,$2,0x10
-	.set	macro
-	.set	reorder
-
-	lw	$2,4($4)
-	beq	$2,$5,$L73
-$L16:
-	jal	free
-	move	$2,$16
-	lw	$31,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,24
-	.set	macro
-	.set	reorder
-
-$L73:
-	lw	$2,8($4)
-	bne	$2,$6,$L16
-	lw	$2,12($4)
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$7,$L16
-	move	$3,$4
-	.set	macro
-	.set	reorder
-
-	move	$5,$0
-	li	$7,-2147483648			# 0xffffffff80000000
-	li	$6,31			# 0x1f
-$L24:
-	sra	$2,$5,1
-	addiu	$6,$6,-1
-	sw	$5,0($3)
-	addiu	$3,$3,4
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L24
-	or	$5,$2,$7
-	.set	macro
-	.set	reorder
-
-	move	$3,$4
-	move	$5,$0
-	move	$6,$0
-	.set	noreorder
-	.set	nomacro
-	j	$L29
-	li	$8,-2147483648			# 0xffffffff80000000
-	.set	macro
-	.set	reorder
-
-$L74:
-	addiu	$6,$6,1
-	slt	$2,$6,32
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L26
-	or	$5,$7,$8
-	.set	macro
-	.set	reorder
-
-$L29:
-	lw	$2,0($3)
-	sra	$7,$5,1
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$5,$L74
-	addiu	$3,$3,4
-	.set	macro
-	.set	reorder
-
-$L26:
-	li	$2,32			# 0x20
-	.set	noreorder
-	.set	nomacro
-	bne	$6,$2,$L16
-	move	$3,$4
-	.set	macro
-	.set	reorder
-
-	move	$5,$0
-	li	$6,31			# 0x1f
-$L34:
-	sll	$2,$5,1
-	addiu	$6,$6,-1
-	sw	$5,0($3)
-	addiu	$3,$3,4
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L34
-	ori	$5,$2,0x1
-	.set	macro
-	.set	reorder
-
-	move	$3,$4
-	move	$5,$0
-	.set	noreorder
-	.set	nomacro
-	j	$L39
-	move	$6,$0
-	.set	macro
-	.set	reorder
-
-$L75:
-	addiu	$6,$6,1
-	slt	$2,$6,32
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L36
-	ori	$5,$7,0x1
-	.set	macro
-	.set	reorder
-
-$L39:
-	lw	$2,0($3)
-	sll	$7,$5,1
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$5,$L75
-	addiu	$3,$3,4
-	.set	macro
-	.set	reorder
-
-$L36:
-	li	$2,32			# 0x20
-	.set	noreorder
-	.set	nomacro
-	bne	$6,$2,$L16
-	move	$3,$4
-	.set	macro
-	.set	reorder
-
-	li	$5,1			# 0x1
-	li	$6,31			# 0x1f
-$L44:
-	addiu	$6,$6,-1
-	sw	$5,0($3)
-	addiu	$3,$3,4
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L44
-	sll	$5,$5,1
-	.set	macro
-	.set	reorder
-
-	move	$3,$4
-	li	$5,1			# 0x1
-	.set	noreorder
-	.set	nomacro
-	j	$L49
-	move	$6,$0
-	.set	macro
-	.set	reorder
-
-$L76:
-	addiu	$6,$6,1
-	slt	$2,$6,32
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L46
-	sll	$5,$5,1
-	.set	macro
-	.set	reorder
-
-$L49:
-	lw	$2,0($3)
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$5,$L76
-	addiu	$3,$3,4
-	.set	macro
-	.set	reorder
-
-$L46:
-	li	$2,32			# 0x20
-	.set	noreorder
-	.set	nomacro
-	bne	$6,$2,$L16
-	move	$3,$4
-	.set	macro
-	.set	reorder
-
-	li	$5,-2			# 0xfffffffffffffffe
-	li	$6,31			# 0x1f
-$L54:
-	sll	$2,$5,1
-	addiu	$6,$6,-1
-	sw	$5,0($3)
-	addiu	$3,$3,4
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L54
-	ori	$5,$2,0x1
-	.set	macro
-	.set	reorder
-
-	move	$3,$4
-	li	$5,-2			# 0xfffffffffffffffe
-	.set	noreorder
-	.set	nomacro
-	j	$L59
-	move	$6,$0
-	.set	macro
-	.set	reorder
-
-$L77:
-	addiu	$6,$6,1
-	slt	$2,$6,32
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L56
-	ori	$5,$7,0x1
-	.set	macro
-	.set	reorder
-
-$L59:
-	lw	$2,0($3)
-	sll	$7,$5,1
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$5,$L77
-	addiu	$3,$3,4
-	.set	macro
-	.set	reorder
-
-$L56:
-	li	$2,32			# 0x20
-	bne	$6,$2,$L16
-	.set	noreorder
-	.set	nomacro
-	j	$L16
-	move	$16,$0
-	.set	macro
-	.set	reorder
-
-	.end	Test10_LoadStore
-	.align	2
-	.globl	Test11_AddSub
-	.ent	Test11_AddSub
-Test11_AddSub:
-	.frame	$sp,120,$31		# vars= 80, regs= 5/0, args= 16, gp= 0
-	.mask	0x800f0000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-120
-	li	$2,-1431699456			# 0xffffffffaaaa0000
-	sw	$19,108($sp)
-	sw	$18,104($sp)
-	sw	$16,96($sp)
-	sw	$31,112($sp)
-	sw	$17,100($sp)
-	ori	$16,$2,0xaaaa
-	move	$19,$0
-	move	$4,$0
-	addiu	$18,$sp,16
-$L92:
-	move	$2,$18
-	li	$6,19			# 0x13
-$L85:
-	addiu	$6,$6,-1
-	sw	$16,0($2)
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L85
-	addiu	$2,$2,4
-	.set	macro
-	.set	reorder
-
-	xor	$2,$16,$4
-	addiu	$17,$4,1
-	addiu	$2,$2,-1
-	move	$5,$17
-	addiu	$6,$sp,16
-	li	$7,20			# 0x14
-	.set	noreorder
-	.set	nomacro
-	jal	fibonacci
-	sll	$16,$2,1
-	.set	macro
-	.set	reorder
-
-	li	$7,2			# 0x2
-	addiu	$5,$18,8
-	.set	noreorder
-	.set	nomacro
-	j	$L90
-	li	$6,17			# 0x11
-	.set	macro
-	.set	reorder
-
-$L88:
-	bltz	$6,$L100
-$L90:
-	lw	$2,0($5)
-	lw	$3,-4($5)
-	lw	$4,-8($5)
-	subu	$2,$2,$3
-	addiu	$6,$6,-1
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$2,$L88
-	addiu	$5,$5,4
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L90
-	addiu	$7,$7,1
-	.set	macro
-	.set	reorder
-
-$L100:
-	li	$6,20			# 0x14
-	beq	$7,$6,$L101
-$L81:
-	slt	$2,$17,3
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L92
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-	li	$2,3			# 0x3
-	.set	noreorder
-	.set	nomacro
-	bne	$19,$2,$L102
-	move	$3,$0
-	.set	macro
-	.set	reorder
-
-	lw	$31,112($sp)
-	lw	$19,108($sp)
-	lw	$18,104($sp)
-	lw	$17,100($sp)
-	lw	$16,96($sp)
-	move	$2,$3
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,120
-	.set	macro
-	.set	reorder
-
-$L101:
-	.set	noreorder
-	.set	nomacro
-	j	$L81
-	addiu	$19,$19,1
-	.set	macro
-	.set	reorder
-
-$L102:
-	li	$2,-2147483648			# 0xffffffff80000000
-	ori	$3,$2,0x11
-	lw	$31,112($sp)
-	lw	$19,108($sp)
-	lw	$18,104($sp)
-	lw	$17,100($sp)
-	lw	$16,96($sp)
-	move	$2,$3
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,120
-	.set	macro
-	.set	reorder
-
-	.end	Test11_AddSub
-	.align	2
-	.globl	Test12_MulDiv
-	.ent	Test12_MulDiv
-Test12_MulDiv:
-	.frame	$sp,48,$31		# vars= 8, regs= 5/0, args= 16, gp= 0
-	.mask	0x800f0000,-8
-	.fmask	0x00000000,0
-	li	$4,426770432			# 0x19700000
-	addiu	$sp,$sp,-48
-	ori	$4,$4,0x1031
-	sw	$19,36($sp)
-	sw	$31,40($sp)
-	sw	$18,32($sp)
-	sw	$17,28($sp)
-	sw	$16,24($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	srand
-	move	$19,$0
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	j	$L111
-	li	$18,1			# 0x1
-	.set	macro
-	.set	reorder
-
-$L109:
-	beq	$4,$0,$L117
-$L111:
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	addiu	$18,$18,1
-	.set	macro
-	.set	reorder
-
-	sll	$3,$2,16
-	sll	$2,$2,8
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	xor	$16,$2,$3
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	xor	$17,$2,$16
-	.set	macro
-	.set	reorder
-
-	sll	$3,$2,16
-	sll	$2,$2,8
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	xor	$16,$2,$3
-	.set	macro
-	.set	reorder
-
-	xor	$16,$2,$16
-	addiu	$4,$sp,16
-	move	$5,$17
-	.set	noreorder
-	.set	nomacro
-	jal	div
-	move	$6,$16
-	.set	macro
-	.set	reorder
-
-	lw	$3,16($sp)
-	lw	$2,20($sp)
-	mult	$3,$16
-	mflo	$3
-	addu	$2,$2,$3
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$17,$L109
-	slt	$4,$18,1000
-	.set	macro
-	.set	reorder
-
-	li	$2,-2147483648			# 0xffffffff80000000
-	ori	$2,$2,0x12
-$L103:
-	lw	$31,40($sp)
-	lw	$19,36($sp)
-	lw	$18,32($sp)
-	lw	$17,28($sp)
-	lw	$16,24($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,48
-	.set	macro
-	.set	reorder
-
-$L117:
-	addiu	$19,$19,1
-	slt	$2,$19,100
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L111
-	li	$18,1			# 0x1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	j	$L103
-	move	$2,$0
-	.set	macro
-	.set	reorder
-
-	.end	Test12_MulDiv
-	.section	.rodata.str1.4
-	.align	2
-$LC13:
-	.ascii	"Iteration %d: Passed\r\n\000"
-	.align	2
-$LC14:
-	.ascii	"Iteration \000"
-	.align	2
-$LC15:
-	.ascii	": Passed\r\n\000"
-	.align	2
-$LC16:
-	.ascii	":\000"
-	.align	2
-$LC17:
-	.ascii	"Failed with error \000"
-	.align	2
-$LC18:
-	.ascii	" \r\n\000"
-	.text
-	.align	2
-	.globl	main
-	.ent	main
-main:
-	.frame	$sp,48,$31		# vars= 8, regs= 5/0, args= 16, gp= 0
-	.mask	0x800f0000,-8
-	.fmask	0x00000000,0
-	li	$3,-2147483648			# 0xffffffff80000000
-	li	$2,13
-	ori	$3,$3,0x9
-	addiu	$sp,$sp,-48
-	sb	$2,0($3)
-	sw	$19,36($sp)
-	sw	$18,32($sp)
-	sw	$17,28($sp)
-	sw	$31,40($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	PrintCPUinfo
-	sw	$16,24($sp)
-	.set	macro
-	.set	reorder
-
-	li	$2,1073676288			# 0x3fff0000
-	ori	$19,$2,0xffff
-	li	$18,-2147483648			# 0xffffffff80000000
-	.set	noreorder
-	.set	nomacro
-	j	$L119
-	move	$17,$0
-	.set	macro
-	.set	reorder
-
-$L124:
-	jal	Test11_AddSub
-	.set	noreorder
-	.set	nomacro
-	bltz	$2,$L120
-	move	$16,$2
-	.set	macro
-	.set	reorder
-
-	jal	Test12_MulDiv
-	move	$16,$2
-	la	$4,$LC13
-	.set	noreorder
-	.set	nomacro
-	bltz	$2,$L120
-	move	$5,$17
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	printf
-	addiu	$17,$17,1
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC14
-	jal	sputs
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC15
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	addiu	$17,$17,1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	time
-	move	$4,$0
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$sp,16
-	.set	noreorder
-	.set	nomacro
-	jal	gmtime
-	sw	$2,16($sp)
-	.set	macro
-	.set	reorder
-
-	lb	$4,8($2)
-	.set	noreorder
-	.set	nomacro
-	jal	print_byte
-	move	$16,$2
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC16
-	jal	sputs
-	lb	$4,4($16)
-	jal	print_byte
-	la	$4,$LC16
-	jal	sputs
-	lb	$4,0($16)
-	jal	print_byte
-	la	$4,$LC9
-	jal	sputs
-$L119:
-	and	$2,$17,$19
-	sw	$2,0($18)
-	jal	Test10_LoadStore
-	.set	noreorder
-	.set	nomacro
-	bgez	$2,$L124
-	move	$16,$2
-	.set	macro
-	.set	reorder
-
-$L120:
-	li	$2,1073741824			# 0x40000000
-	or	$2,$17,$2
-	la	$4,$LC17
-	sw	$2,0($18)
-	jal	sputs
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$16
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC18
-	jal	sputs
-	lw	$31,40($sp)
-	lw	$19,36($sp)
-	lw	$18,32($sp)
-	lw	$17,28($sp)
-	lw	$16,24($sp)
-	li	$2,1			# 0x1
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,48
-	.set	macro
-	.set	reorder
-
-	.end	main
diff --git a/lib/CPUs/MIPS/sim/asm/utils.c b/lib/CPUs/MIPS/sim/asm/utils.c
deleted file mode 100644
index b704173..0000000
--- a/lib/CPUs/MIPS/sim/asm/utils.c
+++ /dev/null
@@ -1,179 +0,0 @@
-#include <sys/times.h>
-#include <sys/time.h>
-#include <sys/stat.h>
-#include <stdlib.h>
-
-char readchar(void)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while(!(0x10 & *pUART_stat));
-
-	return *pUART_data;
-}
-
-void writechar(char c)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while((0x02 & *pUART_stat) != 0);
-
-	*pUART_data = c;
-}
-
-clock_t times(struct tms *buffer)
-{
-	volatile long *pReg_usec = (long*)0x80000010;
-	volatile long *pReg_sec = (long*)0x80000014;
-	long sec;
-
-	sec = *pReg_sec;
-
-	if (buffer)
-	{
-		buffer->tms_utime = sec;
-		buffer->tms_stime = 0;
-		buffer->tms_cutime = 0;
-		buffer->tms_cstime = 0;
-	}
-
-	return (clock_t)sec;
-}
-
-int gettimeofday(struct timeval *tp, void *tzp)
-{
-	volatile long *pReg_usec = (long*)0x80000010;
-	volatile long *pReg_sec = (long*)0x80000014;
-
-	if (tp)
-	{
-		tp->tv_sec = *pReg_sec;
-		tp->tv_usec = *pReg_usec;
-	}
-
-	return 0;
-}
-
-int settimeofday(const struct timeval *tp, const struct timezone *tzp)
-{
-	volatile long *pReg_usec = (long*)0x80000010;
-	volatile long *pReg_sec = (long*)0x80000014;
-	div_t res;
-
-	res = div(tp->tv_usec, 1E6);
-
-	if (tp)
-	{
-		*pReg_usec = res.rem;
-		*pReg_sec  = tp->tv_sec + res.quot;
-	}
-
-	return 0;
-}
-
-caddr_t sbrk(int incr)
-{
-	extern char end;
-	static char *heap_end;
-	char *prev_heap_end;
-
-	if (heap_end == 0)
-		heap_end = &end;
-
-	prev_heap_end = heap_end;
-//	if (heap_end + incr > stack_ptr)
-//	{
-//		_write(1, "Heap and stack collision\n", 25);
-//		abort();
-//	}
-
-	heap_end += incr;
-	return (caddr_t) prev_heap_end;
-}
-
-int fstat(int file, struct stat *st)
-{
-	st->st_mode = S_IFCHR;
-	return 0;
-}
-
-int lseek(int file, int ptr, int dir)
-{
-	return 0;
-}
-
-int open(const char *name, int flags, int mode)
-{
-	return -1;
-}
-
-int close(int file)
-{
-	return -1;
-}
-
-int read(int file, char *ptr, int len)
-{
-	return 0;
-}
-
-int write(int file, char *ptr, int len)
-{
-	int i;
-
-	for (i=0; i < len; i++)
-		writechar(*ptr++);
-
-	return i;
-}
-
-int isatty(int file)
-{
-	return 1;
-}
-
-int sputs(char *pStr)
-{
-	char *start;
-	start = pStr;
-
-	while(*pStr)
-		writechar(*(pStr++));
-
-	return pStr - start;
-}
-
-void print_byte(char byte)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 2; i++)
-	{
-		nibble = (char)((byte >> 4) & 0xF);
-		byte <<= 4;
-
-		if (nibble < 10)
-			c = nibble + '0';
-		else
-			c = nibble + 'A' - 10;
-
-		writechar(c);
-	}
-}
-
-void print_word(int word)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 4; i++)
-	{
-		c = (char) (word >> 24);
-		print_byte(c);
-		word <<= 8;
-	}
-}
-
diff --git a/lib/CPUs/MIPS/sim/asm/utils.h b/lib/CPUs/MIPS/sim/asm/utils.h
deleted file mode 100644
index aab48c4..0000000
--- a/lib/CPUs/MIPS/sim/asm/utils.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef UTILS_H
-#define UTILS_H
-
-char readchar(void);
-void writechar(char c);
-int write(int file, char *ptr, int len);
-int sputs(char *pStr);
-void print_byte(char byte);
-void print_word(int word);
-
-#endif // UTILS_H
-
diff --git a/lib/CPUs/MIPS/sim/asm/utils.s b/lib/CPUs/MIPS/sim/asm/utils.s
deleted file mode 100644
index 56b6d8c..0000000
--- a/lib/CPUs/MIPS/sim/asm/utils.s
+++ /dev/null
@@ -1,184 +0,0 @@
-	.file	1 "utils.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	sein
-	.ent	sein
-sein:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	ori	$4,$2,0x4
-	ori	$3,$2,0x8
-$L2:
-	lbu	$2,0($3)
-	andi	$2,$2,0x10
-	beq	$2,$0,$L2
-	lbu	$2,0($4)
-	sll	$2,$2,24
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	sra	$2,$2,24
-	.set	macro
-	.set	reorder
-
-	.end	sein
-	.align	2
-	.globl	saus
-	.ent	saus
-saus:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	sll	$4,$4,24
-	sra	$4,$4,24
-	ori	$5,$2,0x4
-	ori	$3,$2,0x8
-$L6:
-	lbu	$2,0($3)
-	andi	$2,$2,0x2
-	bne	$2,$0,$L6
-	sb	$4,0($5)
-	j	$31
-	.end	saus
-	.align	2
-	.globl	sputs
-	.ent	sputs
-sputs:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	lb	$4,0($4)
-	.set	noreorder
-	.set	nomacro
-	j	$L14
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-$L15:
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-	lb	$4,0($16)
-$L14:
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L15
-	subu	$2,$16,$17
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	sputs
-	.align	2
-	.globl	print_byte
-	.ent	print_byte
-print_byte:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$16,16($sp)
-	sll	$16,$4,24
-	sw	$17,20($sp)
-	sw	$31,24($sp)
-	sra	$16,$16,24
-	li	$17,1			# 0x1
-	sra	$2,$16,4
-$L25:
-	andi	$5,$2,0xf
-	sll	$2,$16,4
-	sll	$16,$2,24
-	sltu	$3,$5,10
-	addiu	$17,$17,-1
-	sra	$16,$16,24
-	.set	noreorder
-	.set	nomacro
-	bne	$3,$0,$L21
-	addiu	$4,$5,48
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$5,55
-$L21:
-	jal	saus
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L25
-	sra	$2,$16,4
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_byte
-	.align	2
-	.globl	print_word
-	.ent	print_word
-print_word:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	li	$17,3			# 0x3
-$L30:
-	sra	$4,$16,24
-	.set	noreorder
-	.set	nomacro
-	jal	print_byte
-	addiu	$17,$17,-1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L30
-	sll	$16,$16,8
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_word