- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1544 cc03376c-175c-47c8-b038-4cd826a8556b

projects/mips_sys/ghdl/tb_mips_sys.make

@@ -0,0 +1,109 @@
+# -----------------------------------------------------------
+include $(VHDL_HOME)/make/defs.mk
+# -----------------------------------------------------------
+include $(LIB_PATH)/CPUs/MIPS/ghdl/mips_core.inc
+include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
+include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
+include $(LIB_PATH)/emac/ghdl/emac_jbus.inc
+
+# Configs
+SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
+SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd
+SRCS += $(LIB_PATH)/models/memory/sdram/mt46v16m16/mt46v16m16.vhd
+SRCS += ../src/sdram_config_sim.vhd
+
+# Clock Generator
+SRCS += ../src/clockgen.vhd
+
+# UART
+SRCS += $(LIB_PATH)/uart/src/uart_types.vhd
+SRCS += $(LIB_PATH)/uart/src/sim/uart.vhd
+SRCS += $(LIB_PATH)/uart/src/uart_wb.vhd
+
+# MIPS
+SRCS += $(MIPS_CORE_SRCS)
+
+# ROM
+#vcom -explicit  -93 "Z:/work/repos/mips/src/bootloader/test.ROM.vhd"
+SRCS += ../src/bootloader_flash.ROM.vhd
+SRCS += $(LIB_PATH)/JBUS/memory/src/rom_wb.vhd
+
+# RAMS 
+SRCS += $(LIB_PATH)/rams/sim/src/dpram_1w1r2c_ro.vhd
+
+# VGA
+SRCS += $(LIB_PATH)/VGA_ctrl/src/fonts/char_rom_c64.vhd
+SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_types.vhd
+SRCS += $(LIB_PATH)/VGA_ctrl/src/char_gen.vhd
+SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_sync.vhd
+SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_timing.vhd
+SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_backend.vhd
+SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_frontend64.vhd
+
+# UART
+SRCS += $(LIB_PATH)/uart/src/uart_types.vhd
+SRCS += $(LIB_PATH)/uart/src/sim/uart.vhd
+SRCS += $(LIB_PATH)/uart/src/uart_wb.vhd
+
+# PS2
+SRCS += $(LIB_PATH)/ps2_port/src/debounce.vhd
+SRCS += $(LIB_PATH)/ps2_port/src/ps2_core.vhd
+SRCS += $(LIB_PATH)/ps2_port/src/ps2_phy_virtex.vhd
+SRCS += $(LIB_PATH)/ps2_port/src/ps2_wb.vhd
+
+# GPIO
+SRCS += $(LIB_PATH)/JBUS/gpio/src/gpio_wb.vhd
+
+# LCD
+SRCS += $(LIB_PATH)/misc/lcd_port.vhd
+
+# Flash and USB
+SRCS += $(LIB_PATH)/JBUS/async_port/src/async_types.vhd
+SRCS += $(LIB_PATH)/JBUS/async_port/src/async_port_wb.vhd
+SRCS += $(LIB_PATH)/JBUS/flash_port/src/flash_port_wb.vhd
+SRCS += ../src/async_defs_sim.vhd
+
+# Sync SRAM
+SRCS += $(LIB_PATH)/SSRAM/src/package_utility.vhd
+SRCS += $(LIB_PATH)/SSRAM/src/CY7C1354B.vhd
+SRCS += $(LIB_PATH)/SSRAM/src/ssram_port_wb.vhd
+
+# SDRAM
+SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
+SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd
+SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
+SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd
+SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb64.vhd
+
+# AC-97
+SRCS += $(LIB_PATH)/misc/singleshot.vhd
+SRCS += $(LIB_PATH)/ac97_ctrl/src/core/ac_out.vhd
+SRCS += $(LIB_PATH)/ac97_ctrl/src/core/ac_in.vhd
+SRCS += $(LIB_PATH)/ac97_ctrl/src/core/ac_io.vhd
+SRCS += $(LIB_PATH)/ac97_ctrl/src/core/ac97_wb.vhd
+
+# Ethernet MAC
+SRCS += $(EMAC_JBUS_SRCS)
+
+# Async port
+SRCS += $(LIB_PATH)/JBUS/async_port/src/async_types.vhd
+SRCS += $(LIB_PATH)/JBUS/async_port/src/async_port_wb.vhd
+SRCS += ../src/async_defs.vhd
+
+# Top and TB
+SRCS += ../src/mips_sys_sim.vhd
+SRCS += ../src/tb_mips_sys.vhd
+
+# Compile
+TARGET := tb_mips_sys
+ENTITY = tb_mips_sys
+RUN_TIME := 10ms
+WITH_VCD := y
+
+GHDL_OPTS := -P$(ROOT_PATH)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
+
+include $(VHDL_HOME)/make/ghdl.mk
+

projects/mips_sys/src/mips_sys_sim.vhd

@@ -193,6 +193,7 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal ps2_data_rx	: std_logic;
 	signal ps2_clk_tx	: std_logic;
 	signal ps2_data_tx	: std_logic;
+	signal gmii_clk		: std_logic;
 		
 	-- Arbiter
 	constant ARB_MAX_MASTER	: natural := 2;
@@ -369,7 +370,7 @@ BEGIN
 
 	sys_flash_ac97_rstn		<= ac97_rstn and flash_rstn;
 	vga_ce					<= not vga_rst;
-	
+	sys_phy_gtx_clk			<= gmii_clk;	
 sys_flash_ssram_out:
 	process(CLK_O)
 	begin
@@ -838,6 +839,21 @@ inst_clocken_vga : entity work.clockgen
 		clk_out				=> vga_clk
 	);
 
+inst_clockgen_gmii : entity work.clockgen
+	GENERIC MAP
+	(
+		clk_in_freq		=> sys_freq_in,
+		clk_out_freq		=> 125.0
+	)
+	PORT MAP 
+	(
+		-- Clocks and Reset
+		rst_in				=> rst_in,
+		clk_in				=> sys_clk_in,
+		rst_out				=> open,
+		clk_out				=> gmii_clk
+	);
+
 inst_sdram_ctrl_wb64 : entity work.ctrl_ddr_wb64
 	GENERIC MAP
 	(
@@ -1022,7 +1038,7 @@ inst_emac_jb : entity work.emac_top_jb
 		mii_tx_en	=> sys_phy_tx_en,
 		mii_tx_er	=> sys_phy_tx_er,
 		mii_tx		=> sys_phy_tx,
-		mii_gtx_clk	=> sys_phy_gtx_clk,
+		mii_gtx_clk	=> gmii_clk,
 		mii_crs		=> sys_phy_crs,
 		mii_col		=> sys_phy_col
 		

projects/mips_sys/src/tb_mips_sys.vhd

@@ -140,6 +140,9 @@ ARCHITECTURE behavior OF tb_mips_sys IS
 	signal	ac_right			: unsigned(17 downto 0) := X"0000" & "01";
 	signal  ac_synced			:  std_logic;
 
+	signal slv_flash_ssram_d	: STD_LOGIC_VECTOR(sys_flash_ssram_d'left downto sys_flash_ssram_d'right);
+	signal slv_ssram_dp			: STD_LOGIC_VECTOR(sys_ssram_dp'left downto sys_ssram_dp'right);
+		
 BEGIN
 
 uut: entity work.mips_sys
@@ -243,11 +246,14 @@ uut: entity work.mips_sys
 	sys_phy_crs		<= '0';
 	sys_phy_col		<= '0';
 
+	slv_flash_ssram_d	<= STD_LOGIC_VECTOR(sys_flash_ssram_d);
+	slv_ssram_dp		<= STD_LOGIC_VECTOR(sys_ssram_dp);
+	
 inst_ssram : entity work.cy7c1354
     PORT MAP 
     (
-		Dq		=> STD_LOGIC_VECTOR(sys_flash_ssram_d),   	-- Data I/O
+		Dq		=> slv_flash_ssram_d,   	-- Data I/O
-		Dpq		=> STD_LOGIC_VECTOR(sys_ssram_dp),   	-- Data I/O
+		Dpq		=> slv_ssram_dp,   	-- Data I/O
 		Addr	=> STD_LOGIC_VECTOR(sys_flash_ssram_a(18 downto 1)),   	-- Address
 		Mode	=> sys_ssram_mode, 	-- Burst Mode
 		Clk		=> sys_ssram_clk,      -- Clk