jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- added

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1544 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-28 11:07:17 +00:00
parent 881893fda3
commit 795ca6b382
5 changed files with 137 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/mips_sys_sim.vhd
+19 -3
View File
@@ -193,7 +193,8 @@ ARCHITECTURE behavior OF mips_sys IS
signal ps2_data_rx : std_logic;
signal ps2_clk_tx : std_logic;
signal ps2_data_tx : std_logic;
signal gmii_clk : std_logic;
-- Arbiter
constant ARB_MAX_MASTER : natural := 2;
signal arb_idx : natural range 0 to ARB_MAX_MASTER-1;
@@ -369,7 +370,7 @@ BEGIN
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
vga_ce <= not vga_rst;
sys_phy_gtx_clk <= gmii_clk;
sys_flash_ssram_out:
process(CLK_O)
begin
@@ -838,6 +839,21 @@ inst_clocken_vga : entity work.clockgen
clk_out => vga_clk
);
inst_clockgen_gmii : entity work.clockgen
GENERIC MAP
(
clk_in_freq => sys_freq_in,
clk_out_freq => 125.0
)
PORT MAP
(
-- Clocks and Reset
rst_in => rst_in,
clk_in => sys_clk_in,
rst_out => open,
clk_out => gmii_clk
);
inst_sdram_ctrl_wb64 : entity work.ctrl_ddr_wb64
GENERIC MAP
(
@@ -1022,7 +1038,7 @@ inst_emac_jb : entity work.emac_top_jb
mii_tx_en => sys_phy_tx_en,
mii_tx_er => sys_phy_tx_er,
mii_tx => sys_phy_tx,
mii_gtx_clk => sys_phy_gtx_clk,
mii_gtx_clk => gmii_clk,
mii_crs => sys_phy_crs,
mii_col => sys_phy_col
projects/mips_sys/src/tb_mips_sys.vhd
+9 -3
View File
@@ -139,7 +139,10 @@ ARCHITECTURE behavior OF tb_mips_sys IS
signal ac_left : unsigned(17 downto 0) := X"0000" & "00";
signal ac_right : unsigned(17 downto 0) := X"0000" & "01";
signal ac_synced : std_logic;
signal slv_flash_ssram_d : STD_LOGIC_VECTOR(sys_flash_ssram_d'left downto sys_flash_ssram_d'right);
signal slv_ssram_dp : STD_LOGIC_VECTOR(sys_ssram_dp'left downto sys_ssram_dp'right);
BEGIN
uut: entity work.mips_sys
@@ -243,11 +246,14 @@ uut: entity work.mips_sys
sys_phy_crs <= '0';
sys_phy_col <= '0';
slv_flash_ssram_d <= STD_LOGIC_VECTOR(sys_flash_ssram_d);
slv_ssram_dp <= STD_LOGIC_VECTOR(sys_ssram_dp);
inst_ssram : entity work.cy7c1354
PORT MAP
(
Dq => STD_LOGIC_VECTOR(sys_flash_ssram_d), -- Data I/O
Dpq => STD_LOGIC_VECTOR(sys_ssram_dp), -- Data I/O
Dq => slv_flash_ssram_d, -- Data I/O
Dpq => slv_ssram_dp, -- Data I/O
Addr => STD_LOGIC_VECTOR(sys_flash_ssram_a(18 downto 1)), -- Address
Mode => sys_ssram_mode, -- Burst Mode
Clk => sys_ssram_clk, -- Clk