diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd
index e526128..e07ef2a 100644
--- a/lib/misc/async_port_wb.vhd
+++ b/lib/misc/async_port_wb.vhd
@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.11 2009-10-30 13:51:00 Jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.12 2009-11-02 10:29:23 Jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -182,9 +182,7 @@ architecture Behavioral of async_port_wb is
 					cycle_reload	<= async_timespec.ncyc_pulse_page_rd-1;
 					sn				<= pulse;
 				elsif async_timespec.ncyc_leadout = 0 then
-					if en = '1' and (WE_I = WE_I_r) then
-						sn				<= idle;
-					elsif async_timespec.ncyc_release = 0 then
+					if async_timespec.ncyc_release = 0 then
 						sn				<= idle;
 					else
 						cycle_reload	<= async_timespec.ncyc_release-1;
@@ -198,11 +196,10 @@ architecture Behavioral of async_port_wb is
 				
 		when leadout =>
 			as.cs		<= '1';
+			as.drive_d	<= WE_I_r;
 			if cycle_cnt = 0 then
 				cc_rst			<= '1';
-				if en = '1' and (WE_I = WE_I_r) then
-					sn				<= idle;
-				elsif async_timespec.ncyc_release = 0 then
+				if async_timespec.ncyc_release = 0 then
 					sn				<= idle;
 				else
 					cycle_reload	<= async_timespec.ncyc_release-1;