diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
index f11b0ac..ec07fe6 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
@@ -84,6 +84,7 @@ architecture tech of sdram_phy is
 	signal read_en			: std_logic;
 	
 	signal clk0				: std_logic;
+	signal clk0_s			: std_logic;
 	signal rst0				: std_logic;
 	signal clk_rd			: std_logic;
 	signal clk_wr			: std_logic;
@@ -95,7 +96,8 @@ architecture tech of sdram_phy is
 	signal u_tag_pipe : u_tag_array_t;
 	
 begin
-	clk0_out	<= clk0;
+	clk0_out	<= clk0_s;
+	clk0		<= clk0_s after 10 ps;		-- fix delta delay
 	rst0_out	<= rst0;
 	
 ------------------------------------------------------------------------------------------------------------------------------------------------
@@ -112,7 +114,7 @@ inst_clockgen : entity work.clockgen
 		rst				=> rst,   -- external async reset, low active
 		clk_in			=> clk,   -- system clock (e.g. 100MHz), from board
 		clk_fb_in		=> clk_fb,   -- feedback clock
-		clk0_0_out		=> clk0,  -- System clock #0, dcm#0 output 0°
+		clk0_0_out		=> clk0_s,  -- System clock #0, dcm#0 output 0°
 		clk0_270_out	=> clk_wr,  -- System clock #0, dcm#0 output 270°
 		clk1_0_out		=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
 		clk1_270_out	=> clk_rd,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°