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- added AC-97 controller

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git-svn-id: http://moon:8086/svn/vhdl/trunk@132 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-11-01 21:47:15 +00:00
parent a41b5f572a
commit 755b318e7a
7 changed files with 188 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/ise101/mips_sys/mips_sys.prj
+7
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@@ -4,6 +4,7 @@ vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vhdl work "../../../../lib/misc/utils_pkg.vhd"
vhdl work "../../../../lib/misc/singleshot.vhd"
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
@@ -18,8 +19,11 @@ vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
vhdl work "../../../../lib/misc/dpram_1w1r_dist.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd"
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd"
vhdl work "../../src/sys_types.vhd"
vhdl work "../../src/ram_ld.vhd"
vhdl work "../../src/bootloader.ROM_ld.vhd"
@@ -28,7 +32,9 @@ vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
vhdl work "../../../../lib/uart/uart_tx.vhd"
vhdl work "../../../../lib/uart/uart_rx.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync_dist.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_io.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
vhdl work "../../../../lib/uart/uart_wb.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
@@ -39,4 +45,5 @@ vhdl work "../../../../lib/misc/gpio_wb.vhd"
vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
vhdl work "../../../../lib/misc/async_port_wb.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
vhdl work "../../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
vhdl work "../../src/mips_sys.vhd"
projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
+7
View File
@@ -4,6 +4,7 @@ vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
vhdl work "W:\vhdl\lib\misc\singleshot.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
@@ -18,8 +19,11 @@ vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd"
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
@@ -28,7 +32,9 @@ vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_dist.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_io.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
@@ -39,4 +45,5 @@ vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac97_wb.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
projects/mips_sys/sim/tb_mips_sys.fdo
+7
View File
@@ -86,6 +86,13 @@ vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
# AC-97
vcom -explicit -93 "../../../lib/misc/singleshot.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
# Top and TB
vcom -explicit -93 "../src/mips_sys_sim.vhd"
vcom -explicit -93 "../src/tb_mips_sys.vhd"
projects/mips_sys/sim/tb_mips_sys.wdo
+8 -4
View File
@@ -44,6 +44,10 @@ add wave -noupdate -divider Arbiter
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_in
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_out
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
add wave -noupdate -divider {CPU Master}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
@@ -124,6 +128,7 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s
add wave -noupdate -divider Flash
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
@@ -132,7 +137,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rstn
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n
@@ -299,8 +303,8 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_we
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {2419775464 ps} 0}
configure wave -namecolwidth 131
WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {5918510756 ps} 0}
configure wave -namecolwidth 187
configure wave -valuecolwidth 64
configure wave -justifyvalue left
configure wave -signalnamewidth 1
@@ -313,4 +317,4 @@ configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {4072824 ns}
WaveRestoreZoom {1454075947 ps} {11432056635 ps}
projects/mips_sys/src/mips_sys.vhd
+64 -13
View File
@@ -104,8 +104,14 @@ PORT
sys_flash_ce : out std_logic;
sys_flash_wrn : out std_logic;
sys_flash_rdn : out std_logic;
sys_flash_rstn : out std_logic;
sys_flash_ac97_rstn : out std_logic;
sys_flash_byten : out std_logic;
sys_ac97_sdata_in : in std_logic;
sys_ac97_bit_clk : in std_logic;
sys_ac97_sdata_out : out std_logic;
sys_ac97_ssync : out std_logic;
sys_error : out unsigned(1 downto 0) -- indicates Errors
);
@@ -320,6 +326,8 @@ ARCHITECTURE behavior OF mips_sys IS
signal locked : std_logic;
signal usb_addr : unsigned(31 downto 0);
signal flash_addr : unsigned(31 downto 0);
signal ac97_rstn : std_logic;
signal flash_rstn : std_logic;
-- Arbiter
constant ARB_MAX_MASTER : natural := 2;
@@ -406,6 +414,12 @@ ARCHITECTURE behavior OF mips_sys IS
signal SRDY_O_vga : std_logic;
signal SDAT_O_vga : unsigned(31 downto 0);
signal INT_O_ac97 : std_logic;
signal CYC_I_ac97 : std_logic;
signal ACK_O_ac97 : std_logic;
signal SRDY_O_ac97 : std_logic;
signal SDAT_O_ac97 : unsigned(31 downto 0);
signal gpo0 : unsigned(31 downto 0);
signal gpo1 : unsigned(31 downto 0);
signal gpi0 : unsigned(31 downto 0);
@@ -422,7 +436,7 @@ ARCHITECTURE behavior OF mips_sys IS
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga);
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
signal mem_area : mem_area_t;
BEGIN
@@ -441,6 +455,7 @@ BEGIN
SDAT_I_sdram <= MDAT_O & MDAT_O;
SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
---------------------------------------------------------------
-- Arbiter
MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
@@ -484,7 +499,7 @@ int_sample:
process(clk)
begin
if rising_edge(clk) then
int <= "000" & sys_usb_int & int_uart_rx & sys_btn(4);
int <= "00" & INT_O_ac97 & sys_usb_int & int_uart_rx & sys_btn(4);
end if;
end process;
@@ -496,18 +511,20 @@ mem_mux:
-- mem_area <= mem_flash;
if ADDR_O(31 downto 28) = X"A" then
if ADDR_O(27 downto 26) = "00" then
if ADDR_O(17 downto 16) = "00" then
if ADDR_O(18 downto 16) = "000" then
mem_area <= mem_gpio;
elsif ADDR_O(17 downto 16) = "01" then
elsif ADDR_O(18 downto 16) = "001" then
mem_area <= mem_uart;
elsif ADDR_O(17 downto 16) = "10" then
elsif ADDR_O(18 downto 16) = "010" then
mem_area <= mem_usb;
elsif ADDR_O(17 downto 16) = "11" then
elsif ADDR_O(18 downto 16) = "011" then
mem_area <= mem_vga;
elsif ADDR_O(18 downto 16) = "100" then
mem_area <= mem_ac97;
end if;
elsif ADDR_O(27 downto 26) = "01" then
mem_area <= mem_flash;
end if;
elsif ADDR_O(27 downto 26) = "01" then
mem_area <= mem_flash;
end if;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
mem_area <= mem_rom;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
@@ -529,6 +546,7 @@ signal_mux:
CYC_I_ram <= '0';
CYC_I_sdram <= '0';
CYC_I_vga <= '0';
CYC_I_ac97 <= '0';
case mem_area is
@@ -556,6 +574,9 @@ signal_mux:
when mem_vga =>
CYC_I_vga <= CYC_O;
when mem_ac97 =>
CYC_I_ac97 <= CYC_O;
when others => null;
end case;
@@ -563,8 +584,8 @@ signal_mux:
end process;
------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga;
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_ram when CYC_I_ram = '1' else
SDAT_O_rom when CYC_I_rom = '1' else
@@ -572,6 +593,7 @@ signal_mux:
SDAT_O_usb when CYC_I_usb = '1' else
SDAT_O_uart when CYC_I_uart = '1' else
SDAT_O_vga when CYC_I_vga = '1' else
SDAT_O_ac97 when CYC_I_ac97 = '1' else
SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
------------------------------------------------------------------
@@ -687,7 +709,7 @@ inst_flash_port : async_port_wb
async_cs => sys_flash_ce,
async_wr => sys_flash_wrn,
async_rd => sys_flash_rdn,
async_rst => sys_flash_rstn
async_rst => flash_rstn
);
inst_usb_port : async_port_wb
@@ -851,5 +873,34 @@ inst_vga_frontend : vga_frontend64
vga_vsync => sys_vga_vsync
);
inst_ac97_wb : entity work.ac97_wb
GENERIC MAP
(
fifo_depth => 4
)
PORT MAP
(
-- J-Bus domain
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_ac97,
STB_I => STB_O,
WE_I => WE_O,
ACK_O => ACK_O_ac97,
SRDY_O => SRDY_O_ac97,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_ac97,
INT_O => INT_O_ac97,
-- AC97 domain
ac97_sdata_in => sys_ac97_sdata_in,
ac97_bit_clk => sys_ac97_bit_clk,
ac97_reset_n => ac97_rstn,
ac97_sdata_out => sys_ac97_sdata_out,
ac97_ssync => sys_ac97_ssync
);
------------------------------------------------------------------
END;
projects/mips_sys/src/mips_sys_sim.vhd
+67 -17
View File
@@ -104,7 +104,7 @@ PORT
sys_flash_ce : out std_logic;
sys_flash_ssram_we_n : out std_logic;
sys_flash_ssram_oe_n : out std_logic;
sys_flash_rstn : out std_logic;
sys_flash_ac97_rstn : out std_logic;
sys_flash_byten : out std_logic;
sys_ssram_clk : out std_logic;
@@ -116,7 +116,12 @@ PORT
sys_ssram_adv : out std_logic;
sys_ssram_mode : out std_logic;
sys_ssram_zz : out std_logic;
sys_ac97_sdata_in : in std_logic;
sys_ac97_bit_clk : in std_logic;
sys_ac97_sdata_out : out std_logic;
sys_ac97_ssync : out std_logic;
sys_error : out unsigned(1 downto 0) -- indicates Errors
);
@@ -362,6 +367,8 @@ ARCHITECTURE behavior OF mips_sys IS
signal rst_in : std_logic;
signal int_uart_rx : std_logic;
signal locked : std_logic;
signal ac97_rstn : std_logic;
signal flash_rstn : std_logic;
signal ADDR_I_usb : unsigned(31 downto 0);
signal ADDR_I_flash : unsigned(31 downto 0);
signal ADDR_I_ssram : unsigned(31 downto 0);
@@ -469,6 +476,12 @@ ARCHITECTURE behavior OF mips_sys IS
signal SRDY_O_ssram : std_logic;
signal SDAT_O_ssram : unsigned(31 downto 0);
signal INT_O_ac97 : std_logic;
signal CYC_I_ac97 : std_logic;
signal ACK_O_ac97 : std_logic;
signal SRDY_O_ac97 : std_logic;
signal SDAT_O_ac97 : unsigned(31 downto 0);
signal gpo0 : unsigned(31 downto 0);
signal gpo1 : unsigned(31 downto 0);
signal gpi0 : unsigned(31 downto 0);
@@ -486,7 +499,7 @@ ARCHITECTURE behavior OF mips_sys IS
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga);
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
signal mem_area : mem_area_t;
BEGIN
@@ -505,7 +518,8 @@ BEGIN
SDAT_I_sdram <= MDAT_O & MDAT_O;
SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
sys_flash_ssram_out:
process(clk)
@@ -575,7 +589,7 @@ int_sample:
process(clk)
begin
if rising_edge(clk) then
int <= "000" & sys_usb_int & int_uart_rx & sys_btn(4);
int <= "00" & INT_O_ac97 & sys_usb_int & int_uart_rx & sys_btn(4);
end if;
end process;
@@ -587,15 +601,17 @@ mem_mux:
mem_area <= mem_flash;
elsif ADDR_O(31 downto 28) = X"A" then
if ADDR_O(27 downto 26) = "00" then
if ADDR_O(17 downto 16) = "00" then
mem_area <= mem_gpio;
elsif ADDR_O(17 downto 16) = "01" then
mem_area <= mem_uart;
elsif ADDR_O(17 downto 16) = "10" then
mem_area <= mem_usb;
elsif ADDR_O(17 downto 16) = "11" then
mem_area <= mem_vga;
end if;
if ADDR_O(18 downto 16) = "000" then
mem_area <= mem_gpio;
elsif ADDR_O(18 downto 16) = "001" then
mem_area <= mem_uart;
elsif ADDR_O(18 downto 16) = "010" then
mem_area <= mem_usb;
elsif ADDR_O(18 downto 16) = "011" then
mem_area <= mem_vga;
elsif ADDR_O(18 downto 16) = "100" then
mem_area <= mem_ac97;
end if;
elsif ADDR_O(27 downto 26) = "01" then
mem_area <= mem_flash;
elsif ADDR_O(27 downto 26) = "10" then
@@ -624,6 +640,7 @@ signal_mux:
CYC_I_sdram <= '0';
CYC_I_vga <= '0';
CYC_I_ssram <= '0';
CYC_I_ac97 <= '0';
case mem_area is
@@ -651,6 +668,9 @@ signal_mux:
when mem_vga =>
CYC_I_vga <= CYC_O;
when mem_ac97 =>
CYC_I_ac97 <= CYC_O;
when mem_ssram =>
CYC_I_ssram <= CYC_O;
@@ -661,8 +681,8 @@ signal_mux:
end process;
------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga;
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else
SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_ram when CYC_I_ram = '1' else
@@ -671,6 +691,7 @@ signal_mux:
SDAT_O_usb when CYC_I_usb = '1' else
SDAT_O_uart when CYC_I_uart = '1' else
SDAT_O_vga when CYC_I_vga = '1' else
SDAT_O_ac97 when CYC_I_ac97 = '1' else
SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
------------------------------------------------------------------
@@ -790,7 +811,7 @@ inst_flash_port : flash_port_wb
port_wr => flash_we_n,
port_rd => flash_oe_n,
flash_cs => sys_flash_ce,
flash_rst => sys_flash_rstn
flash_rst => flash_rstn
);
inst_usb_port : async_port_wb
@@ -996,5 +1017,34 @@ inst_vga_frontend : vga_frontend64
vga_vsync => sys_vga_vsync
);
inst_ac97_wb : entity work.ac97_wb
GENERIC MAP
(
fifo_depth => 4
)
PORT MAP
(
-- J-Bus domain
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_ac97,
STB_I => STB_O,
WE_I => WE_O,
ACK_O => ACK_O_ac97,
SRDY_O => SRDY_O_ac97,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_ac97,
INT_O => INT_O_ac97,
-- AC97 domain
ac97_sdata_in => sys_ac97_sdata_in,
ac97_bit_clk => sys_ac97_bit_clk,
ac97_reset_n => ac97_rstn,
ac97_sdata_out => sys_ac97_sdata_out,
ac97_ssync => sys_ac97_ssync
);
------------------------------------------------------------------
END;
projects/mips_sys/src/tb_mips_sys.vhd
+28 -4
View File
@@ -37,7 +37,8 @@ END tb_mips_sys;
ARCHITECTURE behavior OF tb_mips_sys IS
constant CLK_PERIOD : time := 10 ns;
constant CLK_PERIOD : time := 10 ns;
constant AC97_CLK_PERIOD : time := 100 ns;
signal sys_rst_n_in : std_logic := '0';
signal sys_clk_in : std_logic := '1';
signal dip : unsigned(7 downto 0) := (others => '0');
@@ -83,7 +84,7 @@ ARCHITECTURE behavior OF tb_mips_sys IS
signal sys_flash_ssram_oe_n : std_logic;
signal sys_flash_ce : std_logic;
signal sys_flash_rstn : std_logic;
signal sys_flash_ac97_rstn : std_logic;
signal sys_flash_byten : std_logic;
signal sys_ssram_clk_fb : std_logic;
@@ -96,6 +97,11 @@ ARCHITECTURE behavior OF tb_mips_sys IS
signal sys_ssram_mode : std_logic;
signal sys_ssram_zz : std_logic;
SIGNAL sys_ac97_bit_clk : std_logic := '0';
SIGNAL sys_ac97_sdata_out : std_logic;
SIGNAL sys_ac97_ssync : std_logic;
SIGNAL sys_ac97_sdata_in : std_logic;
signal flash_reg : word_t;
type flash_data_t is array (natural range 0 to 2**16-1) of word_t;
@@ -152,7 +158,7 @@ uut: entity work.mips_sys
sys_flash_ssram_we_n => sys_flash_ssram_we_n,
sys_flash_ssram_oe_n => sys_flash_ssram_oe_n,
sys_flash_ce => sys_flash_ce,
sys_flash_rstn => sys_flash_rstn,
sys_flash_ac97_rstn => sys_flash_ac97_rstn,
sys_flash_byten => sys_flash_byten,
sys_ssram_clk_fb => sys_ssram_clk_fb,
@@ -165,6 +171,11 @@ uut: entity work.mips_sys
sys_ssram_mode => sys_ssram_mode,
sys_ssram_zz => sys_ssram_zz,
sys_ac97_bit_clk => sys_ac97_bit_clk,
sys_ac97_sdata_out => sys_ac97_sdata_out,
sys_ac97_ssync => sys_ac97_ssync,
sys_ac97_sdata_in => sys_ac97_sdata_in,
sys_error => sys_error
);
@@ -237,9 +248,22 @@ CLK_GEN: process
sys_clk_in <= not sys_clk_in;
end process;
sys_ac97_sdata_in <= '1'; --sys_ac97_sdata_out;
ac97_clk_gen : PROCESS
begin
if (sys_flash_ac97_rstn = '0') then
sys_ac97_bit_clk <= '0';
wait until sys_flash_ac97_rstn = '1';
wait for 150 us;
end if;
wait for AC97_CLK_PERIOD/2;
sys_ac97_bit_clk <= not sys_ac97_bit_clk;
END PROCESS;
FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a)
type file_t is file of integer;
file load_flash : file_t open read_mode is "test_bui.flash.bin";
file load_flash : file_t open read_mode is "test_ac97.flash.bin";
variable instr : integer;
variable index : natural;
variable temp : signed(31 downto 0);