diff --git a/lib/filter/src/delay_line.vhd b/lib/filter/src/delay_line.vhd
index 9a2e704..a05e317 100644
--- a/lib/filter/src/delay_line.vhd
+++ b/lib/filter/src/delay_line.vhd
@@ -42,7 +42,6 @@ Port
 (
 	rst			: in std_logic;
 	clk			: in std_logic;
-	ce			: in std_logic;
 	shift_en	: in std_logic;
 	delay		: in natural range 0 to ntaps-1;
 	din			: in sfixed;
@@ -74,13 +73,11 @@ counter:
 		if rising_edge(clk) then
 			if rst = '1' then
 				count <= 0;
-			elsif ce = '1' then
-				if shift_en = '1' then
-					if count /= ntaps-1 then
-						count <= count + 1;
-					else
-						count <= 0;
-					end if;
+			elsif shift_en = '1' then
+				if count /= ntaps-1 then
+					count <= count + 1;
+				else
+					count <= 0;
 				end if;
 			end if;
 		end if;
@@ -95,8 +92,8 @@ counter:
 	PORT MAP (
 		clka	=> clk,
 		clkb	=> clk,
-		en_a	=> ce,
-		en_b	=> ce,
+		en_a	=> '1',
+		en_b	=> '1',
 		we_a	=> shift_en,
 		addr_a	=> addr_w,
 		addr_b	=> addr_r,
@@ -121,11 +118,9 @@ shift_register:
 	variable delay_pipe	: delay_pipe_t;
 	begin
 		if rising_edge(clk) then
-			if ce = '1' then
-				dout			<= delay_pipe(delay);
-				if shift_en = '1' then
-					delay_pipe		:= delay_pipe(delay_pipe'left-1 downto 0) & din;
-				end if;
+			dout			<= delay_pipe(delay);
+			if shift_en = '1' then
+				delay_pipe		:= delay_pipe(delay_pipe'left-1 downto 0) & din;
 			end if;
 		end if;
 	end process;