diff --git a/projects/mips_sys/src/tb_mips_sys.vhd b/projects/mips_sys/src/tb_mips_sys.vhd
index 9186a3d..610db8f 100644
--- a/projects/mips_sys/src/tb_mips_sys.vhd
+++ b/projects/mips_sys/src/tb_mips_sys.vhd
@@ -38,7 +38,7 @@ END tb_mips_sys;
 ARCHITECTURE behavior OF tb_mips_sys IS 
 
 	constant CLK_PERIOD			: time := 10 ns;
-	constant AC97_CLK_PERIOD	: time := 100 ns;
+	constant AC97_CLK_PERIOD	: time := 83 ns;
 	signal sys_rst_n_in : std_logic := '0';
 	signal sys_clk_in : std_logic := '1';
 	signal dip  : unsigned(7 downto 0) := (others => '0');
@@ -106,6 +106,11 @@ ARCHITECTURE behavior OF tb_mips_sys IS
 
 	type flash_data_t is array (natural range 0 to 2**16-1) of word_t;
 	signal flash_data : flash_data_t;
+
+	signal	ac_frame_reg		: unsigned(255 downto 0) := (others => '0');
+	signal	ac_left				: unsigned(17 downto 0) := X"0000" & "00";
+	signal	ac_right			: unsigned(17 downto 0) := X"0000" & "01";
+	signal  ac_synced			:  std_logic;
 	
 BEGIN
 
@@ -248,7 +253,28 @@ CLK_GEN: process
 		sys_clk_in <= not sys_clk_in;
 	end process;
 
-	sys_ac97_sdata_in <= '1'; --sys_ac97_sdata_out;
+
+	sys_ac97_sdata_in <= ac_frame_reg(ac_frame_reg'left); --sys_ac97_sdata_out;
+
+ac97_data_gen :
+	PROCESS(sys_ac97_bit_clk)
+	begin
+		if rising_edge(sys_ac97_bit_clk) then
+			ac_frame_reg <= ac_frame_reg(ac_frame_reg'left-1 downto 0) & '0';
+			if sys_flash_ac97_rstn = '0' then
+				ac_synced	<= '0';
+			elsif sys_ac97_ssync = '1' then
+				if ac_synced = '0' then
+					ac_frame_reg <= X"F800_00000_00000" & ac_left & "00" & ac_right & "00" & X"00000_00000_00000_00000_00000_00000_00000_00000";
+					ac_left <= ac_left + 2;
+					ac_right <= ac_right + 2;
+					ac_synced	<= '1';
+				end if;	
+			else	
+				ac_synced	<= '0';
+			end if;
+		end if;	
+	END PROCESS;
 
 ac97_clk_gen : PROCESS
 	begin