- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1423 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 11:31:55 +00:00
parent 5309734167
commit 73cfd45401
59 changed files with 16220 additions and 0 deletions
@@ -0,0 +1 @@
+work
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+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_gf_2exp8_arith.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_definitions.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/tech_iface_virtex2.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_row_ops.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_column_ops.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/engine_iface.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_common.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/key_schedule_iface.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/dual_sbox_virtex2.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/aux_funcs.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/CBC_128/cbc_mode_iface.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_encryption.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/tech_subkey_memory_virtex2.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/tech_sbox_stage_virtex2.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/key_schedule_128.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/encryption_engine.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/CBC_128/cbc_mode_encryption.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/CBC_128/cbc_core_iface.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/CBC_128/cbc_128_encryption_core.vhd"
@@ -0,0 +1,55 @@
+set -tmpdir ./xst/projnav.tmp
+set -xsthdpdir ./xst
+run
+-ifn cbc_128_encryption_core.prj
+-ifmt mixed
+-ofn cbc_128_encryption_core
+-ofmt NGC
+-p xc4vsx35-10-ff668
+-top cbc_128_encryption_core
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso cbc_128_encryption_core.lso
+-keep_hierarchy NO
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-dsp_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-mux_extract YES
+-resource_sharing YES
+-use_dsp48 auto
+-iobuf NO
+-max_fanout 500
+-bufg 32
+-bufr 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
@@ -0,0 +1 @@
+work
@@ -0,0 +1,19 @@
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_gf_2exp8_arith.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_definitions.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/tech_iface_virtex2.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_row_ops.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_column_ops.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/engine_iface.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_common.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/key_schedule_iface.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/dual_sbox_virtex2.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/aux_funcs.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/ECB_128/ecb_mode_iface.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_encryption.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/tech_subkey_memory_virtex2.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/tech_sbox_stage_virtex2.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/key_schedule_128.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/encryption_engine.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/ECB_128/ecb_mode_encryption.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/ECB_128/ecb_core_iface.vhd"
+vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/ECB_128/ecb_128_encryption_core.vhd"
@@ -0,0 +1,55 @@
+set -tmpdir ./xst/projnav.tmp
+set -xsthdpdir ./xst
+run
+-ifn ecb_128_encryption_core.prj
+-ifmt mixed
+-ofn ecb_128_encryption_core
+-ofmt NGC
+-p xc4vsx35-10-ff668
+-top ecb_128_encryption_core
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso ecb_128_encryption_core.lso
+-keep_hierarchy NO
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-dsp_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-mux_extract YES
+-resource_sharing YES
+-use_dsp48 auto
+-iobuf NO
+-max_fanout 500
+-bufg 32
+-bufr 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5