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git-svn-id: http://moon:8086/svn/vhdl/trunk@1423 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-21 11:31:55 +00:00
parent 5309734167
commit 73cfd45401
59 changed files with 16220 additions and 0 deletions
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projects/messe_demo/syn/ise81/aes_cbc/cbc_128_encryption_core.lso
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work
projects/messe_demo/syn/ise81/aes_cbc/cbc_128_encryption_core.prj
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vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_gf_2exp8_arith.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_definitions.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/tech_iface_virtex2.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_row_ops.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_column_ops.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/engine_iface.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_common.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/key_schedule_iface.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/dual_sbox_virtex2.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/aux_funcs.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/CBC_128/cbc_mode_iface.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_encryption.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/tech_subkey_memory_virtex2.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/tech_sbox_stage_virtex2.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/key_schedule_128.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/encryption_engine.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/CBC_128/cbc_mode_encryption.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/CBC_128/cbc_core_iface.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/CBC_128/cbc_128_encryption_core.vhd"
projects/messe_demo/syn/ise81/aes_cbc/cbc_128_encryption_core.xst
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set -tmpdir ./xst/projnav.tmp
set -xsthdpdir ./xst
run
-ifn cbc_128_encryption_core.prj
-ifmt mixed
-ofn cbc_128_encryption_core
-ofmt NGC
-p xc4vsx35-10-ff668
-top cbc_128_encryption_core
-opt_mode Speed
-opt_level 1
-iuc NO
-lso cbc_128_encryption_core.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-mux_extract YES
-resource_sharing YES
-use_dsp48 auto
-iobuf NO
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/messe_demo/syn/ise81/aes_ecb/ecb_128_encryption_core.lso
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work
projects/messe_demo/syn/ise81/aes_ecb/ecb_128_encryption_core.prj
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vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_gf_2exp8_arith.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_definitions.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/tech_iface_virtex2.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_row_ops.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_column_ops.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/engine_iface.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_common.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/key_schedule_iface.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/dual_sbox_virtex2.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/aux_funcs.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/ECB_128/ecb_mode_iface.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/aes_encryption.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/tech_subkey_memory_virtex2.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/tech_sbox_stage_virtex2.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/key_schedule_128.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/encryption_engine.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/ECB_128/ecb_mode_encryption.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/ECB_128/ecb_core_iface.vhd"
vhdl work "W:/vhdl/projects/messe_demo/src/AES_32bit_datapath/enc/ECB_128/ecb_128_encryption_core.vhd"
projects/messe_demo/syn/ise81/aes_ecb/ecb_128_encryption_core.xst
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set -tmpdir ./xst/projnav.tmp
set -xsthdpdir ./xst
run
-ifn ecb_128_encryption_core.prj
-ifmt mixed
-ofn ecb_128_encryption_core
-ofmt NGC
-p xc4vsx35-10-ff668
-top ecb_128_encryption_core
-opt_mode Speed
-opt_level 1
-iuc NO
-lso ecb_128_encryption_core.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-mux_extract YES
-resource_sharing YES
-use_dsp48 auto
-iobuf NO
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/messe_demo/syn/ise91/project/messe_demo.lso
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work
projects/messe_demo/syn/ise91/project/messe_demo.prj
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vhdl work "../src/AES_32bit_datapath/aes_definitions.vhd"
vhdl work "../src/cpu_pkg.vhd"
vhdl work "../src/AES_32bit_datapath/enc/tech_iface_virtex2.vhd"
vhdl work "../src/ac97_ctrl/singleshot.vhd"
vhdl work "../src/AES_32bit_datapath/enc/engine_iface.vhd"
vhdl work "../src/test_irom_ld.vhdl"
vhdl work "../src/ac97_ctrl/ac_out.vhd"
vhdl work "../src/ac97_ctrl/ac_in.vhd"
vhdl work "../src/AES_32bit_datapath/enc/key_schedule_iface.vhd"
vhdl work "../src/AES_32bit_datapath/enc/ECB_128/ecb_mode_iface.vhd"
vhdl work "../src/AES_32bit_datapath/enc/CBC_128/cbc_mode_iface.vhd"
vhdl work "../src/test_xrom_ld.vhdl"
vhdl work "../src/lcd_port.vhd"
vhdl work "../src/cpu_embedded.vhd"
vhdl work "../src/ac97_ctrl/ac_io.vhd"
vhdl work "../src/AES_32bit_datapath/enc/ECB_128/ecb_core_iface.vhd"
vhdl work "../src/AES_32bit_datapath/enc/CBC_128/cbc_core_iface.vhd"
vhdl work "../src/demo_top.vhd"
projects/messe_demo/syn/ise91/project/messe_demo.ut
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-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g ConfigRate:4
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g InitPin:Pullup
-g CsPin:Pullup
-g DinPin:Pullup
-g BusyPin:Pullup
-g RdWrPin:Pullup
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g DCIUpdateMode:AsRequired
-g StartUpClk:JtagClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Match_cycle:Auto
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g Encrypt:No
projects/messe_demo/syn/ise91/project/messe_demo.xst
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set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn messe_demo.prj
-ifmt mixed
-ofn messe_demo
-ofmt NGC
-p xc4vfx12-10-ff668
-top messe_demo
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso messe_demo.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract NO
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 16
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/messe_demo/syn/ise91/project/messe_demo_vhdl.prj
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vhdl work "W:\vhdl\projects\messe_demo\src\AES_32bit_datapath\aes_definitions.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\cpu_pkg.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\AES_32bit_datapath\enc\tech_iface_virtex2.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\ac97_ctrl\singleshot.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\AES_32bit_datapath\enc\engine_iface.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\test_irom_ld.vhdl"
vhdl work "W:\vhdl\projects\messe_demo\src\ac97_ctrl\ac_out.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\ac97_ctrl\ac_in.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\AES_32bit_datapath\enc\key_schedule_iface.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\AES_32bit_datapath\enc\ECB_128\ecb_mode_iface.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\AES_32bit_datapath\enc\CBC_128\cbc_mode_iface.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\test_xrom_ld.vhdl"
vhdl work "W:\vhdl\projects\messe_demo\src\lcd_port.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\cpu_embedded.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\ac97_ctrl\ac_io.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\AES_32bit_datapath\enc\ECB_128\ecb_core_iface.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\AES_32bit_datapath\enc\CBC_128\cbc_core_iface.vhd"
vhdl work "W:\vhdl\projects\messe_demo\src\demo_top.vhd"
projects/messe_demo/syn/ise91/project/ml402.ucf
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#CONFIG STEPPING="ES";
# Bus clock nets
NET "sys_clk_in" TNM_NET = "sys_clk";
NET "ac97_bit_clk" TNM_NET = "ac97_clk";
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
TIMESPEC "TSBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %;
NET sys_clk_in LOC = AE14;
NET sys_clk_in IOSTANDARD = LVCMOS33;
NET sys_rst_n_in LOC = D6;
NET sys_rst_n_in PULLUP;
NET sys_rst_n_in TIG;
////////////////////////////////////////////////////////////////////////////
// AC97 Sound Controller
////////////////////////////////////////////////////////////////////////////
NET ac97_bit_clk LOC = AE10;
NET ac97_bit_clk IOSTANDARD = LVCMOS33;
NET ac97_bit_clk PERIOD = 80;
NET ac97_sdata_in LOC = AD16;
NET ac97_sdata_in IOSTANDARD = LVCMOS33;
NET ac97_reset_n LOC = AD10;
NET ac97_reset_n IOSTANDARD = LVCMOS33;
NET ac97_reset_n TIG;
NET ac97_reset_n SLEW = SLOW;
NET ac97_sdata_out LOC = C8;
NET ac97_sdata_out SLEW = FAST;
NET ac97_sync LOC = D9;
NET ac97_sync SLEW = FAST;
////////////////////////////////////////////////////////////////////////////
// RS-232
////////////////////////////////////////////////////////////////////////////
NET sys_rx LOC = W2;
NET sys_rx IOSTANDARD = LVCMOS33;
NET sys_rx TIG;
NET "sys_tx" LOC = "W1";
NET sys_tx IOSTANDARD = LVCMOS33;
NET "sys_tx" TIG;
////////////////////////////////////////////////////////////////////////////
// Buttons, LEDs, and DIP Switches
////////////////////////////////////////////////////////////////////////////
# GPLED 0-3
NET "sys_led<0>" LOC = "G5"; #GPLED0
NET "sys_led<1>" LOC = "G6"; #GPLED1
NET "sys_led<2>" LOC = "A11"; #GPLED2
NET "sys_led<3>" LOC = "A12"; #GPLED3
# North-East-South-West-Center LEDs
NET "sys_led<4>" LOC = "F9"; # W LED
NET "sys_led<5>" LOC = "E2"; # N LED
NET "sys_led<6>" LOC = "E10"; # E LED
NET "sys_led<7>" LOC = "A5"; # S LED
NET "sys_led<8>" LOC = "C6"; # C LED
NET "sys_led<*>" TIG;
NET "sys_led<*>" SLEW = SLOW;
NET "sys_led<*>" DRIVE = 2;
NET "sys_led<*>" TIG;
# North-East-South-West-Center Buttons
NET "sys_btn<0>" LOC = "E9"; # W Button
NET "sys_btn<1>" LOC = "E7"; # N Button
NET "sys_btn<2>" LOC = "F10"; # E Button
NET "sys_btn<3>" LOC = "A6"; # S Button
NET "sys_btn<4>" LOC = "B6"; # C Button
NET "sys_btn<*>" TIG;
# Dip Switches 1-8
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
NET "sys_dip<*>" TIG;
////////////////////////////////////////////////////////////////////////////
// LCD
////////////////////////////////////////////////////////////////////////////
NET sys_lcd_e LOC = AE13; # LCD_E
NET sys_lcd_e IOSTANDARD = LVCMOS33;
NET sys_lcd_e TIG;
NET sys_lcd_rs LOC = AC17; # LCD_RS
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
NET sys_lcd_rs TIG;
NET sys_lcd_rw LOC = AB17; # LCD_RW
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
NET sys_lcd_rw TIG;
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
NET sys_lcd_d<*> TIG;
NET sys_lcd_d<*> PULLDOWN;
projects/messe_demo/syn/ise91/project/ml403.ucf
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#CONFIG STEPPING="ES";
# Bus clock nets
NET "sys_clk_in" TNM_NET = "sys_clk";
NET "ac97_bit_clk" TNM_NET = "ac97_clk";
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
TIMESPEC "TSBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %;
NET sys_clk_in LOC = AE14;
NET sys_clk_in IOSTANDARD = LVCMOS33;
NET sys_rst_n_in LOC = D6;
NET sys_rst_n_in PULLUP;
NET sys_rst_n_in TIG;
////////////////////////////////////////////////////////////////////////////
// AC97 Sound Controller
////////////////////////////////////////////////////////////////////////////
NET ac97_bit_clk LOC = AE10;
NET ac97_bit_clk IOSTANDARD = LVCMOS33;
NET ac97_bit_clk PERIOD = 80;
NET ac97_sdata_in LOC = AD16;
NET ac97_sdata_in IOSTANDARD = LVCMOS33;
NET ac97_reset_n LOC = AD10;
NET ac97_reset_n IOSTANDARD = LVCMOS33;
NET ac97_reset_n TIG;
NET ac97_reset_n SLEW = SLOW;
NET ac97_sdata_out LOC = C8;
NET ac97_sdata_out SLEW = FAST;
NET ac97_sync LOC = D9;
NET ac97_sync SLEW = FAST;
////////////////////////////////////////////////////////////////////////////
// RS-232
////////////////////////////////////////////////////////////////////////////
NET sys_rx LOC = W2;
NET sys_rx IOSTANDARD = LVCMOS33;
NET sys_rx TIG;
NET "sys_tx" LOC = "W1";
NET sys_tx IOSTANDARD = LVCMOS33;
NET "sys_tx" TIG;
////////////////////////////////////////////////////////////////////////////
// Buttons, LEDs, and DIP Switches
////////////////////////////////////////////////////////////////////////////
# GPLED 0-3
NET "sys_led<0>" LOC = "G5"; #GPLED0
NET "sys_led<1>" LOC = "G6"; #GPLED1
NET "sys_led<2>" LOC = "A11"; #GPLED2
NET "sys_led<3>" LOC = "A12"; #GPLED3
# North-East-South-West-Center LEDs
NET "sys_led<4>" LOC = "F9"; # W LED
NET "sys_led<5>" LOC = "E2"; # N LED
NET "sys_led<6>" LOC = "E10"; # E LED
NET "sys_led<7>" LOC = "A5"; # S LED
NET "sys_led<8>" LOC = "C6"; # C LED
NET "sys_led<*>" TIG;
NET "sys_led<*>" SLEW = SLOW;
NET "sys_led<*>" DRIVE = 2;
NET "sys_led<*>" TIG;
# North-East-South-West-Center Buttons
NET "sys_btn<0>" LOC = "E9"; # W Button
NET "sys_btn<1>" LOC = "E7"; # N Button
NET "sys_btn<2>" LOC = "F10"; # E Button
NET "sys_btn<3>" LOC = "A6"; # S Button
NET "sys_btn<4>" LOC = "B6"; # C Button
NET "sys_btn<*>" TIG;
# Dip Switches 1-8
#NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
#NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
#NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
#NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
#NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
#NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
#NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
#NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
#NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
#NET "sys_dip<*>" TIG;
////////////////////////////////////////////////////////////////////////////
// LCD
////////////////////////////////////////////////////////////////////////////
NET sys_lcd_e LOC = AE13; # LCD_E
NET sys_lcd_e IOSTANDARD = LVCMOS33;
NET sys_lcd_e TIG;
NET sys_lcd_rs LOC = AC17; # LCD_RS
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
NET sys_lcd_rs TIG;
NET sys_lcd_rw LOC = AB17; # LCD_RW
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
NET sys_lcd_rw TIG;
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
NET sys_lcd_d<*> TIG;
NET sys_lcd_d<*> PULLDOWN;