- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1423 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,309 @@
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 08:27:43 08/26/2006
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-- Design Name:
|
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-- Module Name: ac_out - Behavioral
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-- Project Name:
|
||||
-- Target Devices:
|
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-- Tool versions:
|
||||
-- Description:
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--
|
||||
-- Dependencies:
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||||
--
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||||
-- Revision:
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||||
-- Revision 0.01 - File Created
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-- Additional Comments:
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||||
--
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||||
----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ac_in is
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Port (
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rst : in std_logic;
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clk : in std_logic;
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sync_frame : out std_logic;
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sync_status : out std_logic;
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slot_valid : out unsigned(0 to 12);
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stat_addr : out unsigned (19 downto 0);
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stat_data : out unsigned (19 downto 0);
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pcm_out_addr : in unsigned (3 downto 0);
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pcm_out_data : out unsigned (19 downto 0);
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ac_reset : in std_logic;
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ac_bit_clk : in std_logic;
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ac_sdata_in : in std_logic;
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ac_ssync : in std_logic
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);
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end ac_in;
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architecture Behavioral of ac_in is
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------------------------------------------------------------------
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COMPONENT singleshot
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GENERIC (mode : integer);
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PORT(
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rst : IN std_logic;
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clk : IN std_logic;
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input : IN std_logic;
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output : OUT std_logic
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);
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END COMPONENT;
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------------------------------------------------------------------
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type sac_t is (ac_idle, ac_tag, ac_data);
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subtype bitcnt_t is integer range 0 to 19;
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subtype slotcnt_t is integer range 0 to 12;
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subtype slot_valid_t is UNSIGNED(0 to 12);
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subtype tag_t is UNSIGNED(15 downto 0);
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subtype slot_t is UNSIGNED(19 downto 0);
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type slot_array_t is array (natural range <>) of slot_t;
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signal data_array : slot_array_t (1 to 12);
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signal tag : tag_t;
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signal sac, snac : sac_t;
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signal bitcnt : bitcnt_t;
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signal bitcnt_rst, bitcnt_en : STD_LOGIC;
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signal slotcnt : slotcnt_t;
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signal slotcnt_rst, slotcnt_en : STD_LOGIC;
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signal rx_reg : slot_t;
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signal stat_read, host_update : STD_LOGIC;
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signal sync_end, slot_end, last_slot, start_of_frame : STD_LOGIC;
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------------------------------------------------------------------
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function GetSlotValid(data : tag_t) return slot_valid_t is
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variable res : slot_valid_t := (others => '0');
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begin
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res := (others => '0');
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for i in slot_valid_t'range loop
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res(i) := data(data'left-i);
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end loop;
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return res;
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end GetSlotValid;
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------------------------------------------------------------------
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begin
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-------------------------------------------------------------
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-- proc_status_flags
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-------------------------------------------------------------
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proc_status_flags:
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process (rst, clk, host_update, tag, data_array)
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begin
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if rising_edge(clk) then
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sync_status <= '0';
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if rst = '1' then
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slot_valid <= (others => '0');
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stat_addr <= (others => '0');
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stat_data <= (others => '0');
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elsif host_update = '1' then
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sync_status <= '1';
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slot_valid <= GetSlotValid(tag);
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stat_addr <= data_array(1);
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stat_data <= data_array(2);
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end if;
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end if;
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end process;
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-------------------------------------------------------------
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-- proc_pcm_data
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-------------------------------------------------------------
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proc_pcm_data:
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process (clk, pcm_out_addr, data_array)
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variable slot_id : integer range 0 to 12;
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begin
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pcm_out_data <= (others => '-');
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slot_id := to_integer(pcm_out_addr);
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if (slot_id > 2) then
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pcm_out_data <= data_array(slot_id);
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end if;
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end process;
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-------------------------------------------------------------
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-- proc_read_data
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-------------------------------------------------------------
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proc_read_data :
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process (ac_reset, ac_bit_clk, slot_end, slotcnt)
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begin
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if ac_reset = '1' then
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stat_read <= '0';
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elsif rising_edge(ac_bit_clk) then
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stat_read <= '0';
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if slot_end = '1' and slotcnt /= 0 then
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data_array(slotcnt) <= rx_reg;
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if slotcnt = 2 then
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stat_read <= '1';
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end if;
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end if;
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end if;
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end process;
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-------------------------------------------------------------
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-- proc_read_stat
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-------------------------------------------------------------
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proc_read_tag :
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process (ac_reset, ac_bit_clk, sync_end)
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begin
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if ac_reset = '1' then
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tag <= (others => '0');
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elsif rising_edge(ac_bit_clk) then
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if sync_end = '1' then
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tag <= rx_reg(15 downto 0);
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end if;
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end if;
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end process;
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-------------------------------------------------------------
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-- proc_slot_count
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-------------------------------------------------------------
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proc_slot_count:
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process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt)
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begin
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if rising_edge(ac_bit_clk) then
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if slotcnt_rst = '1' then
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slotcnt <= slotcnt_t'low;
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elsif slotcnt_en = '1' then
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if slotcnt /= slotcnt_t'high then
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slotcnt <= slotcnt + 1;
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else
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slotcnt <= slotcnt_t'low;
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end if;
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end if;
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end if;
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end process;
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-------------------------------------------------------------
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-- proc_bit_count
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-------------------------------------------------------------
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proc_bit_count:
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process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt)
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begin
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if rising_edge(ac_bit_clk) then
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if bitcnt_rst = '1' then
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bitcnt <= bitcnt_t'low;
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elsif bitcnt_en = '1' then
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if bitcnt /= bitcnt_t'high then
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bitcnt <= bitcnt + 1;
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else
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bitcnt <= bitcnt_t'low;
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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proc_ac_fsm:
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process (bitcnt, slotcnt, sac, ac_ssync)
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begin
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snac <= sac;
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bitcnt_rst <= '0';
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bitcnt_en <= '1';
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slotcnt_rst <= '0';
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slotcnt_en <= '0';
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slot_end <= '0';
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sync_end <= '0';
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last_slot <= '0';
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start_of_frame <= '0';
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if bitcnt = 19 then
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slot_end <= '1';
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end if;
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if slotcnt = 12 and bitcnt = 19 then
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last_slot <= '1';
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end if;
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case sac is
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when ac_idle =>
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bitcnt_rst <= '1';
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slotcnt_rst <= '1';
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if (ac_ssync = '1') then
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snac <= ac_tag;
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end if;
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when ac_tag =>
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if (bitcnt = 0) then
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start_of_frame <= '1';
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elsif (bitcnt = 15) then
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slotcnt_en <= '1';
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bitcnt_rst <= '1';
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sync_end <= '1';
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if (ac_ssync = '0') then
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snac <= ac_data;
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else
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snac <= ac_idle;
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end if;
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end if;
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when ac_data =>
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if bitcnt = 19 then
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slotcnt_en <= '1';
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if slotcnt = 12 then
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slotcnt_rst <= '1';
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snac <= ac_tag;
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end if;
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end if;
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when others => null;
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end case;
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end process;
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proc_ac_fsm_next:
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process (ac_reset, ac_bit_clk, snac)
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begin
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if ac_reset = '1' then
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sac <= ac_idle;
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elsif rising_edge(ac_bit_clk) then
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sac <= snac;
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end if;
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end process;
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-------------------------------------------------------------
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-- Receive Shift Register
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-------------------------------------------------------------
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process (ac_reset, ac_bit_clk, ac_sdata_in)
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begin
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if ac_reset = '1' then
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rx_reg <= (others => '0');
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elsif falling_edge(ac_bit_clk) then
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rx_reg <= rx_reg(rx_reg'left-1 downto 0) & ac_sdata_in;
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end if;
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end process;
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------------------------------------------------------------------
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singleshot_inst1: singleshot
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GENERIC MAP (
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mode => 0)
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PORT MAP(
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rst => rst,
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clk => clk,
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input => stat_read,
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output => host_update
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);
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singleshot_inst2: singleshot
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GENERIC MAP (
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mode => 1)
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PORT MAP(
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rst => rst,
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clk => clk,
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input => start_of_frame,
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output => sync_frame
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);
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-------------------------------------------------------------
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end Behavioral;
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@@ -0,0 +1,182 @@
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----------------------------------------------------------------------------------
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-- Company:
|
||||
-- Engineer:
|
||||
--
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||||
-- Create Date: 18:29:55 08/26/2006
|
||||
-- Design Name:
|
||||
-- Module Name: ac_io - Behavioral
|
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-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
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||||
----------------------------------------------------------------------------------
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||||
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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---- Uncomment the following library declaration if instantiating
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||||
---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ac_io is
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Port (
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rst : in std_logic;
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clk : in std_logic;
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ready : out std_logic;
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sync_strobe : out unsigned(0 to 2);
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slot_valid : out unsigned(0 to 12);
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stat_addr : out unsigned (19 downto 0);
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stat_data : out unsigned (19 downto 0);
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rx_pcm_addr : in unsigned (3 downto 0);
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rx_pcm_data : out unsigned (19 downto 0);
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cmd_addr : in unsigned(19 downto 0);
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cmd_data : in unsigned(19 downto 0);
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cmd_we : in std_logic;
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tx_pcm_addr : in unsigned(3 downto 0);
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tx_pcm_data : in unsigned(19 downto 0);
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tx_pcm_we : in std_logic;
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ac_sdata_in : in std_logic;
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ac_bit_clk : in std_logic;
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ac_reset_n : out std_logic;
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ac_sdata_out : out std_logic;
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ac_ssync : out std_logic);
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end ac_io;
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architecture Behavioral of ac_io is
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COMPONENT ac_in
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Port (
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rst : in std_logic;
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clk : in std_logic;
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sync_frame : out std_logic;
|
||||
sync_status : out std_logic;
|
||||
slot_valid : out unsigned(0 to 12);
|
||||
stat_addr : out unsigned (19 downto 0);
|
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stat_data : out unsigned (19 downto 0);
|
||||
pcm_out_addr : in unsigned (3 downto 0);
|
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pcm_out_data : out unsigned (19 downto 0);
|
||||
ac_reset : in std_logic;
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||||
ac_bit_clk : in std_logic;
|
||||
ac_sdata_in : in std_logic;
|
||||
ac_ssync : in std_logic
|
||||
);
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||||
END COMPONENT;
|
||||
|
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COMPONENT ac_out
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||||
PORT(
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rst : in std_logic;
|
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clk : in std_logic;
|
||||
sync_tx : out std_logic;
|
||||
cmd_addr : in unsigned(19 downto 0);
|
||||
cmd_data : in unsigned(19 downto 0);
|
||||
cmd_we : in std_logic;
|
||||
pcm_in_addr : in unsigned(3 downto 0);
|
||||
pcm_in_data : in unsigned(19 downto 0);
|
||||
pcm_in_we : in std_logic;
|
||||
ac_bit_clk : in std_logic;
|
||||
ac_reset : in std_logic;
|
||||
ac_sdata_out : out std_logic;
|
||||
ac_ssync : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL ac_reset : std_logic;
|
||||
SIGNAL ssync_rx : std_logic;
|
||||
SIGNAL ssync_tx : std_logic;
|
||||
SIGNAL sync_frame : std_logic;
|
||||
SIGNAL sync_status : std_logic;
|
||||
SIGNAL sync_tx : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
inst_ac_in: ac_in PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
sync_frame => sync_frame,
|
||||
sync_status => sync_status,
|
||||
slot_valid => slot_valid,
|
||||
stat_addr => stat_addr,
|
||||
stat_data => stat_data,
|
||||
pcm_out_addr => rx_pcm_addr,
|
||||
pcm_out_data => rx_pcm_data,
|
||||
ac_reset => ac_reset,
|
||||
ac_bit_clk => ac_bit_clk,
|
||||
ac_sdata_in => ac_sdata_in,
|
||||
ac_ssync => ssync_rx
|
||||
);
|
||||
|
||||
inst_ac_out: ac_out PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
sync_tx => sync_tx,
|
||||
cmd_addr => cmd_addr,
|
||||
cmd_data => cmd_data,
|
||||
cmd_we => cmd_we,
|
||||
pcm_in_addr => tx_pcm_addr,
|
||||
pcm_in_data => tx_pcm_data,
|
||||
pcm_in_we => tx_pcm_we,
|
||||
ac_reset => ac_reset,
|
||||
ac_bit_clk => ac_bit_clk,
|
||||
ac_sdata_out => ac_sdata_out,
|
||||
ac_ssync => ssync_tx
|
||||
);
|
||||
|
||||
------------------------------------------------------------------
|
||||
ready <= not ac_reset;
|
||||
ac_ssync <= ssync_tx;
|
||||
ssync_rx <= ssync_tx;
|
||||
sync_strobe <= sync_frame & sync_status & sync_tx;
|
||||
|
||||
------------------------------------------------------------------
|
||||
proc_reset_gen:
|
||||
process (rst, clk, ac_bit_clk)
|
||||
type rstate_t is (s0, s1);
|
||||
variable rstate, rstaten : rstate_t;
|
||||
subtype cnt_t is integer range 0 to 999;
|
||||
variable cnt : cnt_t;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
rstate := s0;
|
||||
cnt := cnt_t'high;
|
||||
ac_reset <= '1';
|
||||
ac_reset_n <= '0';
|
||||
else
|
||||
rstaten := rstate;
|
||||
case rstate is
|
||||
when s0 =>
|
||||
if cnt /= 0 then
|
||||
cnt := cnt - 1;
|
||||
else
|
||||
ac_reset_n <= '1';
|
||||
if ac_bit_clk = '1' then
|
||||
rstaten := s1;
|
||||
cnt := cnt_t'high;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when s1 =>
|
||||
if cnt /= 0 then
|
||||
cnt := cnt - 1;
|
||||
else
|
||||
ac_reset <= '0';
|
||||
end if;
|
||||
end case;
|
||||
rstate := rstaten;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,276 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15:41:12 06/05/2007
|
||||
-- Design Name:
|
||||
-- Module Name: ac_out - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity ac_out is
|
||||
Port (
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
sync_tx : out std_logic;
|
||||
cmd_addr : in unsigned (19 downto 0);
|
||||
cmd_data : in unsigned (19 downto 0);
|
||||
cmd_we : in std_logic;
|
||||
pcm_in_addr : in unsigned (3 downto 0);
|
||||
pcm_in_data : in unsigned (19 downto 0);
|
||||
pcm_in_we : in std_logic;
|
||||
ac_reset : in std_logic;
|
||||
ac_bit_clk : in std_logic;
|
||||
ac_sdata_out : out std_logic;
|
||||
ac_ssync : out std_logic
|
||||
);
|
||||
end ac_out;
|
||||
|
||||
architecture Behavioral of ac_out is
|
||||
|
||||
------------------------------------------------------------------
|
||||
COMPONENT singleshot
|
||||
GENERIC (mode : integer);
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
input : IN std_logic;
|
||||
output : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
------------------------------------------------------------------
|
||||
subtype tag_t is UNSIGNED(15 downto 0);
|
||||
subtype slot_valid_t is UNSIGNED(1 to 12);
|
||||
signal slot_valid : slot_valid_t;
|
||||
subtype slot_t is UNSIGNED(19 downto 0);
|
||||
type slot_array_t is array (natural range <>) of slot_t;
|
||||
signal data_array : slot_array_t (1 to 12);
|
||||
|
||||
signal tx_reg : UNSIGNED(19 downto 0);
|
||||
signal last_slot, ssync : STD_LOGIC;
|
||||
|
||||
type sac_t is (ac_idle, ac_tag, ac_data);
|
||||
signal sac, snac : sac_t;
|
||||
|
||||
subtype bitcnt_t is integer range 0 to 19;
|
||||
subtype slotcnt_t is integer range 0 to 12;
|
||||
|
||||
signal bitcnt : bitcnt_t;
|
||||
signal bitcnt_rst, bitcnt_en : STD_LOGIC;
|
||||
signal slotcnt : slotcnt_t;
|
||||
signal slotcnt_rst, slotcnt_en : STD_LOGIC;
|
||||
|
||||
signal slot_start : STD_LOGIC;
|
||||
|
||||
------------------------------------------------------------------
|
||||
function CreateTag(slot_valid : slot_valid_t) return tag_t is
|
||||
variable tag : tag_t := (others => '0');
|
||||
begin
|
||||
|
||||
tag := (others => '0');
|
||||
for i in slot_valid_t'range loop
|
||||
tag(15-i) := slot_valid(i);
|
||||
if slot_valid(i) = '1' then
|
||||
tag(15) := '1';
|
||||
end if;
|
||||
end loop;
|
||||
tag(0) := '0'; -- ID0
|
||||
tag(1) := '0'; -- ID1
|
||||
tag(2) := '0'; -- Reserved
|
||||
-- tag(15) := '1'; -- Frame is valid
|
||||
return tag;
|
||||
|
||||
end CreateTag;
|
||||
|
||||
begin
|
||||
|
||||
------------------------------------------------------------------
|
||||
proc_slot_reg:
|
||||
process (clk, cmd_addr, cmd_data, cmd_we, pcm_in_data, pcm_in_we, pcm_in_addr, last_slot)
|
||||
variable slot_id : integer range 0 to 12;
|
||||
begin
|
||||
slot_id := to_integer(pcm_in_addr);
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
for i in data_array'range(1) loop
|
||||
data_array(i) <= (others => '0');
|
||||
end loop;
|
||||
slot_valid <= (others => '0');
|
||||
elsif last_slot = '1' then
|
||||
slot_valid <= (others => '0');
|
||||
else
|
||||
if cmd_we = '1' then
|
||||
slot_valid(1) <= '1';
|
||||
slot_valid(2) <= '1';
|
||||
data_array(1) <= cmd_addr;
|
||||
data_array(2) <= cmd_data;
|
||||
end if;
|
||||
if pcm_in_we = '1' then
|
||||
if (slot_id > 2) then
|
||||
data_array(slot_id) <= pcm_in_data;
|
||||
slot_valid(slot_id) <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- proc_slot_count
|
||||
-------------------------------------------------------------
|
||||
proc_slot_count:
|
||||
process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt)
|
||||
begin
|
||||
if rising_edge(ac_bit_clk) then
|
||||
if slotcnt_rst = '1' then
|
||||
slotcnt <= slotcnt_t'low;
|
||||
elsif slotcnt_en = '1' then
|
||||
if slotcnt /= slotcnt_t'high then
|
||||
slotcnt <= slotcnt + 1;
|
||||
else
|
||||
slotcnt <= slotcnt_t'low;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- proc_bit_count
|
||||
------------------------------------------------------------------
|
||||
proc_bit_count:
|
||||
process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt)
|
||||
begin
|
||||
if rising_edge(ac_bit_clk) then
|
||||
if bitcnt_rst = '1' then
|
||||
bitcnt <= bitcnt_t'low;
|
||||
elsif bitcnt_en = '1' then
|
||||
if bitcnt /= bitcnt_t'high then
|
||||
bitcnt <= bitcnt + 1;
|
||||
else
|
||||
bitcnt <= bitcnt_t'low;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
------------------------------------------------------------------
|
||||
proc_ac_fsm:
|
||||
process (bitcnt, slotcnt, sac)
|
||||
begin
|
||||
snac <= sac;
|
||||
bitcnt_rst <= '0';
|
||||
bitcnt_en <= '1';
|
||||
slotcnt_rst <= '0';
|
||||
slotcnt_en <= '0';
|
||||
slot_start <= '0';
|
||||
ssync <= '0';
|
||||
|
||||
if bitcnt = 0 then
|
||||
slot_start <= '1';
|
||||
end if;
|
||||
|
||||
case sac is
|
||||
|
||||
when ac_idle =>
|
||||
bitcnt_rst <= '1';
|
||||
slotcnt_rst <= '1';
|
||||
snac <= ac_tag;
|
||||
|
||||
when ac_tag =>
|
||||
ssync <= '1';
|
||||
if (bitcnt = 15) then
|
||||
slotcnt_en <= '1';
|
||||
bitcnt_rst <= '1';
|
||||
snac <= ac_data;
|
||||
end if;
|
||||
|
||||
when ac_data =>
|
||||
if bitcnt = 19 then
|
||||
slotcnt_en <= '1';
|
||||
if slotcnt = 12 then
|
||||
slotcnt_rst <= '1';
|
||||
snac <= ac_tag;
|
||||
end if;
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
proc_ac_fsm_next:
|
||||
process (ac_reset, ac_bit_clk, snac)
|
||||
begin
|
||||
if ac_reset = '1' then
|
||||
sac <= ac_idle;
|
||||
elsif rising_edge(ac_bit_clk) then
|
||||
sac <= snac;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
proc_tx_shift_reg:
|
||||
process (ac_reset, ac_bit_clk, tx_reg, ssync, slot_valid, data_array)
|
||||
begin
|
||||
|
||||
if ac_reset = '1' then
|
||||
tx_reg <= (others => '0');
|
||||
elsif rising_edge(ac_bit_clk) then
|
||||
last_slot <= '0';
|
||||
if slot_start = '1' then
|
||||
if ssync = '1' then
|
||||
tx_reg <= CreateTag(slot_valid) & "0000";
|
||||
else
|
||||
if slotcnt /= 0 then
|
||||
tx_reg <= data_array(slotcnt);
|
||||
if slotcnt = 12 then
|
||||
last_slot <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
tx_reg <= tx_reg(tx_reg'left-1 downto 0) & '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
proc_ac_sync_out:
|
||||
process (ac_reset, ac_bit_clk, ssync, tx_reg)
|
||||
begin
|
||||
if ac_reset = '1' then
|
||||
ac_ssync <= '0';
|
||||
ac_sdata_out <= '0';
|
||||
elsif rising_edge(ac_bit_clk) then
|
||||
ac_ssync <= ssync;
|
||||
ac_sdata_out <= tx_reg(tx_reg'left);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
singleshot_inst1: singleshot
|
||||
GENERIC MAP (
|
||||
mode => 0)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
input => last_slot,
|
||||
output => sync_tx
|
||||
@@ -0,0 +1,153 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 21:52:19 10/22/05
|
||||
-- Design Name:
|
||||
-- Module Name: singleshot - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Component Template
|
||||
--
|
||||
-- COMPONENT singleshot
|
||||
-- GENERIC (mode : integer);
|
||||
-- PORT(
|
||||
-- rst : IN std_logic;
|
||||
-- clk : IN std_logic;
|
||||
-- input : IN std_logic;
|
||||
-- output : OUT std_logic
|
||||
-- );
|
||||
-- END COMPONENT;
|
||||
--
|
||||
-- Instantation Template
|
||||
--
|
||||
-- singleshot_int: oneshot
|
||||
-- GENERIC MAP (
|
||||
-- mode => 1)
|
||||
-- PORT MAP(
|
||||
-- rst => ,
|
||||
-- clk => ,
|
||||
-- input => ,
|
||||
-- output =>
|
||||
-- );
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity singleshot is
|
||||
Generic ( mode : integer range 0 to 2 := 1);
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
input : in std_logic;
|
||||
output : out std_logic);
|
||||
end singleshot;
|
||||
|
||||
architecture Behavioral of singleshot is
|
||||
|
||||
type s_t is (idle, shot_in, active, shot_out);
|
||||
signal s, sn : s_t;
|
||||
|
||||
begin
|
||||
|
||||
process (rst, clk, sn)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
s <= idle;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
mode_1:
|
||||
if mode = 1 generate
|
||||
begin
|
||||
process (input, s)
|
||||
begin
|
||||
output <= '0';
|
||||
sn <= s;
|
||||
case s is
|
||||
when idle =>
|
||||
if input = '1' then
|
||||
sn <= shot_in;
|
||||
end if;
|
||||
when shot_in =>
|
||||
output <= '1';
|
||||
sn <= active;
|
||||
when active =>
|
||||
if input = '0' then
|
||||
sn <= shot_out;
|
||||
end if;
|
||||
when shot_out =>
|
||||
sn <= idle;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
mode_0:
|
||||
if mode = 0 generate
|
||||
begin
|
||||
process (input, s)
|
||||
begin
|
||||
output <= '0';
|
||||
sn <= s;
|
||||
case s is
|
||||
when idle =>
|
||||
if input = '1' then
|
||||
sn <= shot_in;
|
||||
end if;
|
||||
when shot_in =>
|
||||
sn <= active;
|
||||
when active =>
|
||||
if input = '0' then
|
||||
sn <= shot_out;
|
||||
end if;
|
||||
when shot_out =>
|
||||
output <= '1';
|
||||
sn <= idle;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
mode_2:
|
||||
if mode = 2 generate
|
||||
begin
|
||||
process (input, s)
|
||||
begin
|
||||
output <= '0';
|
||||
sn <= s;
|
||||
case s is
|
||||
when idle =>
|
||||
if input = '1' then
|
||||
sn <= shot_in;
|
||||
end if;
|
||||
when shot_in =>
|
||||
output <= '1';
|
||||
sn <= active;
|
||||
when active =>
|
||||
if input = '0' then
|
||||
sn <= shot_out;
|
||||
end if;
|
||||
when shot_out =>
|
||||
output <= '1';
|
||||
sn <= idle;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
end Behavioral;
|
||||
Reference in New Issue
Block a user