- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1423 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,134 @@
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--- ============================================================================
|
||||
--
|
||||
-- Design unit : aes_column_ops
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||||
--
|
||||
-- File Name : aes_column_ops.vhd
|
||||
--
|
||||
-- Purpose : Design file
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : -
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : -
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>,
|
||||
-- M.v.d.Wall (mvdw) <vdwall@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
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||||
-- - constants are in UPPERCASE
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-- - name parts are separated by "_"
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--
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-- ============================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use work.aes_gf_2exp8_arith.all;
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package aes_column_ops is
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type column_t is array (0 to 3) of gf_2exp8_t;
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function mix_column(col : in column_t) return column_t;
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function inv_mix_column(col : in column_t) return column_t;
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end aes_column_ops;
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package body aes_column_ops is
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type trans_matrix_t is array (0 to 3, 0 to 3) of gf_2exp8_t;
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constant TRANS_MATRIX : trans_matrix_t :=
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(
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(X"02", X"03", X"01", X"01"),
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(X"01", X"02", X"03", X"01"),
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(X"01", X"01", X"02", X"03"),
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(X"03", X"01", X"01", X"02")
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);
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constant INV_TRANS_MATRIX : trans_matrix_t :=
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(
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(X"0e", X"0b", X"0d", X"09"),
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(X"09", X"0e", X"0b", X"0d"),
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(X"0d", X"09", X"0e", X"0b"),
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(X"0b", X"0d", X"09", X"0e")
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);
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function mix_column(col : in column_t) return column_t is
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variable v_col : column_t;
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begin
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for c in v_col'range loop
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v_col(c) := X"00";
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end loop;
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for r in v_col'range loop
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for c in v_col'range loop
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v_col(r) := add_gf_2exp8(v_col(r), mul_gf_2exp8(TRANS_MATRIX(r,c), col(c)));
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end loop;
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end loop;
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return v_col;
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end mix_column;
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function inv_mix_column(col : in column_t) return column_t is
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variable v_col : column_t;
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begin
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for c in v_col'range loop
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v_col(c) := X"00";
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end loop;
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for r in v_col'range loop
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for c in v_col'range loop
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v_col(r) := add_gf_2exp8(v_col(r), mul_gf_2exp8(INV_TRANS_MATRIX(r,c), col(c)));
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end loop;
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end loop;
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return v_col;
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end inv_mix_column;
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end aes_column_ops;
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@@ -0,0 +1,202 @@
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--- ============================================================================
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||||
--
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||||
-- Design unit : aes_common
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||||
--
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||||
-- File Name : aes_common.vhd
|
||||
--
|
||||
-- Purpose : This package defines supplemental types, subtypes,
|
||||
-- constants, and functions
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : -
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : -
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>,
|
||||
-- M.v.d.Wall (mvdw) <vdwall@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
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use ieee.std_logic_1164.all;
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use work.aes_definitions.all;
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use work.aes_row_ops.all;
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use work.aes_column_ops.all;
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||||
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package aes_common is
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function add_round_key(state, state_key : aes_state_t) return aes_state_t;
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function select_column(state : aes_state_t; pos : natural) return column_t;
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function replace_column(state : aes_state_t; col : column_t; pos : natural) return aes_state_t;
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function select_row(state : aes_state_t; pos : natural) return row_t;
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function replace_row(state : aes_state_t; row : row_t; pos : natural) return aes_state_t;
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function to_aes_state_matrix(st : aes_state_t) return aes_sbox_matrix_t;
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function to_aes_state_vector(bb : aes_sbox_matrix_t) return aes_state_t;
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end aes_common;
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package body aes_common is
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function add_round_key(state, state_key : aes_state_t) return aes_state_t is
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begin
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return (state xor state_key);
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end add_round_key;
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function select_column(state : aes_state_t; pos : natural) return column_t is
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variable v_col : column_t;
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begin
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for i in v_col'range loop
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v_col(i) := state((127 - 32*pos - 8*i) downto (127 - 32*pos - 8*i) - 7);
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end loop;
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return v_col;
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end select_column;
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function replace_column(state : aes_state_t; col : column_t; pos : natural) return aes_state_t is
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variable v_st : aes_state_t;
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begin
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v_st := state;
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for i in col'range loop
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v_st((127 - 32*pos - 8*i) downto (127 - 32*pos - 8*i) - 7) := col(i);
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end loop;
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return v_st;
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end replace_column;
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||||
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function select_row(state : aes_state_t; pos : natural) return row_t is
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variable v_row : row_t;
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begin
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for i in v_row'range loop
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v_row(i) := state((127 - 8*pos - 32*i) downto (127 - 8*pos - 32*i) - 7);
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end loop;
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||||
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return v_row;
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end select_row;
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||||
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function replace_row(state : aes_state_t; row : row_t; pos : natural) return aes_state_t is
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variable v_st : aes_state_t;
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begin
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v_st := state;
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for i in row'range loop
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v_st((127 - 8*pos - 32*i) downto (127 - 8*pos - 32*i) - 7) := row(i);
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||||
end loop;
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return v_st;
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end replace_row;
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||||
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function to_aes_state_matrix(st : aes_state_t) return aes_sbox_matrix_t is
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variable v_row : row_t;
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variable v_line : std_logic_vector(31 downto 0);
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variable v_bb : aes_sbox_matrix_t;
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begin
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||||
for r in v_bb'range(1) loop
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for c in v_bb'range(2) loop
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v_bb(r, c) := (others => '0');
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||||
end loop;
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||||
end loop;
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||||
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for r in v_bb'range(1) loop
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v_row := select_row(st, r);
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v_line := v_row(0) & v_row(1) & v_row(2) & v_row(3);
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for c in v_bb'range(2) loop
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v_bb(r, c)(7 downto 0) := v_line(31 - 8*c downto 24 - 8*c);
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||||
end loop;
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||||
|
||||
end loop;
|
||||
|
||||
return v_bb;
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||||
end to_aes_state_matrix;
|
||||
|
||||
|
||||
|
||||
function to_aes_state_vector(bb : aes_sbox_matrix_t) return aes_state_t is
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||||
variable v_row : row_t;
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||||
variable v_line : std_logic_vector(31 downto 0);
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||||
variable v_st : aes_state_t;
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||||
begin
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||||
v_st := (others => '0');
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||||
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||||
for r in bb'range(1) loop
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||||
v_line := (others => '0');
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||||
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||||
for c in bb'range(2) loop
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||||
v_line(31 - 8*c downto 24 - 8*c) := bb(r, c)(7 downto 0);
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||||
end loop;
|
||||
|
||||
for i in v_row'range loop
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||||
v_row(i) := v_line(31 - 8*i downto 31-8*i - 7);
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||||
end loop;
|
||||
|
||||
v_st := replace_row(v_st, v_row, r);
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||||
end loop;
|
||||
|
||||
return v_st;
|
||||
end to_aes_state_vector;
|
||||
|
||||
|
||||
end aes_common;
|
||||
@@ -0,0 +1,115 @@
|
||||
--- ============================================================================
|
||||
--
|
||||
-- Design unit : aes_decryption
|
||||
--
|
||||
-- File Name : aes_decryption.vhd
|
||||
--
|
||||
-- Purpose : design file
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : -
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : -
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>,
|
||||
-- M.v.d.Wall (mvdw) <vdwall@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
use work.aes_definitions.all;
|
||||
use work.aes_common.all;
|
||||
use work.aes_column_ops.all;
|
||||
use work.aes_row_ops.all;
|
||||
|
||||
|
||||
|
||||
package aes_decryption is
|
||||
|
||||
|
||||
function inv_mix_columns(st : in aes_state_t) return aes_state_t;
|
||||
|
||||
function inv_shift_rows(st : in aes_state_t) return aes_state_t;
|
||||
|
||||
|
||||
end aes_decryption;
|
||||
|
||||
|
||||
package body aes_decryption is
|
||||
|
||||
|
||||
function inv_mix_columns(st : in aes_state_t) return aes_state_t is
|
||||
type columns_t is array(0 to 3) of column_t;
|
||||
variable v_cols : columns_t;
|
||||
variable v_st : aes_state_t;
|
||||
begin
|
||||
for i in v_cols'range loop
|
||||
v_cols(i) := inv_mix_column(select_column(st, i));
|
||||
v_st := replace_column(v_st, v_cols(i), i);
|
||||
end loop;
|
||||
|
||||
return v_st;
|
||||
end inv_mix_columns;
|
||||
|
||||
|
||||
|
||||
|
||||
function inv_shift_rows(st : in aes_state_t) return aes_state_t is
|
||||
type rows_t is array(0 to 3) of row_t;
|
||||
variable v_rows : rows_t;
|
||||
variable v_st : aes_state_t;
|
||||
begin
|
||||
for i in v_rows'range loop
|
||||
v_rows(i) := inv_shift_row(select_row(st, i), i);
|
||||
v_st := replace_row(v_st, v_rows(i), i);
|
||||
end loop;
|
||||
|
||||
return v_st;
|
||||
end inv_shift_rows;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
end aes_decryption;
|
||||
@@ -0,0 +1,83 @@
|
||||
--- ============================================================================
|
||||
--
|
||||
-- Design unit : aes_definitions
|
||||
--
|
||||
-- File Name : aes_definitions.vhd
|
||||
--
|
||||
-- Purpose : This package defines supplemental types, subtypes,
|
||||
-- constants, and functions
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : -
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : -
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>,
|
||||
-- M.v.d.Wall (mvdw) <vdwall@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
|
||||
package aes_definitions is
|
||||
|
||||
|
||||
constant AES_128_ROUNDS : natural := 10;
|
||||
|
||||
constant AES_256_ROUNDS : natural := 14;
|
||||
|
||||
|
||||
subtype aes_state_t is std_logic_vector(127 downto 0);
|
||||
|
||||
-- 4 bit are sufficient to keep maximal round number
|
||||
subtype aes_round_no_t is std_logic_vector(3 downto 0);
|
||||
|
||||
|
||||
subtype aes_sbox_8_t is std_logic_vector(7 downto 0);
|
||||
|
||||
|
||||
type aes_sbox_matrix_t is array(0 to 3, 0 to 3) of aes_sbox_8_t;
|
||||
|
||||
|
||||
end aes_definitions;
|
||||
@@ -0,0 +1,110 @@
|
||||
--- ============================================================================
|
||||
--
|
||||
-- Design unit : aes_encryption
|
||||
--
|
||||
-- File Name : aes_encryption.vhd
|
||||
--
|
||||
-- Purpose : Design file
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : -
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : -
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>,
|
||||
-- M.v.d.Wall (mvdw) <vdwall@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
use work.aes_definitions.all;
|
||||
use work.aes_common.all;
|
||||
use work.aes_column_ops.all;
|
||||
use work.aes_row_ops.all;
|
||||
|
||||
|
||||
package aes_encryption is
|
||||
|
||||
|
||||
function mix_columns(st : in aes_state_t) return aes_state_t;
|
||||
|
||||
function shift_rows(st : in aes_state_t) return aes_state_t;
|
||||
|
||||
|
||||
end aes_encryption;
|
||||
|
||||
|
||||
package body aes_encryption is
|
||||
|
||||
|
||||
function mix_columns(st : in aes_state_t) return aes_state_t is
|
||||
type columns_t is array(0 to 3) of column_t;
|
||||
variable v_cols : columns_t;
|
||||
variable v_st : aes_state_t;
|
||||
begin
|
||||
for i in v_cols'range loop
|
||||
v_cols(i) := mix_column(select_column(st, i));
|
||||
v_st := replace_column(v_st, v_cols(i), i);
|
||||
end loop;
|
||||
|
||||
return v_st;
|
||||
end mix_columns;
|
||||
|
||||
|
||||
|
||||
|
||||
function shift_rows(st : in aes_state_t) return aes_state_t is
|
||||
type rows_t is array(0 to 3) of row_t;
|
||||
variable v_rows : rows_t;
|
||||
variable v_st : aes_state_t;
|
||||
begin
|
||||
for i in v_rows'range loop
|
||||
v_rows(i) := shift_row(select_row(st, i), i);
|
||||
v_st := replace_row(v_st, v_rows(i), i);
|
||||
end loop;
|
||||
|
||||
return v_st;
|
||||
end shift_rows;
|
||||
|
||||
|
||||
end aes_encryption;
|
||||
@@ -0,0 +1,168 @@
|
||||
--- ============================================================================
|
||||
--
|
||||
-- Design unit : aes_gf_2exp8_arith
|
||||
--
|
||||
-- File Name : aes_gf_2exp8_arith.vhd
|
||||
--
|
||||
-- Purpose : Design file
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : -
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : -
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>,
|
||||
-- M.v.d.Wall (mvdw) <vdwall@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
package aes_gf_2exp8_arith is
|
||||
|
||||
|
||||
subtype gf_2exp8_t is std_logic_vector(7 downto 0);
|
||||
|
||||
|
||||
function add_gf_2exp8(a, b : in gf_2exp8_t) return gf_2exp8_t;
|
||||
|
||||
function mul_gf_2exp8(a, b : in gf_2exp8_t) return gf_2exp8_t;
|
||||
|
||||
|
||||
end aes_gf_2exp8_arith;
|
||||
|
||||
|
||||
-- AES irreducible polynomial
|
||||
-- POLY = 2**8 + 2**4 + 2**3 + 2**1 + 2**0
|
||||
|
||||
package body aes_gf_2exp8_arith is
|
||||
|
||||
|
||||
function add_gf_2exp8(a, b : in gf_2exp8_t) return gf_2exp8_t is
|
||||
begin
|
||||
return (a xor b);
|
||||
end add_gf_2exp8;
|
||||
|
||||
|
||||
function mul_gf_2exp8(a, b : in gf_2exp8_t) return gf_2exp8_t is
|
||||
variable c : gf_2exp8_t;
|
||||
begin
|
||||
|
||||
c(0) := ((a(0)) and b(0)) xor
|
||||
((a(7)) and b(1)) xor
|
||||
((a(6)) and b(2)) xor
|
||||
((a(5)) and b(3)) xor
|
||||
((a(4)) and b(4)) xor
|
||||
((a(3) xor a(7)) and b(5)) xor
|
||||
((a(2) xor a(6) xor a(7)) and b(6)) xor
|
||||
((a(1) xor a(5) xor a(6)) and b(7));
|
||||
|
||||
c(1) := ((a(1)) and b(0)) xor
|
||||
((a(0) xor a(7)) and b(1)) xor
|
||||
((a(6) xor a(7)) and b(2)) xor
|
||||
((a(5) xor a(6)) and b(3)) xor
|
||||
((a(4) xor a(5)) and b(4)) xor
|
||||
((a(3) xor a(4) xor a(7)) and b(5)) xor
|
||||
((a(2) xor a(3) xor a(6)) and b(6)) xor
|
||||
((a(1) xor a(2) xor a(5) xor a(7)) and b(7));
|
||||
|
||||
c(2) := ((a(2)) and b(0)) xor
|
||||
((a(1)) and b(1)) xor
|
||||
((a(0) xor a(7)) and b(2)) xor
|
||||
((a(6) xor a(7)) and b(3)) xor
|
||||
((a(5) xor a(6)) and b(4)) xor
|
||||
((a(4) xor a(5)) and b(5)) xor
|
||||
((a(3) xor a(4) xor a(7)) and b(6)) xor
|
||||
((a(2) xor a(3) xor a(6)) and b(7));
|
||||
|
||||
c(3) := ((a(3)) and b(0)) xor
|
||||
((a(2) xor a(7)) and b(1)) xor
|
||||
((a(1) xor a(6)) and b(2)) xor
|
||||
((a(0) xor a(5) xor a(7)) and b(3)) xor
|
||||
((a(4) xor a(6) xor a(7)) and b(4)) xor
|
||||
((a(3) xor a(5) xor a(6) xor a(7)) and b(5)) xor
|
||||
((a(2) xor a(4) xor a(5) xor a(6) xor a(7)) and b(6)) xor
|
||||
((a(1) xor a(3) xor a(4) xor a(5) xor a(6) xor a(7)) and b(7));
|
||||
|
||||
c(4) := ((a(4)) and b(0)) xor
|
||||
((a(3) xor a(7)) and b(1)) xor
|
||||
((a(2) xor a(6) xor a(7)) and b(2)) xor
|
||||
((a(1) xor a(5) xor a(6)) and b(3)) xor
|
||||
((a(0) xor a(4) xor a(5) xor a(7)) and b(4)) xor
|
||||
((a(3) xor a(4) xor a(6)) and b(5)) xor
|
||||
((a(2) xor a(3) xor a(5)) and b(6)) xor
|
||||
((a(1) xor a(2) xor a(4) xor a(7)) and b(7));
|
||||
|
||||
c(5) := ((a(5)) and b(0)) xor
|
||||
((a(4)) and b(1)) xor
|
||||
((a(3) xor a(7)) and b(2)) xor
|
||||
((a(2) xor a(6) xor a(7)) and b(3)) xor
|
||||
((a(1) xor a(5) xor a(6)) and b(4)) xor
|
||||
((a(0) xor a(4) xor a(5) xor a(7)) and b(5)) xor
|
||||
((a(3) xor a(4) xor a(6)) and b(6)) xor
|
||||
((a(2) xor a(3) xor a(5)) and b(7));
|
||||
|
||||
c(6) := ((a(6)) and b(0)) xor
|
||||
((a(5)) and b(1)) xor
|
||||
((a(4)) and b(2)) xor
|
||||
((a(3) xor a(7)) and b(3)) xor
|
||||
((a(2) xor a(6) xor a(7)) and b(4)) xor
|
||||
((a(1) xor a(5) xor a(6)) and b(5)) xor
|
||||
((a(0) xor a(4) xor a(5) xor a(7)) and b(6)) xor
|
||||
((a(3) xor a(4) xor a(6)) and b(7));
|
||||
|
||||
c(7) := ((a(7)) and b(0)) xor
|
||||
((a(6)) and b(1)) xor
|
||||
((a(5)) and b(2)) xor
|
||||
((a(4)) and b(3)) xor
|
||||
((a(3) xor a(7)) and b(4)) xor
|
||||
((a(2) xor a(6) xor a(7)) and b(5)) xor
|
||||
((a(1) xor a(5) xor a(6)) and b(6)) xor
|
||||
((a(0) xor a(4) xor a(5) xor a(7)) and b(7));
|
||||
|
||||
return c;
|
||||
|
||||
end mul_gf_2exp8;
|
||||
|
||||
|
||||
end aes_gf_2exp8_arith;
|
||||
@@ -0,0 +1,105 @@
|
||||
--- ============================================================================
|
||||
--
|
||||
-- Design unit : aes
|
||||
--
|
||||
-- File Name : aes_row_ops.vhd
|
||||
--
|
||||
-- Purpose : Row shift operations for ciper and inverse ciphers
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : -
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : -
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>,
|
||||
-- M.v.d.Wall (mvdw) <vdwall@dsi-it.de>
|
||||
-- J. Ahrensfeld (ja) <ja@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
-- use ieee.numeric_bit.all;
|
||||
|
||||
use work.aes_gf_2exp8_arith.all;
|
||||
|
||||
|
||||
package aes_row_ops is
|
||||
|
||||
|
||||
type row_t is array (0 to 3) of gf_2exp8_t;
|
||||
|
||||
|
||||
function shift_row(row : in row_t; steps : natural) return row_t;
|
||||
|
||||
function inv_shift_row(row : in row_t; steps : natural) return row_t;
|
||||
|
||||
|
||||
end aes_row_ops;
|
||||
|
||||
|
||||
package body aes_row_ops is
|
||||
|
||||
|
||||
function shift_row(row : in row_t; steps : natural) return row_t is
|
||||
variable a_row : row_t;
|
||||
begin
|
||||
for i in a_row'range loop
|
||||
a_row(i) := row((i + steps) mod row'length);
|
||||
end loop;
|
||||
|
||||
return a_row;
|
||||
end shift_row;
|
||||
|
||||
|
||||
function inv_shift_row(row : in row_t; steps : natural) return row_t is
|
||||
variable a_row : row_t;
|
||||
begin
|
||||
for i in a_row'range loop
|
||||
a_row(i) := row((i - steps + row'length) mod row'length);
|
||||
end loop;
|
||||
|
||||
return a_row;
|
||||
end inv_shift_row;
|
||||
|
||||
|
||||
end aes_row_ops;
|
||||
@@ -0,0 +1,185 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : cbc_128_encryption_core (CBC-mode encryption core with
|
||||
-- 128-bit key schedule)
|
||||
--
|
||||
-- File Name : cbc_128_encryption_core.vhd
|
||||
--
|
||||
-- Purpose : The module instantiates all necessary modules (S-box
|
||||
-- stages, encryption, CBC-mode, key schedule, subkey
|
||||
-- memory etc.) to provide an CBC-mode encryption core
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : tech_iface, key_schedule_iface, engine_iface,
|
||||
-- cbc_mode_iface, cbc_core_iface
|
||||
--
|
||||
-- - Module(s) : cbc_mode_encryption, encryption_engine, tech_sbox_stage,
|
||||
-- tech_subkey_memory, key_schedule_128
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : Version for implementation using 32-bit datapath
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2007-01-31 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
|
||||
use work.tech_iface.all;
|
||||
use work.key_schedule_iface.all;
|
||||
use work.engine_iface.all;
|
||||
use work.cbc_mode_iface.all;
|
||||
use work.cbc_core_iface.all;
|
||||
|
||||
|
||||
entity cbc_128_encryption_core is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in cbc_mode_encryption_in_type; -- see package cbc_mode_iface
|
||||
mode_o : out cbc_mode_encryption_out_type; -- see package cbc_mode_iface
|
||||
key_i : in key_schedule_128_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_128_out_type; -- see package key_schedule_iface
|
||||
sbld_i : in sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end cbc_128_encryption_core;
|
||||
|
||||
|
||||
architecture behavioural of cbc_128_encryption_core is
|
||||
|
||||
|
||||
signal enc_i : encryption_engine_in_type; -- input to the encryption engine
|
||||
signal enc_o : encryption_engine_out_type; -- output of the encryption engine
|
||||
|
||||
signal sbox_enc_i : sbox_stage_in_type; -- input to the S-box stage
|
||||
signal sbox_enc_o : sbox_stage_out_type; -- output of the S-box stage
|
||||
|
||||
signal sbox_ks_i : sbox_stage_in_type; -- input to the S-box stage (key schedule)
|
||||
signal sbox_ks_o : sbox_stage_out_type; -- output of the S-box stage (key schedule)
|
||||
|
||||
signal skm_enc_i : subkey_memory_ed_in_type; -- encryption-side subkey memory access (subkey selection)
|
||||
signal skm_enc_o : subkey_memory_ed_out_type; -- encryption-side subkey memory access (selected subkey)
|
||||
|
||||
signal skm_ks_enc_i : subkey_memory_ks_in_type; -- subkey storage by key schedule
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-- AES CBC-mode encryption
|
||||
cbc_mode: cbc_mode_encryption
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
mode_i => mode_i,
|
||||
mode_o => mode_o,
|
||||
enc_i => enc_o,
|
||||
enc_o => enc_i
|
||||
);
|
||||
|
||||
|
||||
-- AES encryption engine
|
||||
enc_eng: encryption_engine
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
enc_i => enc_i,
|
||||
enc_o => enc_o,
|
||||
skm_i => skm_enc_o,
|
||||
skm_o => skm_enc_i,
|
||||
sbox_i => sbox_enc_o,
|
||||
sbox_o => sbox_enc_i
|
||||
);
|
||||
|
||||
|
||||
-- S-Box stage for encryption engine
|
||||
sbox_enc: tech_sbox_stage
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
data_i => sbox_enc_i,
|
||||
data_o => sbox_enc_o,
|
||||
load_i => sbld_i
|
||||
);
|
||||
|
||||
|
||||
-- subkey memory for encryption engine
|
||||
skm_enc: tech_subkey_memory
|
||||
port map (
|
||||
clk => clk,
|
||||
key_sched_i => skm_ks_enc_i,
|
||||
enc_dec_i => skm_enc_i,
|
||||
enc_dec_o => skm_enc_o
|
||||
);
|
||||
|
||||
|
||||
-- 128-bit key schedule
|
||||
key_sched: key_schedule_128
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
key_i => key_i,
|
||||
key_o => key_o,
|
||||
sbox_i => sbox_ks_o,
|
||||
sbox_o => sbox_ks_i,
|
||||
skm_enc_o => skm_ks_enc_i,
|
||||
skm_dec_o => open
|
||||
);
|
||||
|
||||
|
||||
-- S-Box stage for key schedule
|
||||
sbox_ks: tech_sbox_stage
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
data_i => sbox_ks_i,
|
||||
data_o => sbox_ks_o,
|
||||
load_i => sbld_i
|
||||
);
|
||||
|
||||
|
||||
end behavioural;
|
||||
+2430
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,146 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : cbc_core_iface (interfaces of CBC-mode en-/decryption
|
||||
-- cores)
|
||||
--
|
||||
-- File Name : cbc_core_iface.vhd
|
||||
--
|
||||
-- Purpose : The package collects type declarations for all non-
|
||||
-- trivial interfaces of used entities. Record types
|
||||
-- are used extensively to group related signals (e.g.
|
||||
-- data / control & status, physical attachment etc.).
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : tech_iface, key_schedule_iface, engine_iface,
|
||||
-- cbc_mode_iface
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : Version for implementation using 32-bit datapath
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2007-01-31 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
use work.tech_iface.all;
|
||||
use work.key_schedule_iface.all;
|
||||
use work.engine_iface.all;
|
||||
use work.cbc_mode_iface.all;
|
||||
|
||||
|
||||
package cbc_core_iface is
|
||||
|
||||
|
||||
-- no new interfaces are needed yet
|
||||
|
||||
|
||||
|
||||
--
|
||||
--
|
||||
-- Component declarations
|
||||
--
|
||||
--
|
||||
|
||||
|
||||
-- AES-CBC-128 encryption core
|
||||
component cbc_128_encryption_core is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in cbc_mode_encryption_in_type; -- see package cbc_mode_iface
|
||||
mode_o : out cbc_mode_encryption_out_type; -- see package cbc_mode_iface
|
||||
key_i : in key_schedule_128_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_128_out_type; -- see package key_schedule_iface
|
||||
sbld_i : in sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
-- AES-CBC-128 decryption core
|
||||
component cbc_128_decryption_core is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in cbc_mode_decryption_in_type; -- see package cbc_mode_iface
|
||||
mode_o : out cbc_mode_decryption_out_type; -- see package cbc_mode_iface
|
||||
key_i : in key_schedule_128_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_128_out_type; -- see package key_schedule_iface
|
||||
sbld_i : in sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
-- AES-CBC-256 encryption core
|
||||
component cbc_256_encryption_core is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in cbc_mode_encryption_in_type; -- see package cbc_mode_iface
|
||||
mode_o : out cbc_mode_encryption_out_type; -- see package cbc_mode_iface
|
||||
key_i : in key_schedule_256_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_256_out_type; -- see package key_schedule_iface
|
||||
sbld_i : in sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
-- AES-CBC-256 decryption core
|
||||
component cbc_256_decryption_core is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in cbc_mode_decryption_in_type; -- see package cbc_mode_iface
|
||||
mode_o : out cbc_mode_decryption_out_type; -- see package cbc_mode_iface
|
||||
key_i : in key_schedule_256_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_256_out_type; -- see package key_schedule_iface
|
||||
sbld_i : in sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
end cbc_core_iface;
|
||||
@@ -0,0 +1,272 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : cbc_mode_encryption (CBC-mode encryption)
|
||||
--
|
||||
-- File Name : cbc_mode_encryption.vhd
|
||||
--
|
||||
-- Purpose : The module provides CBC-mode encryption for AES
|
||||
-- using 32-bit datapath
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : aes_defnitions, tech_iface, engine_iface, cbc_mode_iface
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : Version for implementation using 32-bit datapath
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2007-01-31 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: two-process method (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
|
||||
use work.aes_definitions.all;
|
||||
use work.tech_iface.all;
|
||||
use work.engine_iface.all;
|
||||
use work.cbc_mode_iface.all;
|
||||
|
||||
|
||||
entity cbc_mode_encryption is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in cbc_mode_encryption_in_type; -- see package cbc_mode_iface
|
||||
mode_o : out cbc_mode_encryption_out_type; -- see package cbc_mode_iface
|
||||
enc_i : in encryption_engine_out_type; -- see package engine_iface
|
||||
enc_o : out encryption_engine_in_type -- see package engine_iface
|
||||
);
|
||||
end cbc_mode_encryption;
|
||||
|
||||
|
||||
architecture behavioural of cbc_mode_encryption is
|
||||
|
||||
|
||||
-- control fsm, states: idle / load IV / load input data / wait while encrypting / output data
|
||||
type ctrl_fsm_t is (cf_idle, cf_load_iv, cf_load_data, cf_wait_enc, cf_out_data);
|
||||
|
||||
type registers is record
|
||||
ctrl_fsm : ctrl_fsm_t; -- control fsm
|
||||
busy : std_logic; -- busy, encryption in progress
|
||||
part_no : part_no_t; -- partial word number
|
||||
cbc_fb_shr : aes_state_t; -- CBC-mode feedback shift-register
|
||||
fb_shr_src : std_logic; -- data source for fb-shr: ciphertext (0) / IV @ din (1)
|
||||
fb_shr_shift : std_logic; -- shift-data into / out of fb-shr
|
||||
key_id : key_id_t; -- stored key ID
|
||||
end record;
|
||||
|
||||
|
||||
type variables is record
|
||||
dummy : std_logic;
|
||||
end record;
|
||||
|
||||
|
||||
signal r, rin : registers;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-- combinatorial logic
|
||||
comb: process (rst, r, mode_i, enc_i)
|
||||
variable v : registers;
|
||||
variable t : variables;
|
||||
begin
|
||||
|
||||
-- assign default values
|
||||
v := r;
|
||||
--
|
||||
--
|
||||
--
|
||||
|
||||
if (r.fb_shr_shift = '1') or (enc_i.valid = '1')
|
||||
then
|
||||
v.part_no := r.part_no + 1;
|
||||
end if;
|
||||
|
||||
|
||||
-- control fsm
|
||||
case r.ctrl_fsm is
|
||||
-- wait for start / IV loading
|
||||
when cf_idle =>
|
||||
-- handle IV loading
|
||||
if (mode_i.load_iv = '1')
|
||||
then
|
||||
v.busy := '1';
|
||||
v.key_id := mode_i.key_id;
|
||||
v.fb_shr_shift := '1';
|
||||
v.part_no := "01";
|
||||
|
||||
v.ctrl_fsm := cf_load_iv;
|
||||
-- handle encryption start
|
||||
elsif (mode_i.start = '1')
|
||||
then
|
||||
v.fb_shr_src := '0'; -- use ciphertext as source
|
||||
v.fb_shr_shift := '1';
|
||||
v.part_no := "01";
|
||||
|
||||
v.ctrl_fsm := cf_load_data;
|
||||
end if;
|
||||
|
||||
-- load iv
|
||||
when cf_load_iv =>
|
||||
-- handle last input data word
|
||||
if (r.part_no = "11")
|
||||
then
|
||||
v.busy := '0';
|
||||
v.fb_shr_shift := '0'; -- partial number is hold at "00"
|
||||
|
||||
v.ctrl_fsm := cf_idle;
|
||||
end if;
|
||||
|
||||
-- load input data
|
||||
when cf_load_data =>
|
||||
-- handle last input data word
|
||||
if (r.part_no = "11")
|
||||
then
|
||||
v.fb_shr_shift := '0'; -- partial number is hold at "00"
|
||||
|
||||
v.ctrl_fsm := cf_wait_enc;
|
||||
end if;
|
||||
|
||||
-- wait while encrypting
|
||||
when cf_wait_enc =>
|
||||
if (enc_i.valid = '1')
|
||||
then
|
||||
v.part_no := "01";
|
||||
v.fb_shr_shift := '1';
|
||||
|
||||
v.ctrl_fsm := cf_out_data;
|
||||
end if;
|
||||
|
||||
-- ouput data
|
||||
when cf_out_data =>
|
||||
-- handle last output data word
|
||||
if (r.part_no = "11")
|
||||
then
|
||||
v.fb_shr_src := '1';
|
||||
v.fb_shr_shift := '0';
|
||||
|
||||
v.ctrl_fsm := cf_idle;
|
||||
end if;
|
||||
|
||||
|
||||
when others =>
|
||||
v.ctrl_fsm := cf_idle;
|
||||
|
||||
end case;
|
||||
|
||||
|
||||
-- CBC-mode feedback register operation (4x32-bit shift-register)
|
||||
if (mode_i.load_iv = '1') or (enc_i.valid = '1') or (r.fb_shr_shift = '1')
|
||||
then
|
||||
if (r.fb_shr_src = '1')
|
||||
then
|
||||
-- handle IV loading
|
||||
v.cbc_fb_shr(31 downto 0) := mode_i.din;
|
||||
else
|
||||
v.cbc_fb_shr(31 downto 0) := enc_i.cipher;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if (mode_i.start = '1') or (r.fb_shr_shift = '1')
|
||||
then
|
||||
v.cbc_fb_shr(127 downto 32) := r.cbc_fb_shr(95 downto 0);
|
||||
end if;
|
||||
|
||||
--
|
||||
--
|
||||
--
|
||||
-- reset handling
|
||||
if (rst = '1')
|
||||
then
|
||||
v.fb_shr_shift := '0';
|
||||
v.fb_shr_src := '1';
|
||||
v.part_no := "00";
|
||||
v.busy := '0';
|
||||
v.key_id := (others => '0');
|
||||
|
||||
v.ctrl_fsm := cf_idle;
|
||||
|
||||
end if;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- update registers
|
||||
rin <= v;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- drive outputs
|
||||
enc_o.start <= mode_i.start;
|
||||
enc_o.plain <= mode_i.din xor r.cbc_fb_shr(127 downto 96);
|
||||
enc_o.key_id <= r.key_id;
|
||||
|
||||
mode_o.valid <= enc_i.valid;
|
||||
mode_o.busy <= enc_i.busy or r.busy;
|
||||
mode_o.dout <= enc_i.cipher;
|
||||
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
-- registers
|
||||
regs: process (clk, rst)
|
||||
begin
|
||||
if rising_edge(clk)
|
||||
then
|
||||
r <= rin;
|
||||
end if;
|
||||
|
||||
-- async. reset
|
||||
if (rst = '1')
|
||||
then
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end behavioural;
|
||||
@@ -0,0 +1,153 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : cbc_mode_iface (interfaces of CBC-mode en-/decryption
|
||||
-- modules)
|
||||
--
|
||||
-- File Name : cbc_mode_iface.vhd
|
||||
--
|
||||
-- Purpose : The package collects type declarations for all non-
|
||||
-- trivial interfaces of used entities. Record types
|
||||
-- are used extensively to group related signals (e.g.
|
||||
-- data / control & status, physical attachment etc.).
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : aes_definitions, tech_iface, engine_iface
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : Version for implementation using 32-bit datapath
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2007-01-31 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
use work.aes_definitions.all;
|
||||
use work.tech_iface.all;
|
||||
use work.engine_iface.all;
|
||||
|
||||
|
||||
package cbc_mode_iface is
|
||||
|
||||
|
||||
--
|
||||
-- CBC-mode encryption interface definition
|
||||
--
|
||||
|
||||
|
||||
-- data/control input signals
|
||||
type cbc_mode_encryption_in_type is record
|
||||
start : std_logic; -- start encryption
|
||||
load_iv : std_logic; -- load IV
|
||||
din : part_data_t; -- IV / data to be encrypted (plaintext)
|
||||
key_id : key_id_t; -- key id to use
|
||||
end record;
|
||||
|
||||
-- data/status outputs signals
|
||||
type cbc_mode_encryption_out_type is record
|
||||
dout : part_data_t; -- encrypted data (ciphertext)
|
||||
busy : std_logic; -- busy, encrypion in progress
|
||||
valid : std_logic; -- ciphertext is valid
|
||||
end record;
|
||||
|
||||
|
||||
--
|
||||
-- CBC-mode decryption interface definition
|
||||
--
|
||||
|
||||
|
||||
-- data/control input signals
|
||||
type cbc_mode_decryption_in_type is record
|
||||
start : std_logic; -- start decryption
|
||||
load_iv : std_logic; -- load IV
|
||||
din : part_data_t; -- IV / data to be decrypted (ciphertext)
|
||||
key_id : key_id_t; -- key id to use
|
||||
end record;
|
||||
|
||||
-- data/status outputs signals
|
||||
type cbc_mode_decryption_out_type is record
|
||||
dout : part_data_t; -- decrypted data (plaintext)
|
||||
busy : std_logic; -- busy, decrypion in progress
|
||||
valid : std_logic; -- plaintext is valid
|
||||
end record;
|
||||
|
||||
|
||||
--
|
||||
--
|
||||
-- Component declarations
|
||||
--
|
||||
--
|
||||
|
||||
|
||||
-- AES CBC-mode encryption
|
||||
component cbc_mode_encryption is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in cbc_mode_encryption_in_type; -- see package cbc_mode_iface
|
||||
mode_o : out cbc_mode_encryption_out_type; -- see package cbc_mode_iface
|
||||
enc_i : in encryption_engine_out_type; -- see package engine_iface
|
||||
enc_o : out encryption_engine_in_type -- see package engine_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
|
||||
-- AES CBC-mode decryption
|
||||
component cbc_mode_decryption is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in cbc_mode_decryption_in_type; -- see package cbc_mode_iface
|
||||
mode_o : out cbc_mode_decryption_out_type; -- see package cbc_mode_iface
|
||||
dec_i : in decryption_engine_out_type; -- see package engine_iface
|
||||
dec_o : out decryption_engine_in_type -- see package engine_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
end cbc_mode_iface;
|
||||
@@ -0,0 +1,185 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : ecb_128_encryption_core (ECB-mode encryption core with
|
||||
-- 128-bit key schedule)
|
||||
--
|
||||
-- File Name : ecb_128_encryption_core.vhd
|
||||
--
|
||||
-- Purpose : The module instantiates all necessary modules (S-box
|
||||
-- stages, encryption, ECB-mode, key schedule, subkey
|
||||
-- memory etc.) to provide an ECB-mode encryption core
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : tech_iface, key_schedule_iface, engine_iface,
|
||||
-- ecb_mode_iface, ecb_core_iface
|
||||
--
|
||||
-- - Module(s) : ecb_mode_encryption, encryption_engine, tech_sbox_stage,
|
||||
-- tech_subkey_memory, key_schedule_128
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : Version for implementation using 32-bit datapath
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-15 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
|
||||
use work.tech_iface.all;
|
||||
use work.key_schedule_iface.all;
|
||||
use work.engine_iface.all;
|
||||
use work.ecb_mode_iface.all;
|
||||
use work.ecb_core_iface.all;
|
||||
|
||||
|
||||
entity ecb_128_encryption_core is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in ecb_mode_encryption_in_type; -- see package ecb_mode_iface
|
||||
mode_o : out ecb_mode_encryption_out_type; -- see package ecb_mode_iface
|
||||
key_i : in key_schedule_128_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_128_out_type; -- see package key_schedule_iface
|
||||
sbld_i : in sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end ecb_128_encryption_core;
|
||||
|
||||
|
||||
architecture behavioural of ecb_128_encryption_core is
|
||||
|
||||
|
||||
signal enc_i : encryption_engine_in_type; -- input to the encryption engine
|
||||
signal enc_o : encryption_engine_out_type; -- output of the encryption engine
|
||||
|
||||
signal sbox_enc_i : sbox_stage_in_type; -- input to the S-box stage
|
||||
signal sbox_enc_o : sbox_stage_out_type; -- output of the S-box stage
|
||||
|
||||
signal sbox_ks_i : sbox_stage_in_type; -- input to the S-box stage (key schedule)
|
||||
signal sbox_ks_o : sbox_stage_out_type; -- output of the S-box stage (key schedule)
|
||||
|
||||
signal skm_enc_i : subkey_memory_ed_in_type; -- encryption-side subkey memory access (subkey selection)
|
||||
signal skm_enc_o : subkey_memory_ed_out_type; -- encryption-side subkey memory access (selected subkey)
|
||||
|
||||
signal skm_ks_enc_i : subkey_memory_ks_in_type; -- subkey storage by key schedule
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-- AES ECB-mode encryption
|
||||
ecb_mode: ecb_mode_encryption
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
mode_i => mode_i,
|
||||
mode_o => mode_o,
|
||||
enc_i => enc_o,
|
||||
enc_o => enc_i
|
||||
);
|
||||
|
||||
|
||||
-- AES encryption engine
|
||||
enc_eng: encryption_engine
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
enc_i => enc_i,
|
||||
enc_o => enc_o,
|
||||
skm_i => skm_enc_o,
|
||||
skm_o => skm_enc_i,
|
||||
sbox_i => sbox_enc_o,
|
||||
sbox_o => sbox_enc_i
|
||||
);
|
||||
|
||||
|
||||
-- S-Box stage for encryption engine
|
||||
sbox_enc: tech_sbox_stage
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
data_i => sbox_enc_i,
|
||||
data_o => sbox_enc_o,
|
||||
load_i => sbld_i
|
||||
);
|
||||
|
||||
|
||||
-- subkey memory for encryption engine
|
||||
skm_enc: tech_subkey_memory
|
||||
port map (
|
||||
clk => clk,
|
||||
key_sched_i => skm_ks_enc_i,
|
||||
enc_dec_i => skm_enc_i,
|
||||
enc_dec_o => skm_enc_o
|
||||
);
|
||||
|
||||
|
||||
-- 128-bit key schedule
|
||||
key_sched: key_schedule_128
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
key_i => key_i,
|
||||
key_o => key_o,
|
||||
sbox_i => sbox_ks_o,
|
||||
sbox_o => sbox_ks_i,
|
||||
skm_enc_o => skm_ks_enc_i,
|
||||
skm_dec_o => open
|
||||
);
|
||||
|
||||
|
||||
-- S-Box stage for key schedule
|
||||
sbox_ks: tech_sbox_stage
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
data_i => sbox_ks_i,
|
||||
data_o => sbox_ks_o,
|
||||
load_i => sbld_i
|
||||
);
|
||||
|
||||
|
||||
end behavioural;
|
||||
+1221
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,146 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : ecb_core_iface (interfaces of ECB-mode en-/decryption
|
||||
-- cores)
|
||||
--
|
||||
-- File Name : ecb_core_iface.vhd
|
||||
--
|
||||
-- Purpose : The package collects type declarations for all non-
|
||||
-- trivial interfaces of used entities. Record types
|
||||
-- are used extensively to group related signals (e.g.
|
||||
-- data / control & status, physical attachment etc.).
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : tech_iface, key_schedule_iface, engine_iface,
|
||||
-- ecb_mode_iface
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : -
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-15 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
use work.tech_iface.all;
|
||||
use work.key_schedule_iface.all;
|
||||
use work.engine_iface.all;
|
||||
use work.ecb_mode_iface.all;
|
||||
|
||||
|
||||
package ecb_core_iface is
|
||||
|
||||
|
||||
-- no new interfaces are needed yet
|
||||
|
||||
|
||||
|
||||
--
|
||||
--
|
||||
-- Component declarations
|
||||
--
|
||||
--
|
||||
|
||||
|
||||
-- AES-ECB-128 encryption core
|
||||
component ecb_128_encryption_core is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in ecb_mode_encryption_in_type; -- see package ecb_mode_iface
|
||||
mode_o : out ecb_mode_encryption_out_type; -- see package ecb_mode_iface
|
||||
key_i : in key_schedule_128_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_128_out_type; -- see package key_schedule_iface
|
||||
sbld_i : in sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
-- AES-ECB-128 decryption core
|
||||
component ecb_128_decryption_core is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in ecb_mode_decryption_in_type; -- see package ecb_mode_iface
|
||||
mode_o : out ecb_mode_decryption_out_type; -- see package ecb_mode_iface
|
||||
key_i : in key_schedule_128_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_128_out_type; -- see package key_schedule_iface
|
||||
sbld_i : in sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
-- AES-ECB-256 encryption core
|
||||
component ecb_256_encryption_core is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in ecb_mode_encryption_in_type; -- see package ecb_mode_iface
|
||||
mode_o : out ecb_mode_encryption_out_type; -- see package ecb_mode_iface
|
||||
key_i : in key_schedule_256_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_256_out_type; -- see package key_schedule_iface
|
||||
sbld_i : in sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
-- AES-ECB-256 decryption core
|
||||
component ecb_256_decryption_core is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in ecb_mode_decryption_in_type; -- see package ecb_mode_iface
|
||||
mode_o : out ecb_mode_decryption_out_type; -- see package ecb_mode_iface
|
||||
key_i : in key_schedule_256_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_256_out_type; -- see package key_schedule_iface
|
||||
sbld_i : in sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
end ecb_core_iface;
|
||||
@@ -0,0 +1,161 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : ecb_mode_encryption (ECB-mode encryption)
|
||||
--
|
||||
-- File Name : ecb_mode_encryption.vhd
|
||||
--
|
||||
-- Purpose : The module provides ECB-mode encryption (there is no
|
||||
-- internal logic, it's just a placeholder to hold up with
|
||||
-- common infrastructure used for more complex modes)
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : engine_iface, ecb_mode_iface
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : Version for implementation using 32-bit datapath
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-02 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: two-process method (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
|
||||
use work.engine_iface.all;
|
||||
use work.ecb_mode_iface.all;
|
||||
|
||||
|
||||
entity ecb_mode_encryption is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in ecb_mode_encryption_in_type; -- see package ecb_mode_iface
|
||||
mode_o : out ecb_mode_encryption_out_type; -- see package ecb_mode_iface
|
||||
enc_i : in encryption_engine_out_type; -- see package engine_iface
|
||||
enc_o : out encryption_engine_in_type -- see package engine_iface
|
||||
);
|
||||
end ecb_mode_encryption;
|
||||
|
||||
|
||||
architecture behavioural of ecb_mode_encryption is
|
||||
|
||||
|
||||
type registers is record
|
||||
dummy : std_logic;
|
||||
end record;
|
||||
|
||||
|
||||
type variables is record
|
||||
dummy : std_logic;
|
||||
end record;
|
||||
|
||||
|
||||
signal r, rin : registers;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-- combinatorial logic
|
||||
comb: process (rst, r, mode_i, enc_i)
|
||||
variable v : registers;
|
||||
variable t : variables;
|
||||
begin
|
||||
|
||||
-- assign default values
|
||||
v := r;
|
||||
--
|
||||
--
|
||||
--
|
||||
|
||||
|
||||
|
||||
--
|
||||
--
|
||||
--
|
||||
-- reset handling
|
||||
if (rst = '1')
|
||||
then
|
||||
end if;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- update registers
|
||||
rin <= v;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- drive outputs
|
||||
enc_o.start <= mode_i.start;
|
||||
enc_o.plain <= mode_i.plain;
|
||||
enc_o.key_id <= mode_i.key_id;
|
||||
|
||||
mode_o.valid <= enc_i.valid;
|
||||
mode_o.busy <= enc_i.busy;
|
||||
mode_o.cipher <= enc_i.cipher;
|
||||
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
-- registers
|
||||
regs: process (clk, rst)
|
||||
begin
|
||||
if rising_edge(clk)
|
||||
then
|
||||
r <= rin;
|
||||
end if;
|
||||
|
||||
-- async. reset
|
||||
if (rst = '1')
|
||||
then
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end behavioural;
|
||||
@@ -0,0 +1,151 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : ecb_mode_iface (interfaces of ECB-mode en-/decryption
|
||||
-- modules)
|
||||
--
|
||||
-- File Name : ecb_mode_iface.vhd
|
||||
--
|
||||
-- Purpose : The package collects type declarations for all non-
|
||||
-- trivial interfaces of used entities. Record types
|
||||
-- are used extensively to group related signals (e.g.
|
||||
-- data / control & status, physical attachment etc.).
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : aes_definitions, tech_iface, engine_iface
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : Version for implementation using 32-bit datapath
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-15 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
use work.aes_definitions.all;
|
||||
use work.tech_iface.all;
|
||||
use work.engine_iface.all;
|
||||
|
||||
|
||||
package ecb_mode_iface is
|
||||
|
||||
|
||||
--
|
||||
-- ECB-mode encryption interface definition
|
||||
--
|
||||
|
||||
|
||||
-- data/control input signals
|
||||
type ecb_mode_encryption_in_type is record
|
||||
start : std_logic; -- start encryption
|
||||
plain : part_data_t; -- data to be encrypted (plaintext)
|
||||
key_id : key_id_t; -- key id to use
|
||||
end record;
|
||||
|
||||
-- data/status outputs signals
|
||||
type ecb_mode_encryption_out_type is record
|
||||
cipher : part_data_t; -- encrypted data (ciphertext)
|
||||
busy : std_logic; -- busy, encrypion in progress
|
||||
valid : std_logic; -- ciphertext is valid (encryption finished)
|
||||
end record;
|
||||
|
||||
|
||||
--
|
||||
-- ECB-mode decryption interface definition
|
||||
--
|
||||
|
||||
|
||||
-- data/control input signals
|
||||
type ecb_mode_decryption_in_type is record
|
||||
start : std_logic; -- start decryption
|
||||
cipher : part_data_t; -- data to be decrypted (ciphertext)
|
||||
key_id : key_id_t; -- key id to use
|
||||
end record;
|
||||
|
||||
-- data/status outputs signals
|
||||
type ecb_mode_decryption_out_type is record
|
||||
plain : part_data_t; -- decrypted data (plaintext)
|
||||
busy : std_logic; -- busy, decrypion in progress
|
||||
valid : std_logic; -- plaintext is valid (decryption finished)
|
||||
end record;
|
||||
|
||||
|
||||
--
|
||||
--
|
||||
-- Component declarations
|
||||
--
|
||||
--
|
||||
|
||||
|
||||
-- AES ECB-mode encryption
|
||||
component ecb_mode_encryption is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in ecb_mode_encryption_in_type; -- see package ecb_mode_iface
|
||||
mode_o : out ecb_mode_encryption_out_type; -- see package ecb_mode_iface
|
||||
enc_i : in encryption_engine_out_type; -- see package engine_iface
|
||||
enc_o : out encryption_engine_in_type -- see package engine_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
|
||||
-- AES ECB-mode decryption
|
||||
component ecb_mode_decryption is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
mode_i : in ecb_mode_decryption_in_type; -- see package ecb_mode_iface
|
||||
mode_o : out ecb_mode_decryption_out_type; -- see package ecb_mode_iface
|
||||
dec_i : in decryption_engine_out_type; -- see package engine_iface
|
||||
dec_o : out decryption_engine_in_type -- see package engine_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
end ecb_mode_iface;
|
||||
@@ -0,0 +1,182 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : aux_funcs (auxiliary functions)
|
||||
--
|
||||
-- File Name : aux_funcs.vhd
|
||||
--
|
||||
-- Purpose : The package collects type declarations and auxiliary
|
||||
-- functions which are commonly used by encryption,
|
||||
-- decryption and key schedule
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : aes_definitions, aes_common, aes_column_ops,
|
||||
-- aes_row_ops
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : -
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-14 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
use work.aes_definitions.all;
|
||||
use work.aes_common.all;
|
||||
use work.aes_column_ops.all;
|
||||
use work.aes_row_ops.all;
|
||||
|
||||
|
||||
package aux_funcs is
|
||||
|
||||
|
||||
subtype slv256_t is std_logic_vector(255 downto 0);
|
||||
|
||||
subtype slv32_t is std_logic_vector(31 downto 0);
|
||||
|
||||
subtype slv3_t is std_logic_vector(2 downto 0);
|
||||
|
||||
subtype slv4_t is std_logic_vector(3 downto 0);
|
||||
|
||||
subtype slv5_t is std_logic_vector(4 downto 0);
|
||||
|
||||
subtype slv13_t is std_logic_vector(12 downto 0);
|
||||
|
||||
subtype slv19_t is std_logic_vector(18 downto 0);
|
||||
|
||||
|
||||
|
||||
-- rotate left
|
||||
function rotl(val : std_logic_vector; pos : natural) return std_logic_vector;
|
||||
|
||||
-- rotate right
|
||||
function rotr(val : std_logic_vector; pos : natural) return std_logic_vector;
|
||||
|
||||
|
||||
-- convert the row representation to 32-bit logic vector
|
||||
function row2slv(row : row_t) return slv32_t;
|
||||
|
||||
|
||||
-- convert 32-bit logic vector to row representation
|
||||
function slv2row(slv : slv32_t) return row_t;
|
||||
|
||||
|
||||
-- convert the column representation to 32-bit logic vector
|
||||
function col2slv(col : column_t) return slv32_t;
|
||||
|
||||
|
||||
-- convert 32-bit logic vector to column representation
|
||||
function slv2col(slv : slv32_t) return column_t;
|
||||
|
||||
|
||||
end aux_funcs;
|
||||
|
||||
|
||||
package body aux_funcs is
|
||||
|
||||
|
||||
-- rotate left
|
||||
function rotl(val : std_logic_vector; pos : natural) return std_logic_vector is
|
||||
variable v : std_logic_vector(val'high downto 0);
|
||||
begin
|
||||
v := val;
|
||||
return v(v'left - pos downto 0) & v(v'left downto v'left - pos + 1);
|
||||
end function;
|
||||
|
||||
|
||||
-- rotate right
|
||||
function rotr(val : std_logic_vector; pos : natural) return std_logic_vector is
|
||||
variable v : std_logic_vector(val'high downto 0);
|
||||
begin
|
||||
v := val;
|
||||
return v(pos - 1 downto 0) & v(v'left downto pos);
|
||||
end function;
|
||||
|
||||
|
||||
-- convert the row representation to 32-bit logic vector
|
||||
function row2slv(row : row_t) return slv32_t is
|
||||
variable v : slv32_t;
|
||||
begin
|
||||
v := row(0) & row(1) & row(2) & row(3);
|
||||
return v;
|
||||
end function;
|
||||
|
||||
|
||||
-- convert 32-bit logic vector to row representation
|
||||
function slv2row(slv : slv32_t) return row_t is
|
||||
variable row : row_t;
|
||||
begin
|
||||
for i in row'range loop
|
||||
row(i) := slv(31 - 8*i downto 31-8*i - 7);
|
||||
end loop;
|
||||
|
||||
return row;
|
||||
end function;
|
||||
|
||||
|
||||
-- convert the column representation to 32-bit logic vector
|
||||
function col2slv(col : column_t) return slv32_t is
|
||||
variable v : slv32_t;
|
||||
begin
|
||||
v := col(0) & col(1) & col(2) & col(3);
|
||||
return v;
|
||||
end function;
|
||||
|
||||
|
||||
-- convert 32-bit logic vector to column representation
|
||||
function slv2col(slv : slv32_t) return column_t is
|
||||
variable col : column_t;
|
||||
begin
|
||||
for i in col'range loop
|
||||
col(i) := slv(31 - 8*i downto 31-8*i - 7);
|
||||
end loop;
|
||||
|
||||
return col;
|
||||
end function;
|
||||
|
||||
|
||||
end aux_funcs;
|
||||
@@ -0,0 +1,150 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : dual_sbox_virtex2 (dual AES S-box)
|
||||
--
|
||||
-- File Name : dual_sbox_virtex2.vhd
|
||||
--
|
||||
-- Purpose : The module provides dual (dual-port memory) AES S-box
|
||||
-- on Virtex2 family
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : Xilinx/unisim
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : -
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-15 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
|
||||
entity dual_sbox_virtex2 is
|
||||
port (
|
||||
clk : in std_logic; -- clock (rising)
|
||||
enca : in std_logic; -- encryption (0) / decryption (1) mode
|
||||
encb : in std_logic; -- encryption (0) / decryption (1) mode
|
||||
posa : in std_logic_vector(7 downto 0); -- position
|
||||
posb : in std_logic_vector(7 downto 0); -- position
|
||||
dina : in std_logic_vector(7 downto 0); -- write data
|
||||
dinb : in std_logic_vector(7 downto 0); -- write data
|
||||
wea : in std_logic; -- write enable
|
||||
web : in std_logic; -- write enable
|
||||
douta : out std_logic_vector(7 downto 0); -- read data
|
||||
doutb : out std_logic_vector(7 downto 0); -- read data
|
||||
is_init : out std_logic -- pre-initialised memory
|
||||
);
|
||||
end dual_sbox_virtex2;
|
||||
|
||||
|
||||
architecture behavioral of dual_sbox_virtex2 is
|
||||
|
||||
signal s_addra : std_logic_vector(10 downto 0);
|
||||
signal s_addrb : std_logic_vector(10 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
s_addra <= "00" & enca & posa;
|
||||
|
||||
s_addrb <= "00" & encb & posb;
|
||||
|
||||
|
||||
-- RAMB16_S9_S9: Virtex-II/II-Pro 2k x 8 + 1 Parity bit Dual-Port RAM
|
||||
-- Xilinx HDL Language Template version 7.1i
|
||||
|
||||
sboxd: RAMB16_S9_S9
|
||||
generic map (
|
||||
WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
||||
WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
||||
SIM_COLLISION_CHECK => "NONE", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
|
||||
INIT_00 => X"C072A49CAFA2D4ADF04759FA7DC982CA76ABD7FE2B670130C56F6BF27B777C63",
|
||||
INIT_01 => X"75B227EBE28012079A059618C323C7041531D871F1E5A534CCF73F362693FDB7",
|
||||
INIT_02 => X"CF584C4A39BECB6A5BB1FC20ED00D153842FE329B3D63B52A05A6E1B1A2C8309",
|
||||
INIT_03 => X"D2F3FF1021DAB6BCF5389D928F40A351A89F3C507F02F94585334D43FBAAEFD0",
|
||||
INIT_04 => X"DB0B5EDE14B8EE4688902A22DC4F816073195D643D7EA7C41744975FEC130CCD",
|
||||
INIT_05 => X"08AE7A65EAF4566CA94ED58D6D37C8E779E4959162ACD3C25C2406490A3A32E0",
|
||||
INIT_06 => X"9E1DC186B95735610EF6034866B53E708A8BBD4B1F74DDE8C6B4A61C2E2578BA",
|
||||
INIT_07 => X"16BB54B00F2D99416842E6BF0D89A18CDF2855CEE9871E9B948ED9691198F8E1",
|
||||
INIT_08 => X"CBE9DEC444438E3487FF2F9B8239E37CFBD7F3819EA340BF38A53630D56A0952",
|
||||
INIT_09 => X"25D18B6D49A25B76B224D92866A12E084EC3FA420B954CEE3D23C2A632947B54",
|
||||
INIT_0A => X"849D8DA75746155EDAB9EDFD5048706C92B6655DCC5CA4D41698688664F6F872",
|
||||
INIT_0B => X"6B8A130103BDAFC1020F3FCA8F1E2CD00645B3B80558E4F70AD3BC8C00ABD890",
|
||||
INIT_0C => X"6EDF751CE837F9E28535ADE72274AC9673E6B4F0CECFF297EADC674F4111913A",
|
||||
INIT_0D => X"F45ACD78FEC0DB9A2079D2C64B3E56FC1BBE18AA0E62B76F89C5291D711AF147",
|
||||
INIT_0E => X"EF9CC9939F7AE52D0D4AB519A97F51605FEC8027591012B131C7078833A8DD1F",
|
||||
INIT_0F => X"7D0C2155631469E126D677BA7E042B17619953833CBBEBC8B0F52AAE4D3BE0A0"
|
||||
)
|
||||
port map (
|
||||
DOA => douta(7 downto 0), -- Port A 8-bit Data Output
|
||||
DOB => doutb(7 downto 0), -- Port B 8-bit Data Output
|
||||
DOPA => open, -- Port A 1-bit Parity Output
|
||||
DOPB => open, -- Port B 1-bit Parity Output
|
||||
ADDRA => s_addra, -- Port A 11-bit Address Input
|
||||
ADDRB => s_addrb, -- Port B 11-bit Address Input
|
||||
CLKA => clk, -- Port A Clock
|
||||
CLKB => clk, -- Port B Clock
|
||||
DIA => dina(7 downto 0), -- Port A 8-bit Data Input
|
||||
DIB => dinb(7 downto 0), -- Port B 8-bit Data Input
|
||||
DIPA => "0", -- Port A 1-bit parity Input
|
||||
DIPB => "0", -- Port-B 1-bit parity Input
|
||||
ENA => '1', -- Port A RAM Enable Input
|
||||
ENB => '1', -- Port B RAM Enable Input
|
||||
SSRA => '0', -- Port A Synchronous Set/Reset Input
|
||||
SSRB => '0', -- Port B Synchronous Set/Reset Input
|
||||
WEA => wea, -- Port A Write Enable Input
|
||||
WEB => web -- Port B Write Enable Input
|
||||
);
|
||||
|
||||
|
||||
is_init <= '1';
|
||||
|
||||
|
||||
end behavioral;
|
||||
@@ -0,0 +1,207 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : dual_sbox_virtex2 (dual AES S-box)
|
||||
--
|
||||
-- File Name : dual_sbox_virtex2_empty.vhd
|
||||
--
|
||||
-- Purpose : The module provides dual (dual-port memory) AES S-box
|
||||
-- on Virtex2 family
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : Xilinx/unisim
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : the S-box in not pre-initialized to allow testing
|
||||
-- of S-box load I/F
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-15 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
|
||||
entity dual_sbox_virtex2 is
|
||||
port (
|
||||
clk : in std_logic; -- clock (rising)
|
||||
enca : in std_logic; -- encryption (0) / decryption (1) mode
|
||||
encb : in std_logic; -- encryption (0) / decryption (1) mode
|
||||
posa : in std_logic_vector(7 downto 0); -- position
|
||||
posb : in std_logic_vector(7 downto 0); -- position
|
||||
dina : in std_logic_vector(7 downto 0); -- write data
|
||||
dinb : in std_logic_vector(7 downto 0); -- write data
|
||||
wea : in std_logic; -- write enable
|
||||
web : in std_logic; -- write enable
|
||||
douta : out std_logic_vector(7 downto 0); -- read data
|
||||
doutb : out std_logic_vector(7 downto 0); -- read data
|
||||
is_init : out std_logic -- pre-initialised memory
|
||||
);
|
||||
end dual_sbox_virtex2;
|
||||
|
||||
|
||||
architecture behavioral of dual_sbox_virtex2 is
|
||||
|
||||
signal s_addra : std_logic_vector(10 downto 0);
|
||||
signal s_addrb : std_logic_vector(10 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
s_addra <= "00" & enca & posa;
|
||||
|
||||
s_addrb <= "00" & encb & posb;
|
||||
|
||||
|
||||
-- RAMB16_S9_S9: Virtex-II/II-Pro 2k x 8 + 1 Parity bit Dual-Port RAM
|
||||
-- Xilinx HDL Language Template version 7.1i
|
||||
|
||||
sboxd: RAMB16_S9_S9
|
||||
generic map (
|
||||
WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
||||
WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
||||
SIM_COLLISION_CHECK => "NONE", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
|
||||
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
|
||||
)
|
||||
port map (
|
||||
DOA => douta(7 downto 0), -- Port A 8-bit Data Output
|
||||
DOB => doutb(7 downto 0), -- Port B 8-bit Data Output
|
||||
DOPA => open, -- Port A 1-bit Parity Output
|
||||
DOPB => open, -- Port B 1-bit Parity Output
|
||||
ADDRA => s_addra, -- Port A 11-bit Address Input
|
||||
ADDRB => s_addrb, -- Port B 11-bit Address Input
|
||||
CLKA => clk, -- Port A Clock
|
||||
CLKB => clk, -- Port B Clock
|
||||
DIA => dina(7 downto 0), -- Port A 8-bit Data Input
|
||||
DIB => dinb(7 downto 0), -- Port B 8-bit Data Input
|
||||
DIPA => "0", -- Port A 1-bit parity Input
|
||||
DIPB => "0", -- Port-B 1-bit parity Input
|
||||
ENA => '1', -- Port A RAM Enable Input
|
||||
ENB => '1', -- Port B RAM Enable Input
|
||||
SSRA => '0', -- Port A Synchronous Set/Reset Input
|
||||
SSRB => '0', -- Port B Synchronous Set/Reset Input
|
||||
WEA => wea, -- Port A Write Enable Input
|
||||
WEB => web -- Port B Write Enable Input
|
||||
);
|
||||
|
||||
|
||||
is_init <= '0';
|
||||
|
||||
|
||||
end behavioral;
|
||||
@@ -0,0 +1,345 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : encryption_engine (AES encryption engine)
|
||||
--
|
||||
-- File Name : encryption_engine.vhd
|
||||
--
|
||||
-- Purpose : The module provides encryption functionality (ECB-Mode)
|
||||
-- based on AES algorithm by using ressource sharing
|
||||
-- architecture (32-bit datapath) to reduce required area
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : aes_definitions, aes_common, aes_column_ops,
|
||||
-- aes_row_ops, aes_common, aes_encryption, tech_iface,
|
||||
-- engine_iface
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : - requires external S-box stage and subkey memory
|
||||
-- - number of rounds is obtained from the subkey memory
|
||||
-- (set by key schedule) and should be valid when the
|
||||
-- first subkey is read
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-15 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: two-process method (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
|
||||
use work.aes_definitions.all;
|
||||
use work.aes_common.all;
|
||||
use work.aes_column_ops.all;
|
||||
use work.aes_row_ops.all;
|
||||
use work.aes_common.all;
|
||||
use work.aes_encryption.all;
|
||||
|
||||
use work.tech_iface.all;
|
||||
use work.engine_iface.all;
|
||||
use work.aux_funcs.all;
|
||||
|
||||
|
||||
entity encryption_engine is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
enc_i : in encryption_engine_in_type; -- see package engine_iface
|
||||
enc_o : out encryption_engine_out_type; -- see package engine_iface
|
||||
skm_i : in subkey_memory_ed_out_type; -- see package tech_iface
|
||||
skm_o : out subkey_memory_ed_in_type; -- see package tech_iface
|
||||
sbox_i : in sbox_stage_out_type; -- see package tech_iface
|
||||
sbox_o : out sbox_stage_in_type -- see package tech_iface
|
||||
);
|
||||
end encryption_engine;
|
||||
|
||||
|
||||
architecture behavioural of encryption_engine is
|
||||
|
||||
|
||||
-- control fsm, states: idle / load input data / shift-rows / sub-bytes + mix-column + add-key
|
||||
type ctrl_fsm_t is (cf_idle, cf_load, cf_sr, cf_sb_mc_ak);
|
||||
|
||||
|
||||
type registers is record
|
||||
busy : std_logic; -- busy, encryption in progress
|
||||
valid : std_logic; -- ciphertext is valid
|
||||
ctrl_fsm : ctrl_fsm_t; -- control fsm
|
||||
key_id : key_id_t; -- stored key id
|
||||
subkey_no : aes_round_no_t; -- subkey number (round number)
|
||||
part_no : part_no_t; -- partinal number of subkey (# of 32-bit slice within subkey)
|
||||
inc_part_no : std_logic; -- increment partial number
|
||||
state : aes_state_t; -- state matrix
|
||||
rounds : aes_round_no_t; -- stored number of rounds
|
||||
din_sel : std_logic; -- input data select (0 : process data, 1 : load data)
|
||||
sb_mx_sel : std_logic; -- select SubBytes() + MixColumn() path
|
||||
act_sbox : std_logic; -- activate S-box stage (to suppress simulation warnings on Actel)
|
||||
shift_rows : std_logic; -- perform ShiftRows() on state matrix
|
||||
end record;
|
||||
|
||||
|
||||
type variables is record
|
||||
key_id : key_id_t;
|
||||
sbox_dout : part_data_t;
|
||||
end record;
|
||||
|
||||
|
||||
signal r, rin : registers;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-- combinatorial logic
|
||||
comb: process (rst, r, enc_i, skm_i, sbox_i)
|
||||
variable v : registers;
|
||||
variable t : variables;
|
||||
begin
|
||||
|
||||
-- assign default values
|
||||
v := r;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- strobes
|
||||
v.shift_rows := '0';
|
||||
|
||||
|
||||
|
||||
if (r.inc_part_no = '1')
|
||||
then
|
||||
v.part_no := r.part_no + 1;
|
||||
end if;
|
||||
|
||||
-- count-up subkey # (round #)
|
||||
if (r.part_no = "11")
|
||||
then
|
||||
v.subkey_no := r.subkey_no + 1;
|
||||
end if;
|
||||
|
||||
|
||||
t.sbox_dout := (others => '-');
|
||||
|
||||
-- transform state matrix
|
||||
if (r.shift_rows = '1')
|
||||
then
|
||||
-- perform ShiftRows() (followed by one column-rotation step)
|
||||
v.state := shift_rows(r.state);
|
||||
v.state := v.state(95 downto 0) & (31 downto 0 => '-'); -- avoid unnecessary logic
|
||||
t.sbox_dout := col2slv(select_column(shift_rows(r.state), 0));
|
||||
else
|
||||
-- rotate column-weise
|
||||
if (r.sb_mx_sel = '0')
|
||||
then
|
||||
-- bypass SubBytes() and MixColumns() during loading
|
||||
v.state(31 downto 0) := r.state(127 downto 96) xor skm_i.subkey;
|
||||
else
|
||||
v.state(31 downto 0) := col2slv(mix_column(slv2col(sbox_i.dout))) xor skm_i.subkey;
|
||||
end if;
|
||||
v.state(127 downto 32) := r.state(95 downto 0);
|
||||
t.sbox_dout := col2slv(select_column(r.state, 0));
|
||||
end if;
|
||||
|
||||
-- shift-in input data
|
||||
if (r.din_sel = '1')
|
||||
then
|
||||
v.state(127 downto 96) := enc_i.plain;
|
||||
end if;
|
||||
|
||||
|
||||
-- control fsm
|
||||
case r.ctrl_fsm is
|
||||
-- wait for start
|
||||
when cf_idle =>
|
||||
v.sb_mx_sel := '0'; -- bypass SubBytes() + MixColumn()
|
||||
|
||||
-- handle loading
|
||||
if (enc_i.start = '1')
|
||||
then
|
||||
v.busy := '1';
|
||||
v.key_id := enc_i.key_id; -- store key-id
|
||||
v.part_no := "01"; -- consider synchronous subkey memory
|
||||
v.inc_part_no := '1'; -- allow part_no to increment
|
||||
|
||||
v.ctrl_fsm := cf_load;
|
||||
end if;
|
||||
|
||||
-- load input data
|
||||
when cf_load =>
|
||||
-- prepare to handle last input data word
|
||||
if (r.part_no = "11")
|
||||
then
|
||||
v.din_sel := '0';
|
||||
v.inc_part_no := '0'; -- hold partial number at "00"
|
||||
v.rounds := skm_i.rounds;
|
||||
end if;
|
||||
|
||||
-- finish loading
|
||||
if (r.din_sel = '0')
|
||||
then
|
||||
v.act_sbox := '1'; -- activate S-box stage
|
||||
v.sb_mx_sel := '1'; -- enable SubBytes() + MixColumn() path
|
||||
-- r.part_no is automatically set to "00" (wrap-around)
|
||||
v.shift_rows := '1';
|
||||
v.inc_part_no := '1'; -- re-activate partial number counting
|
||||
|
||||
v.ctrl_fsm := cf_sr;
|
||||
end if;
|
||||
|
||||
-- perform ShiftRows()
|
||||
when cf_sr =>
|
||||
-- check for last round
|
||||
if (r.subkey_no = r.rounds)
|
||||
then
|
||||
v.sb_mx_sel := '0'; -- bypass SubBytes() + MixColumn()
|
||||
v.valid := '1'; -- start output of encrypted data
|
||||
end if;
|
||||
|
||||
v.ctrl_fsm := cf_sb_mc_ak;
|
||||
|
||||
-- perform SubBytes(), MixColumn() and AddRoundKey()
|
||||
when cf_sb_mc_ak =>
|
||||
-- one clock cycle before completion
|
||||
if (r.part_no = "11")
|
||||
then
|
||||
v.inc_part_no := '0'; -- hold partial number at "00"
|
||||
v.act_sbox := '0'; -- deactivate S-box stage
|
||||
end if;
|
||||
|
||||
-- column-wise rotation completed
|
||||
if (r.act_sbox = '0')
|
||||
then
|
||||
-- check for last round
|
||||
if (r.sb_mx_sel = '0')
|
||||
then
|
||||
v.subkey_no := (others => '0'); -- consider synchronous subkey memory
|
||||
-- r.part_no is held at "00"
|
||||
v.din_sel := '1'; -- activate input data load mode
|
||||
v.busy := '0';
|
||||
v.valid := '0'; -- stop output of encrypted data
|
||||
|
||||
v.ctrl_fsm := cf_idle;
|
||||
else
|
||||
v.act_sbox := '1'; -- re-activate S-box stage
|
||||
v.inc_part_no := '1'; -- re-activate partial number counting
|
||||
v.shift_rows := '1';
|
||||
|
||||
v.ctrl_fsm := cf_sr;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
v.ctrl_fsm := cf_idle;
|
||||
|
||||
end case;
|
||||
|
||||
|
||||
-- handle start signal (synchronous subkey memory)
|
||||
if (enc_i.start = '1')
|
||||
then
|
||||
t.key_id := enc_i.key_id;
|
||||
else
|
||||
t.key_id := r.key_id;
|
||||
end if;
|
||||
|
||||
--
|
||||
--
|
||||
--
|
||||
-- reset handling
|
||||
if (rst = '1')
|
||||
then
|
||||
v.ctrl_fsm := cf_idle;
|
||||
v.rounds := (others => '0');
|
||||
v.key_id := (others => '0');
|
||||
v.subkey_no := (others => '0');
|
||||
v.part_no := (others => '0');
|
||||
v.busy := '0';
|
||||
v.valid := '0';
|
||||
v.inc_part_no := '0';
|
||||
v.din_sel := '1';
|
||||
v.act_sbox := '0';
|
||||
end if;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- update registers
|
||||
rin <= v;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- drive outputs
|
||||
enc_o.valid <= r.valid;
|
||||
enc_o.busy <= r.busy or (not sbox_i.ready);
|
||||
enc_o.cipher <= sbox_i.dout xor skm_i.subkey;
|
||||
|
||||
skm_o.rd_en <= enc_i.start or r.busy;
|
||||
skm_o.subkey_no <= r.subkey_no;
|
||||
skm_o.part_no <= r.part_no;
|
||||
skm_o.key_id <= t.key_id;
|
||||
|
||||
sbox_o.act <= r.act_sbox;
|
||||
sbox_o.din <= t.sbox_dout;
|
||||
sbox_o.ed_mode <= '0';
|
||||
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
-- registers
|
||||
regs: process (clk, rst)
|
||||
begin
|
||||
if rising_edge(clk)
|
||||
then
|
||||
r <= rin;
|
||||
end if;
|
||||
|
||||
-- async. reset
|
||||
if (rst = '1')
|
||||
then
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end behavioural;
|
||||
@@ -0,0 +1,152 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : engine_iface (interfaces of en-/decryption engines)
|
||||
--
|
||||
-- File Name : engine_iface.vhd
|
||||
--
|
||||
-- Purpose : The package collects type declarations for all non-
|
||||
-- trivial interfaces of used entities. Record types
|
||||
-- are used extensively to group related signals (e.g.
|
||||
-- data / control & status, physical attachment etc.).
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : tech_iface
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : -
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-15 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
use work.tech_iface.all;
|
||||
|
||||
|
||||
package engine_iface is
|
||||
|
||||
|
||||
--
|
||||
-- encryption engine interface definition
|
||||
--
|
||||
|
||||
|
||||
-- data/control input signals
|
||||
type encryption_engine_in_type is record
|
||||
start : std_logic; -- start encryption
|
||||
plain : part_data_t; -- data to be encrypted (plaintext)
|
||||
key_id : key_id_t; -- key id to use
|
||||
end record;
|
||||
|
||||
-- data/status outputs signals
|
||||
type encryption_engine_out_type is record
|
||||
cipher : part_data_t; -- encrypted data (ciphertext)
|
||||
busy : std_logic; -- busy, encrypion in progress
|
||||
valid : std_logic; -- ciphertext is valid (encryption finished)
|
||||
end record;
|
||||
|
||||
|
||||
--
|
||||
-- decryption engine interface definition
|
||||
--
|
||||
|
||||
|
||||
-- data/control input signals
|
||||
type decryption_engine_in_type is record
|
||||
start : std_logic; -- start decryption
|
||||
cipher : part_data_t; -- data to be decrypted (ciphertext)
|
||||
key_id : key_id_t; -- key id to use
|
||||
end record;
|
||||
|
||||
-- data/status outputs signals
|
||||
type decryption_engine_out_type is record
|
||||
plain : part_data_t; -- decrypted data (plaintext)
|
||||
busy : std_logic; -- busy, decrypion in progress
|
||||
valid : std_logic; -- plaintext is valid (decryption finished)
|
||||
end record;
|
||||
|
||||
|
||||
--
|
||||
--
|
||||
-- Component declarations
|
||||
--
|
||||
--
|
||||
|
||||
|
||||
-- AES encryption engine
|
||||
component encryption_engine is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
enc_i : in encryption_engine_in_type; -- see package engine_iface
|
||||
enc_o : out encryption_engine_out_type; -- see package engine_iface
|
||||
skm_i : in subkey_memory_ed_out_type; -- see package tech_iface
|
||||
skm_o : out subkey_memory_ed_in_type; -- see package tech_iface
|
||||
sbox_i : in sbox_stage_out_type; -- see package tech_iface
|
||||
sbox_o : out sbox_stage_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
|
||||
-- AES decryption engine
|
||||
component decryption_engine is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
dec_i : in decryption_engine_in_type; -- see package engine_iface
|
||||
dec_o : out decryption_engine_out_type; -- see package engine_iface
|
||||
skm_i : in subkey_memory_ed_out_type; -- see package tech_iface
|
||||
skm_o : out subkey_memory_ed_in_type; -- see package tech_iface
|
||||
sbox_i : in sbox_stage_out_type; -- see package tech_iface
|
||||
sbox_o : out sbox_stage_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
end engine_iface;
|
||||
@@ -0,0 +1,282 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : key_schedule_128 (AES 128-bit key schdeule)
|
||||
--
|
||||
-- File Name : key_schedule_128.vhd
|
||||
--
|
||||
-- Purpose : The module provides key expansion/subkey generaion
|
||||
-- functionality for AES algorithm by using ressource
|
||||
-- sharing architecture (32-bit datapath) to reduce
|
||||
-- required area
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : aes_definitions, aes_gf_2exp8_arith, tech_iface,
|
||||
-- key_schedule_iface, aux_funcs
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : requires external S-box stage and subkey memory
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-14 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: two-process method (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
|
||||
use work.aes_definitions.all;
|
||||
use work.aes_gf_2exp8_arith.all;
|
||||
|
||||
use work.tech_iface.all;
|
||||
use work.key_schedule_iface.all;
|
||||
use work.aux_funcs.all;
|
||||
|
||||
|
||||
entity key_schedule_128 is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
key_i : in key_schedule_128_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_128_out_type; -- see package key_schedule_iface
|
||||
sbox_i : in sbox_stage_out_type; -- see package tech_iface
|
||||
sbox_o : out sbox_stage_in_type; -- see package tech_iface
|
||||
skm_enc_o : out subkey_memory_ks_in_type; -- see package tech_iface
|
||||
skm_dec_o : out subkey_memory_ks_in_type -- see package tech_iface
|
||||
);
|
||||
end key_schedule_128;
|
||||
|
||||
|
||||
architecture behavioural of key_schedule_128 is
|
||||
|
||||
|
||||
-- control fsm, states: idle / load key / expand key
|
||||
type ctrl_fsm_t is (cf_idle, cf_load, cf_expand);
|
||||
|
||||
type registers is record
|
||||
busy : std_logic; -- busy, key expansion in progress
|
||||
sk_slide : aes_state_t; -- sliding subkey register
|
||||
key_id : key_id_t; -- stored key id
|
||||
enc_sk_no : aes_round_no_t; -- encryption subkey number
|
||||
dec_sk_no : aes_round_no_t; -- decryption subkey number
|
||||
part_no : part_no_t; -- number of 32-bit slice within subkey
|
||||
rconst : gf_2exp8_t; -- round "constant"
|
||||
ctrl_fsm : ctrl_fsm_t; -- control fsm
|
||||
din_sel : std_logic; -- input data select (0 : input data, 1 : processing)
|
||||
sbox_sel : std_logic; -- select S-box path
|
||||
end record;
|
||||
|
||||
|
||||
type variables is record
|
||||
sbox_dout : std_logic_vector(sbox_o.din'range); -- input data to the S-box stage
|
||||
end record;
|
||||
|
||||
|
||||
signal r, rin : registers;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-- combinatorial logic
|
||||
comb: process (rst, r, key_i, sbox_i)
|
||||
variable v : registers;
|
||||
variable t : variables;
|
||||
|
||||
begin
|
||||
-- assign default values
|
||||
v := r;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- strobes
|
||||
v.sbox_sel := '0';
|
||||
|
||||
|
||||
-- count-up (down) subkey # / round constant / subkey / etc.
|
||||
if (r.busy = '1')
|
||||
then
|
||||
v.part_no := r.part_no + 1;
|
||||
|
||||
if (r.part_no = "10")
|
||||
then
|
||||
v.sbox_sel := '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
-- count-up (down) subkey # / round constant / subkey / etc.
|
||||
if (r.sbox_sel = '1')
|
||||
then
|
||||
v.enc_sk_no := r.enc_sk_no + 1;
|
||||
v.dec_sk_no := r.dec_sk_no - 1;
|
||||
v.rconst := mul_gf_2exp8(r.rconst, X"02");
|
||||
end if;
|
||||
|
||||
|
||||
|
||||
|
||||
v.sk_slide(127 downto 32) := r.sk_slide(95 downto 0);
|
||||
|
||||
if (r.din_sel = '0')
|
||||
then
|
||||
-- shift-in input data
|
||||
v.sk_slide(31 downto 0) := key_i.key;
|
||||
t.sbox_dout := rotl(key_i.key, 8);
|
||||
else
|
||||
if (r.sbox_sel = '1')
|
||||
then
|
||||
v.sk_slide(31 downto 0) := sbox_i.dout xor (r.rconst & X"000000") xor r.sk_slide(127 downto 96);
|
||||
else
|
||||
v.sk_slide(31 downto 0) := r.sk_slide(31 downto 0) xor r.sk_slide(127 downto 96);
|
||||
end if;
|
||||
t.sbox_dout := rotl(r.sk_slide(31 downto 0) xor r.sk_slide(127 downto 96), 8);
|
||||
end if;
|
||||
|
||||
|
||||
-- control fsm
|
||||
case r.ctrl_fsm is
|
||||
when cf_idle =>
|
||||
v.part_no := (others => '0');
|
||||
v.enc_sk_no := (others => '0');
|
||||
v.dec_sk_no := conv_std_logic_vector(AES_128_ROUNDS, skm_enc_o.rounds'length);
|
||||
v.rconst := X"01";
|
||||
|
||||
-- handle key loading
|
||||
if (key_i.load_key = '1')
|
||||
then
|
||||
v.busy := '1';
|
||||
v.key_id := key_i.key_id;
|
||||
|
||||
v.ctrl_fsm := cf_load;
|
||||
end if;
|
||||
|
||||
when cf_load =>
|
||||
-- handle last input word
|
||||
if (r.part_no = "10")
|
||||
then
|
||||
v.din_sel := '1'; -- switch to processing data
|
||||
|
||||
v.ctrl_fsm := cf_expand;
|
||||
end if;
|
||||
|
||||
when cf_expand =>
|
||||
if (r.part_no = "11") and (r.enc_sk_no = AES_128_ROUNDS)
|
||||
then
|
||||
v.din_sel := '0';
|
||||
v.busy := '0';
|
||||
|
||||
v.ctrl_fsm := cf_idle;
|
||||
end if;
|
||||
|
||||
|
||||
when others =>
|
||||
v.ctrl_fsm := cf_idle;
|
||||
end case;
|
||||
|
||||
--
|
||||
--
|
||||
--
|
||||
-- reset handling
|
||||
if (rst = '1')
|
||||
then
|
||||
v.ctrl_fsm := cf_idle;
|
||||
v.din_sel := '0';
|
||||
v.sbox_sel := '0';
|
||||
v.busy := '0';
|
||||
v.key_id := (others => '0');
|
||||
v.enc_sk_no := (others => '0');
|
||||
v.dec_sk_no := conv_std_logic_vector(AES_128_ROUNDS, skm_enc_o.rounds'length);
|
||||
v.part_no := (others => '0');
|
||||
end if;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- update registers
|
||||
rin <= v;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- drive outputs
|
||||
key_o.busy <= r.busy or (not sbox_i.ready);
|
||||
|
||||
sbox_o.act <= r.busy;
|
||||
sbox_o.din <= t.sbox_dout;
|
||||
sbox_o.ed_mode <= '0';
|
||||
|
||||
skm_enc_o.subkey_no <= r.enc_sk_no;
|
||||
skm_enc_o.part_no <= r.part_no;
|
||||
skm_enc_o.subkey <= r.sk_slide(31 downto 0);
|
||||
skm_enc_o.rounds <= conv_std_logic_vector(AES_128_ROUNDS, skm_enc_o.rounds'length);
|
||||
skm_enc_o.key_id <= r.key_id;
|
||||
skm_enc_o.write_en <= r.busy;
|
||||
|
||||
skm_dec_o.subkey_no <= r.dec_sk_no;
|
||||
skm_dec_o.part_no <= r.part_no;
|
||||
skm_dec_o.subkey <= r.sk_slide(31 downto 0);
|
||||
skm_dec_o.rounds <= conv_std_logic_vector(AES_128_ROUNDS, skm_enc_o.rounds'length);
|
||||
skm_dec_o.key_id <= r.key_id;
|
||||
skm_dec_o.write_en <= r.busy;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
-- registers
|
||||
regs: process (clk, rst)
|
||||
begin
|
||||
if rising_edge(clk)
|
||||
then
|
||||
r <= rin;
|
||||
end if;
|
||||
|
||||
-- async. reset
|
||||
if (rst = '1')
|
||||
then
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end behavioural;
|
||||
@@ -0,0 +1,151 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : key_schedule_iface (interfaces of 128-bit and 256-bit
|
||||
-- key schedule)
|
||||
--
|
||||
-- File Name : key_schedule_iface.vhd
|
||||
--
|
||||
-- Purpose : The package collects type declarations for all non-
|
||||
-- trivial interfaces of used entities. Record types
|
||||
-- are used extensively to group related signals (e.g.
|
||||
-- data / control & status, physical attachment etc.).
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : aes_definitions, tech_iface
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : Version for implementation using 32-bit datapath
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-14 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
use work.aes_definitions.all;
|
||||
use work.tech_iface.all;
|
||||
|
||||
|
||||
package key_schedule_iface is
|
||||
|
||||
|
||||
--
|
||||
-- 256-bit key schedule interface definition
|
||||
--
|
||||
|
||||
|
||||
-- key/control input signals
|
||||
type key_schedule_256_in_type is record
|
||||
load_key : std_logic; -- load key / start expansion
|
||||
key : part_data_t; -- encryption/decryption key
|
||||
key_id : key_id_t; -- key id to use
|
||||
end record;
|
||||
|
||||
|
||||
-- status output signals
|
||||
type key_schedule_256_out_type is record
|
||||
busy : std_logic; -- busy, key expansion in progress
|
||||
end record;
|
||||
|
||||
|
||||
--
|
||||
-- 128-bit key schedule interface definition
|
||||
--
|
||||
|
||||
|
||||
-- key/control input signals
|
||||
type key_schedule_128_in_type is record
|
||||
load_key : std_logic; -- load key / start expansion
|
||||
key : part_data_t; -- encryption/decryption key
|
||||
key_id : key_id_t; -- key id to use
|
||||
end record;
|
||||
|
||||
|
||||
-- status output signals
|
||||
type key_schedule_128_out_type is record
|
||||
busy : std_logic; -- busy, key expansion in progress
|
||||
end record;
|
||||
|
||||
|
||||
--
|
||||
--
|
||||
-- Component declarations
|
||||
--
|
||||
--
|
||||
|
||||
|
||||
-- 256-bit key schedule
|
||||
component key_schedule_256 is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
key_i : in key_schedule_256_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_256_out_type; -- see package key_schedule_iface
|
||||
sbox_i : in sbox_stage_out_type; -- see package tech_iface
|
||||
sbox_o : out sbox_stage_in_type; -- see package tech_iface
|
||||
skm_enc_o : out subkey_memory_ks_in_type; -- see package tech_iface
|
||||
skm_dec_o : out subkey_memory_ks_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
-- 128-bit key schedule
|
||||
component key_schedule_128 is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
key_i : in key_schedule_128_in_type; -- see package key_schedule_iface
|
||||
key_o : out key_schedule_128_out_type; -- see package key_schedule_iface
|
||||
sbox_i : in sbox_stage_out_type; -- see package tech_iface
|
||||
sbox_o : out sbox_stage_in_type; -- see package tech_iface
|
||||
skm_enc_o : out subkey_memory_ks_in_type; -- see package tech_iface
|
||||
skm_dec_o : out subkey_memory_ks_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
end key_schedule_iface;
|
||||
@@ -0,0 +1,197 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : tech_iface
|
||||
--
|
||||
-- File Name : tech_iface_virtex2.vhd
|
||||
--
|
||||
-- Purpose : The package collects type declarations for all non-
|
||||
-- trivial interfaces of used entities. Record types
|
||||
-- are used extensively to group related signals (e.g.
|
||||
-- data / control & status, physical attachment etc.).
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : aes_definitions
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : -
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-15 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - coding style: record-signals for related purposes (Gaisler-style)
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
use work.aes_definitions.all;
|
||||
|
||||
|
||||
package tech_iface is
|
||||
|
||||
|
||||
-- architecture-dependent key-id size (matching Virtex-II BlockRAM size)
|
||||
subtype key_id_t is std_logic_vector(2 downto 0);
|
||||
|
||||
|
||||
-- number of 32-bit slice within subkey
|
||||
subtype part_no_t is std_logic_vector(1 downto 0);
|
||||
|
||||
-- 32-bit slice of 128-bit data block
|
||||
subtype part_data_t is std_logic_vector(31 downto 0);
|
||||
|
||||
-- 32-bit slice of 128-bit subkey
|
||||
subtype part_subkey_t is std_logic_vector(31 downto 0);
|
||||
|
||||
|
||||
--
|
||||
-- S-box stage interface definition (32-bit version, 2x7-bit + 2x9-bit, mapping as required by KS-128)
|
||||
--
|
||||
|
||||
|
||||
-- s-box stage input signals
|
||||
type sbox_stage_in_type is record
|
||||
act : std_logic; -- read-enable control (to suppress simulation warnings)
|
||||
din : part_data_t; -- S-box input data
|
||||
ed_mode : std_logic; -- encryption (0) / decryption (1) mode
|
||||
end record;
|
||||
|
||||
|
||||
-- s-box stage load input signals
|
||||
type sbox_stage_load_in_type is record
|
||||
act : std_logic; -- activate load I/F
|
||||
ed_mode : std_logic; -- encryption (0) / decryption (1) mode
|
||||
pos : aes_sbox_8_t; -- position
|
||||
din : aes_sbox_8_t; -- new value
|
||||
wen : std_logic; -- write enable
|
||||
done : std_logic; -- S-box loading done
|
||||
end record;
|
||||
|
||||
|
||||
-- s-box stage outputs signals
|
||||
type sbox_stage_out_type is record
|
||||
dout : part_data_t; -- S-box output data
|
||||
ready : std_logic; -- S-box stage is ready
|
||||
end record;
|
||||
|
||||
|
||||
--
|
||||
-- subkey memory interface definition (32-bit version)
|
||||
--
|
||||
|
||||
|
||||
-- key-schedule - side input signals
|
||||
type subkey_memory_ks_in_type is record
|
||||
write_en : std_logic; -- write enable
|
||||
key_id : key_id_t; -- key id to use
|
||||
subkey_no : aes_round_no_t; -- subkey number
|
||||
part_no : part_no_t; -- 32-bit slice number
|
||||
subkey : part_subkey_t; -- subkey
|
||||
rounds : aes_round_no_t; -- number of rounds
|
||||
end record;
|
||||
|
||||
|
||||
-- key-schedule - side output signals
|
||||
type subkey_memory_ks_out_type is record
|
||||
dummy : std_logic;
|
||||
end record;
|
||||
|
||||
|
||||
-- encryption/decryption - side input signals
|
||||
type subkey_memory_ed_in_type is record
|
||||
rd_en : std_logic; -- read-enable control (to suppress simulation warnings)
|
||||
subkey_no : aes_round_no_t; -- subkey number
|
||||
part_no : part_no_t; -- 32-bit slice number
|
||||
key_id : key_id_t; -- key id to use
|
||||
end record;
|
||||
|
||||
|
||||
-- encryption/decryption - side output signals
|
||||
type subkey_memory_ed_out_type is record
|
||||
subkey : part_subkey_t; -- subkey
|
||||
rounds : aes_round_no_t; -- number of rounds
|
||||
end record;
|
||||
|
||||
|
||||
--
|
||||
--
|
||||
-- Component declarations
|
||||
--
|
||||
--
|
||||
|
||||
|
||||
-- S-Box stage
|
||||
component tech_sbox_stage is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
data_i : in sbox_stage_in_type; -- see package tech_iface
|
||||
data_o : out sbox_stage_out_type; -- see package tech_iface
|
||||
load_i : in sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
-- subkey memory
|
||||
component tech_subkey_memory is
|
||||
port (
|
||||
clk : in std_logic; -- clock
|
||||
key_sched_i : in subkey_memory_ks_in_type; -- see package tech_iface
|
||||
enc_dec_i : in subkey_memory_ed_in_type; -- see package tech_iface
|
||||
enc_dec_o : out subkey_memory_ed_out_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
-- S-box loader (mainly for simulation)
|
||||
component sbox_loader is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
load_o : out sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
end tech_iface;
|
||||
@@ -0,0 +1,184 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : tech_sbox_stage
|
||||
--
|
||||
-- File Name : tech_sbox_stage_virtex2.vhd
|
||||
--
|
||||
-- Purpose : The module provides S-box stage for implementation of
|
||||
-- encryption, decryption and key schedule using 32-bit
|
||||
-- datapath on Virtex-II family
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : aes_definitions, tech_iface
|
||||
--
|
||||
-- - Module(s) : dual_sbox_virtex2 (dual-port RAM block)
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : S-box type mapping as required by 128-bit key schedule
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-02 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
use work.aes_definitions.all;
|
||||
use work.tech_iface.all;
|
||||
|
||||
|
||||
entity tech_sbox_stage is
|
||||
port (
|
||||
rst : in std_logic; -- reset
|
||||
clk : in std_logic; -- clock
|
||||
data_i : in sbox_stage_in_type; -- see package tech_iface
|
||||
data_o : out sbox_stage_out_type; -- see package tech_iface
|
||||
load_i : in sbox_stage_load_in_type -- see package tech_iface
|
||||
);
|
||||
end tech_sbox_stage;
|
||||
|
||||
|
||||
architecture behavioural of tech_sbox_stage is
|
||||
|
||||
|
||||
component dual_sbox_virtex2 is
|
||||
port (
|
||||
clk : in std_logic; -- clock (rising)
|
||||
enca : in std_logic; -- encryption (0) / decryption (1) mode
|
||||
encb : in std_logic; -- encryption (0) / decryption (1) mode
|
||||
posa : in std_logic_vector(7 downto 0); -- position
|
||||
posb : in std_logic_vector(7 downto 0); -- position
|
||||
dina : in std_logic_vector(7 downto 0); -- write data
|
||||
dinb : in std_logic_vector(7 downto 0); -- write data
|
||||
wea : in std_logic; -- write enable
|
||||
web : in std_logic; -- write enable
|
||||
douta : out std_logic_vector(7 downto 0); -- read data
|
||||
doutb : out std_logic_vector(7 downto 0); -- read data
|
||||
is_init : out std_logic -- pre-initialised memory
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
signal s_din : std_logic_vector(31 downto 0); -- S-box input data
|
||||
signal s_ed_mode : std_logic; -- en-/decryption mode selection
|
||||
|
||||
signal s_wen : std_logic; -- write enable
|
||||
signal s_ready : std_logic; -- S-box is ready
|
||||
|
||||
signal s_is_init : std_logic_vector(1 downto 0); -- S-box is pre-initialized
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-- handle activation of load I/F
|
||||
process (load_i, data_i)
|
||||
begin
|
||||
if (load_i.act = '1')
|
||||
then
|
||||
s_din <= load_i.pos & load_i.pos & load_i.pos & load_i.pos;
|
||||
s_ed_mode <= load_i.ed_mode;
|
||||
s_wen <= load_i.wen;
|
||||
else
|
||||
s_din <= data_i.din;
|
||||
s_ed_mode <= data_i.ed_mode;
|
||||
s_wen <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
sbox_2x8_1: dual_sbox_virtex2
|
||||
port map (
|
||||
clk => clk,
|
||||
enca => s_ed_mode,
|
||||
encb => s_ed_mode,
|
||||
posa => s_din(31 downto 24),
|
||||
posb => s_din(23 downto 16),
|
||||
dina => load_i.din,
|
||||
dinb => (others => '0'),
|
||||
wea => s_wen,
|
||||
web => '0',
|
||||
douta => data_o.dout(31 downto 24),
|
||||
doutb => data_o.dout(23 downto 16),
|
||||
is_init => s_is_init(1)
|
||||
);
|
||||
|
||||
|
||||
sbox_2x8_0: dual_sbox_virtex2
|
||||
port map (
|
||||
clk => clk,
|
||||
enca => s_ed_mode,
|
||||
encb => s_ed_mode,
|
||||
posa => s_din(15 downto 8),
|
||||
posb => s_din(7 downto 0),
|
||||
dina => load_i.din,
|
||||
dinb => (others => '0'),
|
||||
wea => s_wen,
|
||||
web => '0',
|
||||
douta => data_o.dout(15 downto 8),
|
||||
doutb => data_o.dout(7 downto 0),
|
||||
is_init => s_is_init(0)
|
||||
);
|
||||
|
||||
|
||||
-- generate S-box ready flag
|
||||
process
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
if (rst = '1')
|
||||
then
|
||||
s_ready <= s_is_init(0) and s_is_init(1);
|
||||
elsif (load_i.act = '1') and (load_i.wen = '1')
|
||||
then
|
||||
s_ready <= '0';
|
||||
elsif (load_i.act = '1') and (load_i.done = '1')
|
||||
then
|
||||
s_ready <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
data_o.ready <= (not load_i.act) and s_ready;
|
||||
|
||||
|
||||
end behavioural;
|
||||
@@ -0,0 +1,142 @@
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Design unit : tech_subkey_memory
|
||||
--
|
||||
-- File Name : tech_subkey_memory_virtex2.vhd
|
||||
--
|
||||
-- Purpose : The module provides subkey memory for implementation of
|
||||
-- encryption, decryption and key schedule using 32-bit
|
||||
-- datapath on Virtex-II family
|
||||
--
|
||||
--
|
||||
-- Depends on :
|
||||
--
|
||||
-- - Package(s) : aes_definitions, tech_iface
|
||||
--
|
||||
-- - Module(s) : -
|
||||
--
|
||||
--
|
||||
-- Dev. Platform : Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
|
||||
--
|
||||
-- - Simulator(s) : Modelsim XE III 6.0d
|
||||
--
|
||||
-- - Synthesis : Xilinx XST
|
||||
--
|
||||
-- - Place & Route : Xilinx PAR
|
||||
--
|
||||
--
|
||||
-- Errors : None known
|
||||
--
|
||||
--
|
||||
-- Limitations : None known
|
||||
--
|
||||
--
|
||||
-- Notes : parity memory is used to store number of rounds
|
||||
-- beside the subkey
|
||||
--
|
||||
--
|
||||
-- Author(s) : A. Freund (af) <a.freund@dsi-it.de>
|
||||
-- Digitale Signalverabeitung & Informationstechnik GmbH,
|
||||
-- Bremen, Germany
|
||||
--
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Revision List:
|
||||
-- Version Author(s) Date Changes
|
||||
--
|
||||
-- v0.00 af 2006-11-15 initial version
|
||||
--
|
||||
-- see SVN logs
|
||||
--
|
||||
-- ============================================================================
|
||||
--
|
||||
-- Naming conventions:
|
||||
--
|
||||
-- - active-low signals are indicated by appending "_n"
|
||||
-- - constants are in UPPERCASE
|
||||
-- - name parts are separated by "_"
|
||||
--
|
||||
-- ============================================================================
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
|
||||
use work.aes_definitions.all;
|
||||
use work.tech_iface.all;
|
||||
|
||||
|
||||
entity tech_subkey_memory is
|
||||
port (
|
||||
clk : in std_logic; -- clock
|
||||
key_sched_i : in subkey_memory_ks_in_type; -- see package tech_iface
|
||||
enc_dec_i : in subkey_memory_ed_in_type; -- see package tech_iface
|
||||
enc_dec_o : out subkey_memory_ed_out_type -- see package tech_iface
|
||||
);
|
||||
end tech_subkey_memory;
|
||||
|
||||
|
||||
architecture behavioural of tech_subkey_memory is
|
||||
|
||||
signal s_pm_a_in : std_logic_vector(3 downto 0) := (others => '0');
|
||||
signal s_pm_b_out : std_logic_vector(3 downto 0);
|
||||
|
||||
signal s_addr_a : std_logic_vector(key_id_t'length + aes_round_no_t'length + part_no_t'length - 1 downto 0);
|
||||
signal s_addr_b : std_logic_vector(key_id_t'length + aes_round_no_t'length + part_no_t'length - 1 downto 0);
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
s_pm_a_in(aes_round_no_t'range) <= key_sched_i.rounds;
|
||||
|
||||
s_addr_a <= key_sched_i.key_id & key_sched_i.subkey_no & key_sched_i.part_no;
|
||||
|
||||
s_addr_b <= enc_dec_i.key_id & enc_dec_i.subkey_no & enc_dec_i.part_no;
|
||||
|
||||
|
||||
-- 1 Block-RAMs for subkey memory, port A : key schedule, port B : en-/decryprion
|
||||
|
||||
-- RAMB16_S36_S36: Virtex-II/II-Pro, Spartan-3/3E 512 x 32 + 4 Parity bits Dual-Port RAM
|
||||
-- Xilinx HDL Language Template version 7.1i
|
||||
|
||||
skm: RAMB16_S36_S36
|
||||
generic map (
|
||||
WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
||||
WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
||||
SIM_COLLISION_CHECK => "NONE" -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
|
||||
)
|
||||
port map (
|
||||
DOA => open, -- Port A 32-bit Data Output
|
||||
DOB => enc_dec_o.subkey, -- Port B 32-bit Data Output
|
||||
DOPA => open, -- Port A 4-bit Parity Output
|
||||
DOPB => s_pm_b_out, -- Port B 4-bit Parity Output
|
||||
ADDRA => s_addr_a, -- Port A 9-bit Address Input
|
||||
ADDRB => s_addr_b, -- Port B 9-bit Address Input
|
||||
CLKA => clk, -- Port A Clock
|
||||
CLKB => clk, -- Port B Clock
|
||||
DIA => key_sched_i.subkey, -- Port A 32-bit Data Input
|
||||
DIB => X"00000000", -- Port B 32-bit Data Input
|
||||
DIPA => s_pm_a_in, -- Port A 4-bit parity Input
|
||||
DIPB => "0000", -- Port-B 4-bit parity Input
|
||||
ENA => key_sched_i.write_en, -- Port A RAM Enable Input
|
||||
ENB => enc_dec_i.rd_en, -- PortB RAM Enable Input
|
||||
SSRA => '0', -- Port A Synchronous Set/Reset Input
|
||||
SSRB => '0', -- Port B Synchronous Set/Reset Input
|
||||
WEA => key_sched_i.write_en, -- Port A Write Enable Input
|
||||
WEB => '0' -- Port B Write Enable Input
|
||||
);
|
||||
|
||||
|
||||
|
||||
enc_dec_o.rounds <= s_pm_b_out(aes_round_no_t'range);
|
||||
|
||||
|
||||
end behavioural;
|
||||
Reference in New Issue
Block a user