diff --git a/lib/VGA_ctrl/src/tb_vga_frontend.vhd b/lib/VGA_ctrl/src/tb_vga_frontend.vhd
index a07ec69..5911dde 100644
--- a/lib/VGA_ctrl/src/tb_vga_frontend.vhd
+++ b/lib/VGA_ctrl/src/tb_vga_frontend.vhd
@@ -45,9 +45,9 @@ ARCHITECTURE behavior OF tb_vga_frontend IS
 	signal ACK_I			: std_logic := '0';
 	signal MRDY_O			: std_logic := '1';
 	signal SRDY_I			: std_logic := '0';
-	signal ADDR_O			: unsigned(31 downto 0);
-	signal MDAT_I			: unsigned(31 downto 0);
-	signal MDAT_O			: unsigned(31 downto 0);
+	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
+	signal MDAT_I			: unsigned(31 downto 0) := (others => '-');
+	signal MDAT_O			: unsigned(31 downto 0) := (others => '-');
 
 	-- Slave
 	signal CYC_I			: std_logic := '0';
@@ -59,10 +59,10 @@ ARCHITECTURE behavior OF tb_vga_frontend IS
 	signal SRDY_O			: std_logic;
 	signal ADDR_I			: unsigned(31 downto 0) := (others => '-');
 	signal SDAT_I			: unsigned(31 downto 0) := (others => '-');
-	signal SDAT_O			: unsigned(31 downto 0);
+	signal SDAT_O			: unsigned(31 downto 0) := (others => '-');
 
 	-- VGA signals
-	signal vga_clk_out		: std_logic;
+	signal vga_clk		: std_logic;
 	signal vga_red			: unsigned(7 downto 0);
 	signal vga_green		: unsigned(7 downto 0);
 	signal vga_blue			: unsigned(7 downto 0);
@@ -70,17 +70,19 @@ ARCHITECTURE behavior OF tb_vga_frontend IS
 	signal vga_sync_n		: std_logic;
 	signal vga_hsync		: std_logic;
 	signal vga_vsync		: std_logic;
+	signal dcm_locked		: std_logic;
+
+	constant tsvga			: vga_timespec_t := ts_vga_800_600_72;
 
 BEGIN
 
 inst_vga_frontend : entity work.vga_frontend
 	GENERIC MAP
 	(
-		sys_freq					=> 100E6,
 		fifo_depth					=> 2048,
 		fifo_almost_full_thresh		=> 2000,
 		fifo_almost_empty_thresh	=> 48,
-		tsvga						=> ts_vga_800_600_72
+		tsvga						=> tsvga
 	)
 	PORT MAP
 	(
@@ -113,7 +115,8 @@ inst_vga_frontend : entity work.vga_frontend
 		SDAT_O			=> SDAT_I,
 		
 		-- VGA signals
-		vga_clk_out		=> vga_clk_out,
+		vga_clk_in		=> vga_clk,
+		vga_clk_ce		=> dcm_locked,
 		vga_red			=> vga_red,
 		vga_green		=> vga_green,
 		vga_blue		=> vga_blue,
@@ -130,6 +133,20 @@ CLK_GEN: process
 		CLK_O <= not CLK_O;
 	end process;
 
+inst_clkgen: entity work.clkgen
+	GENERIC MAP
+	(
+		clk_in_freq_hz		=> 100E6,
+		clk_out_freq_hz		=> tsvga.f_pxl_clk
+	)		
+	PORT MAP
+	(
+		rst			=> RST_O,
+		clk_in		=> CLK_O,
+		clk_out		=> vga_clk,
+		locked		=> dcm_locked
+	);
+
 -- Slave
 	SRDY_O	<= CYC_I;
 	
@@ -154,13 +171,23 @@ STIMULUS: process
 
 		wait for 6*CLK_PERIOD;
 		RST_O <= '0';
+		wait for 60*CLK_PERIOD;
 
 		-- 8 single cycles
 		CYC_O	<= '1';
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		SDAT_I	<= X"0000_0000";
+		SDAT_O	<= X"0000_0001";
+		ADDR_O	<= X"0000_0100";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= X"0000_0000";
 		ADDR_O	<= X"0000_0008";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
@@ -168,7 +195,7 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		SDAT_I	<= X"0000_0000";
+		SDAT_O	<= X"0000_0000";
 		ADDR_O	<= X"0000_0010";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
@@ -176,7 +203,7 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		SDAT_I	<= X"0000_0035";
+		SDAT_O	<= X"0000_0035";
 		ADDR_O	<= X"0000_0004";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
@@ -184,7 +211,7 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		SDAT_I	<= X"0000_0035";
+		SDAT_O	<= X"0000_0035";
 		ADDR_O	<= X"0000_0020";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
index 279f854..a20242d 100644
--- a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+++ b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
@@ -45,9 +45,9 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
 	signal ACK_I			: std_logic := '0';
 	signal MRDY_O			: std_logic := '1';
 	signal SRDY_I			: std_logic := '0';
-	signal ADDR_O			: unsigned(31 downto 0);
-	signal MDAT_I			: unsigned(63 downto 0);
-	signal MDAT_O			: unsigned(63 downto 0);
+	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
+	signal MDAT_I			: unsigned(63 downto 0) := (others => '-');
+	signal MDAT_O			: unsigned(63 downto 0) := (others => '-');
 
 	-- Slave
 	signal CYC_I			: std_logic := '0';
@@ -59,10 +59,10 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
 	signal SRDY_O			: std_logic;
 	signal ADDR_I			: unsigned(31 downto 0) := (others => '-');
 	signal SDAT_I			: unsigned(31 downto 0) := (others => '-');
-	signal SDAT_O			: unsigned(31 downto 0);
+	signal SDAT_O			: unsigned(31 downto 0) := (others => '-');
 
 	-- VGA signals
-	signal vga_clk_out		: std_logic;
+	signal vga_clk			: std_logic;
 	signal vga_red			: unsigned(7 downto 0);
 	signal vga_green		: unsigned(7 downto 0);
 	signal vga_blue			: unsigned(7 downto 0);
@@ -70,17 +70,19 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
 	signal vga_sync_n		: std_logic;
 	signal vga_hsync		: std_logic;
 	signal vga_vsync		: std_logic;
+	signal dcm_locked		: std_logic;
 
+	constant tsvga			: vga_timespec_t := ts_vga_800_600_72;
+	
 BEGIN
 
 inst_vga_frontend64 : entity work.vga_frontend64
 	GENERIC MAP
 	(
-		sys_freq					=> 100E6,
 		fifo_depth					=> 2048,
 		fifo_almost_full_thresh		=> 2000,
 		fifo_almost_empty_thresh	=> 48,
-		tsvga						=> ts_vga_800_600_72
+		tsvga						=> tsvga
 	)
 	PORT MAP
 	(
@@ -113,7 +115,8 @@ inst_vga_frontend64 : entity work.vga_frontend64
 		SDAT_O			=> SDAT_I,
 		
 		-- VGA signals
-		vga_clk_out		=> vga_clk_out,
+		vga_clk_in		=> vga_clk,
+		vga_clk_ce		=> dcm_locked,
 		vga_red			=> vga_red,
 		vga_green		=> vga_green,
 		vga_blue		=> vga_blue,
@@ -130,6 +133,20 @@ CLK_GEN: process
 		CLK_O <= not CLK_O;
 	end process;
 
+inst_clkgen: entity work.clkgen
+	GENERIC MAP
+	(
+		clk_in_freq_hz		=> 100E6,
+		clk_out_freq_hz		=> tsvga.f_pxl_clk
+	)		
+	PORT MAP
+	(
+		rst			=> RST_O,
+		clk_in		=> CLK_O,
+		clk_out		=> vga_clk,
+		locked		=> dcm_locked
+	);
+
 -- Slave
 	SRDY_O	<= CYC_I;
 	
@@ -154,13 +171,23 @@ STIMULUS: process
 
 		wait for 6*CLK_PERIOD;
 		RST_O <= '0';
+		wait for 60*CLK_PERIOD;
 
 		-- 8 single cycles
 		CYC_O	<= '1';
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		SDAT_I	<= X"0000_0000";
+		SDAT_O	<= X"0000_0001";
+		ADDR_O	<= X"0000_0100";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= X"0000_0000";
 		ADDR_O	<= X"0000_0008";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
@@ -168,7 +195,7 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		SDAT_I	<= X"0000_0000";
+		SDAT_O	<= X"0000_0000";
 		ADDR_O	<= X"0000_0010";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
@@ -176,7 +203,7 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		SDAT_I	<= X"0000_0035";
+		SDAT_O	<= X"0000_0035";
 		ADDR_O	<= X"0000_0004";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
@@ -184,7 +211,7 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		SDAT_I	<= X"0000_0035";
+		SDAT_O	<= X"0000_0035";
 		ADDR_O	<= X"0000_0020";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';