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- buf_chg_ack also on 'host_fb_back' write

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git-svn-id: http://moon:8086/svn/vhdl/trunk@668 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-19 20:35:56 +00:00
parent 514f9e0f58
commit 717239c086
1 changed files with 62 additions and 77 deletions
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lib/VGA_ctrl/src/vga_frontend64.vhd
+62 -77
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@@ -128,7 +128,6 @@ architecture Behavioral of vga_frontend64 is
signal bufchg_irq_en : std_logic;
signal bufchg_flag : std_logic;
signal bufchg_flag_ack : std_logic;
signal host_fb_back_we : std_logic;
signal vga_fb_back : unsigned(31 downto 0);
signal vga_fb_front : unsigned(31 downto 0);
signal host_fb_front : unsigned(31 downto 0);
@@ -142,8 +141,8 @@ architecture Behavioral of vga_frontend64 is
signal request_cnt : natural range 0 to MAX_REQUEST_CNT-1;
signal read_cnt : natural range 0 to MAX_REQUEST_CNT-1;
signal STB_O_master : std_logic;
signal ADDR_O_master : unsigned(31 downto 0);
signal STB_O_scan : std_logic;
signal ADDR_O_scan : unsigned(31 downto 0);
signal pixel_cnt : natural range 0 to MAX_REQUEST_CNT/2-1;
signal front : unsigned(31 downto 0);
signal back : unsigned(31 downto 0);
@@ -151,25 +150,25 @@ architecture Behavioral of vga_frontend64 is
signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
-- Bus FIFO
signal bout_fifo_din : unsigned(104 downto 0);
signal bout_fifo_dout : unsigned(104 downto 0);
signal bout_fifo_re : std_logic;
signal bout_fifo_we : std_logic;
signal bout_fifo_full : std_logic;
signal bout_fifo_empty : std_logic;
signal bout_rdy : std_logic;
signal bus_fifo_din : unsigned(104 downto 0);
signal bus_fifo_dout : unsigned(104 downto 0);
signal bus_fifo_re : std_logic;
signal bus_fifo_we : std_logic;
signal bus_fifo_full : std_logic;
signal bus_fifo_empty : std_logic;
signal bus_rdy : std_logic;
alias bout_fifo_addr_in is bout_fifo_din(31 downto 0);
alias bout_fifo_data_in is bout_fifo_din(95 downto 32);
alias bout_fifo_sel_in is bout_fifo_din(103 downto 96);
alias bout_fifo_we_in is bout_fifo_din(104);
alias bus_fifo_addr_in is bus_fifo_din(31 downto 0);
alias bus_fifo_data_in is bus_fifo_din(95 downto 32);
alias bus_fifo_sel_in is bus_fifo_din(103 downto 96);
alias bus_fifo_we_in is bus_fifo_din(104);
alias bout_fifo_addr_out is bout_fifo_dout(31 downto 0);
alias bout_fifo_data_out is bout_fifo_dout(95 downto 32);
alias bout_fifo_sel_out is bout_fifo_dout(103 downto 96);
alias bout_fifo_we_out is bout_fifo_dout(104);
alias bus_fifo_addr_out is bus_fifo_dout(31 downto 0);
alias bus_fifo_data_out is bus_fifo_dout(95 downto 32);
alias bus_fifo_sel_out is bus_fifo_dout(103 downto 96);
alias bus_fifo_we_out is bus_fifo_dout(104);
type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data);
type vm_state_t is (init, idle, rdy, bus_request, bus_data);
signal s, sn : vm_state_t;
begin
@@ -231,6 +230,14 @@ inst_vga_backend : entity work.vga_backend
vga_vsync => vga_vsync
);
SRDY_O <= CYC_I; -- and cg_rdy;
MRDY_O <= not fifo_full;
STB_O <= not bus_fifo_empty;
ADDR_O <= bus_fifo_addr_out;
MDAT_O <= bus_fifo_data_out;
SEL_O <= bus_fifo_sel_out;
WE_O <= bus_fifo_we_out;
odd_pixel <= to_unsigned(stat_hpos, odd_pixel'length);
ctrl_scan_en <= '1';
color_en(0) <= not fifo_empty;
@@ -267,17 +274,36 @@ inst_linefifo: entity work.fifo_async
fifo_color_in <= MDAT_I;
fifo_color_re <= stat_scan and odd_pixel(0);
fifo_color_we <= ACK_I and read_bus_en; -- TODO:
SRDY_O <= CYC_I; -- and cg_rdy;
MRDY_O <= not fifo_full;
-- SEL_O <= (others => '0');
-- WE_O <= '0';
STB_O <= not bout_fifo_empty;
ADDR_O <= bout_fifo_addr_out;
MDAT_O <= bout_fifo_data_out;
SEL_O <= bout_fifo_sel_out;
WE_O <= bout_fifo_we_out;
-- Instantiate synchronous FIFO
inst_bus_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => 2,
data_width => 105
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => bus_fifo_we,
re => bus_fifo_re,
fifo_full => bus_fifo_full,
fifo_empty => bus_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => bus_fifo_din,
data_r => bus_fifo_dout
);
bus_rdy <= not bus_fifo_full;
bus_fifo_re <= not bus_fifo_empty and SRDY_I;
bus_fifo_we <= STB_O_scan and request_cnt_en;
bus_fifo_data_in <= (others => '-');
bus_fifo_addr_in <= ADDR_O_scan;
bus_fifo_sel_in <= (others => '1');
bus_fifo_we_in <= '0';
ADDR_O_scan <= front + (to_unsigned(pixel_cnt, 29) & "000");
vga_master_next:
process(CLK_I)
begin
@@ -295,7 +321,7 @@ vga_master:
begin
CYC_O <= '0';
STB_O_master <= '0';
STB_O_scan <= '0';
pixel_cnt_rst <= '0';
request_cnt_rst <= '0';
request_cnt_en <= '0';
@@ -315,21 +341,14 @@ vga_master:
end if;
when rdy =>
-- pixel_cnt_rst <= '1';
request_cnt_rst <= '1';
if fifo_almost_empty = '1' then
sn <= bus_request;
end if;
when bus_request =>
CYC_O <= '1';
request_cnt_rst <= '1';
-- if SRDY_I = '1' then
sn <= bus_access;
-- end if;
when bus_access =>
CYC_O <= '1';
STB_O_master <= '1';
STB_O_scan <= '1';
request_cnt_en <= '1';
read_bus_en <= '1';
if fifo_almost_full = '1' then
@@ -356,7 +375,7 @@ request_counter:
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
request_cnt <= 0;
elsif request_cnt_en = '1' and bout_rdy = '1' then
elsif request_cnt_en = '1' and bus_rdy = '1' then
if request_cnt /= MAX_REQUEST_CNT-1 then
request_cnt <= request_cnt + 1;
end if;
@@ -378,7 +397,7 @@ read_counter:
end if;
end process;
pixel_counter:
addr_gen_scan:
process(CLK_I)
begin
if rising_edge(CLK_I) then
@@ -386,7 +405,7 @@ pixel_counter:
if pixel_cnt_rst = '1' then
pixel_cnt <= 0;
front <= host_fb_front;
elsif request_cnt_en = '1' and bout_rdy = '1' then
elsif request_cnt_en = '1' and bus_rdy = '1' then
if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
pixel_cnt <= pixel_cnt + 1;
else
@@ -400,39 +419,6 @@ pixel_counter:
end if;
end process;
-- Instantiate synchronous FIFO
inst_bout_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => 2,
data_width => 105
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => bout_fifo_we,
re => bout_fifo_re,
fifo_full => bout_fifo_full,
fifo_empty => bout_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => bout_fifo_din,
data_r => bout_fifo_dout
);
bout_rdy <= not bout_fifo_full;
bout_fifo_re <= not bout_fifo_empty and SRDY_I;
bout_fifo_we <= STB_O_master and request_cnt_en;
bout_fifo_data_in <= (others => '-');
bout_fifo_addr_in <= ADDR_O_master;
bout_fifo_sel_in <= (others => '1');
bout_fifo_we_in <= '0';
ADDR_O_master <= front + (to_unsigned(pixel_cnt, 29) & "000");
inst_char_gen : entity work.char_gen
GENERIC MAP
(
@@ -535,7 +521,6 @@ registers_write:
cg_clr_screen <= '0';
cg_clr_line <= '0';
bufchg_flag_ack <= '0';
host_fb_back_we <= '0';
if RST_I = '1' then
cg_din <= (others => '0');
vga_master_en <= '0';
@@ -579,7 +564,7 @@ registers_write:
-- sys_vga_fb_back 28
when "0111" =>
host_fb_back_we <= '1';
bufchg_flag_ack <= '1';
host_fb_back <= SDAT_I(31 downto 2) & "00";
when others => null;