- commit local changes after CVS2SVN

git-svn-id: http://moon:8086/svn/vhdl/trunk@1036 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/syn/ise101/mips_top.prj

@@ -1,7 +1,8 @@
 vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
 vhdl work "../../../../FIFO/src/gray_counter.vhd"
-vhdl work "../../../../misc/dpram_2w2r.vhd"
+vhdl work "../../../../rams/dpram_2w2r2c_ra_xil.vhd"
-vhdl work "../../../../misc/dpram_1w1r.vhd"
+vhdl work "../../../../rams/dpram_1w1r2c_ro_xil.vhd"
+vhdl work "../../../../rams/dpram_1w1r2c_ra_xil.vhd"
 vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
 vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
 vhdl work "../../src/core/mips_types.vhd"

lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj

@@ -1,7 +1,8 @@
 vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
 vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
+vhdl work "W:\vhdl\lib\rams\dpram_2w2r2c_ra_xil.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\rams\dpram_1w1r2c_ro_xil.vhd"
+vhdl work "W:\vhdl\lib\rams\dpram_1w1r2c_ra_xil.vhd"
 vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
 vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"

lib/CPUs/MIPS/todo.txt

@@ -33,3 +33,8 @@
 
 2010-01-09
 - COP dependency einführen => Pipeline stall, wenn COP Daten nicht verfügbar
+
+213-08-25
+- TLB exception in EX-stage einbauen
+- Cache dout und ready um logic-level reduzieren
+- cam_ram_addr_rd um logic-level reduzieren

lib/JBUS/sim/tb_busmaster_async.wdo

@@ -19,11 +19,17 @@ add wave -noupdate -divider Busmaster
 add wave -noupdate -format Logic /tb_busmaster_async/clk_o
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
+add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/read_cnt
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write
+add wave -noupdate -format Literal -expand /tb_busmaster_async/inst_uut/debug
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_finished
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_en
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_rdy
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_we
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/inst_uut/cmd_in
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_fifo_empty
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_fifo_re
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/read_fifo_we
 add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/din
 add wave -noupdate -format Logic /tb_busmaster_async/din_rdy
 add wave -noupdate -format Logic /tb_busmaster_async/din_we
@@ -31,10 +37,19 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_u
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_vld
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_re
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cycle_busy
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cycle_active
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_en
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_read_en
-add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/read_cnt
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_fifo_we
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_fifo_full
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/read_fifo_re
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/read_fifo_full
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/read_fifo_empty
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write_fifo_re
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write_fifo_we
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write_fifo_full
+add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write_fifo_empty
 add wave -noupdate -divider RAM
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
 add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
@@ -42,7 +57,7 @@ add wave -noupdate -format Literal /tb_busmaster_async/state
 add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/read_reg
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/ram64
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {31500000 ps} 0}
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
 configure wave -namecolwidth 150
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -56,4 +71,4 @@ configure wave -gridperiod 1
 configure wave -griddelta 40
 configure wave -timeline 0
 update
-WaveRestoreZoom {0 ps} {42 us}
+WaveRestoreZoom {0 ps} {8639241 ps}

lib/JBUS/src/busmaster_async.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.2 2013-08-04 17:58:37 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.2 2013/08/04 17:58:37 jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

lib/JBUS/src/busmaster_sync.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.6 2013-08-03 19:31:19 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.6 2013/08/03 19:31:19 jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

lib/JBUS/src/busmaster_types.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_types.vhd,v 1.2 2013-05-27 11:17:51 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/busmaster_types.vhd,v 1.2 2013/05/27 11:17:51 jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/JBUS/src/dmac.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/dmac.vhd,v 1.2 2013-05-28 11:23:15 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/dmac.vhd,v 1.2 2013/05/28 11:23:15 jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -147,14 +147,15 @@ state:
 
 			when FINISH =>
 				master_req	<= '1';
-				if bus_cyc_complete = '1' then
+				dma_end		<= '1';
 				sn	<= DONE;
-					finish_en	<= '1';
-				end if;
 
 			when DONE =>
-				dma_end		<= '1';
+				master_req			<= '1';
+				if bus_cyc_complete = '1' then
 					sn			<= READY;
+					finish_en	<= '1';
+				end if;
 
 			when others =>
 				sn	<= READY;

lib/JBUS/src/tb_busmaster_async.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_async.vhd,v 1.1 2013-07-21 09:21:30 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/tb_busmaster_async.vhd,v 1.1 2013/07/21 09:21:30 jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY ieee;

lib/JBUS/src/tb_busmaster_sync.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.3 2013-07-21 09:10:13 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.3 2013/07/21 09:10:13 jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY ieee;

lib/JBUS/src/tb_dmac.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_dmac.vhd,v 1.2 2013-05-28 11:23:15 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/tb_dmac.vhd,v 1.2 2013/05/28 11:23:15 jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY ieee;

lib/PCK_FIO-2002.7/CHANGES

@@ -1,4 +1,4 @@
-----  $Id: CHANGES,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----  $Id: CHANGES,v 1.1 2008/08/23 08:20:28 Jens Exp $
 ----
 ----  PCK_FIO: a VHDL package for C-style formatted file output
 ----  Copyright (C) 1995, 2001 Easics NV 

lib/PCK_FIO-2002.7/PCK_FIO.html

@@ -4,7 +4,7 @@
    <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
    <meta name="GENERATOR" content="Mozilla/4.76 [en] (X11; U; Linux 2.4.13 i686) [Netscape]">
    <title>VHDL package for formatted file output</title>
-<!-- $Id: PCK_FIO.html,v 1.1 2008-08-23 08:20:28 Jens Exp $ -->
+<!-- $Id: PCK_FIO.html,v 1.1 2008/08/23 08:20:28 Jens Exp $ -->
 </head>
 <body text="#000000" bgcolor="#FFFFFF" link="#0000EE" vlink="#551A8B" alink="#FF0000">
 

lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd

@@ -1,4 +1,4 @@
-----  $Id: PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----  $Id: PCK_FIO_1987.vhd,v 1.1 2008/08/23 08:20:28 Jens Exp $
 ----
 ----  PCK_FIO: a VHDL package for C-style formatted file output
 ----  Copyright (C) 1995, 2001 Easics NV 

lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd

@@ -1,4 +1,4 @@
-----  $Id: PCK_FIO_1987_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----  $Id: PCK_FIO_1987_BODY.vhd,v 1.1 2008/08/23 08:20:28 Jens Exp $
 ----
 ----  PCK_FIO: a VHDL package for C-style formatted file output
 ----  Copyright (C) 1995, 2001 Easics NV 

lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd

@@ -1,4 +1,4 @@
-----  $Id: PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----  $Id: PCK_FIO_1993.vhd,v 1.1 2008/08/23 08:20:28 Jens Exp $
 ----
 ----  PCK_FIO: a VHDL package for C-style formatted file output
 ----  Copyright (C) 1995, 2001 Easics NV 

lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd

@@ -1,4 +1,4 @@
-----  $Id: PCK_FIO_1993_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----  $Id: PCK_FIO_1993_BODY.vhd,v 1.1 2008/08/23 08:20:28 Jens Exp $
 ----
 ----  PCK_FIO: a VHDL package for C-style formatted file output
 ----  Copyright (C) 1995, 2001 Easics NV 

lib/PCK_FIO-2002.7/README

@@ -1,4 +1,4 @@
-----  $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----  $Id: README,v 1.1 2008/08/23 08:20:28 Jens Exp $
 ----
 ----  PCK_FIO: a VHDL package for C-style formatted file output
 ----  Copyright (C) 1995, 2001 Easics NV 

lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd

@@ -1,4 +1,4 @@
----- $Id: TB_PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+---- $Id: TB_PCK_FIO_1987.vhd,v 1.1 2008/08/23 08:20:28 Jens Exp $
 ----
 ----  PCK_FIO: a VHDL package for C-style formatted file output
 ----  Copyright (C) 1995, 2001 Easics NV 

lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd

@@ -1,4 +1,4 @@
----- $Id: TB_PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+---- $Id: TB_PCK_FIO_1993.vhd,v 1.1 2008/08/23 08:20:28 Jens Exp $
 ----
 ----  PCK_FIO: a VHDL package for C-style formatted file output
 ----  Copyright (C) 1995, 2001 Easics NV 

lib/ac97_ctrl/sim/tb_ac97_wb.fdo

@@ -4,8 +4,8 @@
 vlib work
 vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../misc/dpram_1w1r_dist.vhd"
+vcom -explicit  -93 "../../misc/dpram_1w1r.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_sync_dist.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_sync.vhd"
 vcom -explicit  -93 "../../misc/singleshot.vhd"
 vcom -explicit  -93 "../src/core/ac_out.vhd"
 vcom -explicit  -93 "../src/core/ac_in.vhd"

lib/misc/async_port_wb.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010-02-09 09:56:37 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010/02/09 09:56:37 Jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

lib/misc/bbfifo.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008-10-20 19:26:01 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008/10/20 19:26:01 Jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/misc/debounce.vhd

@@ -17,7 +17,7 @@
 -- Additional Comments:
 -- 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

lib/misc/debounce2.vhd

@@ -3,7 +3,7 @@
 -- Jeff Bazinet
 -- February 14, 2002
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
 -----------------------------------------------------------------------
 
 

lib/misc/dpram_1w1r.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY IEEE;

lib/misc/dpram_1w1r1c_sim.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r1c_sim.vhd,v 1.1 2013-02-07 14:15:37 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r1c_sim.vhd,v 1.1 2013/02/07 14:15:37 jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY IEEE;

lib/misc/dpram_1w1r1c_xil.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r1c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY IEEE;

lib/misc/dpram_1w1r2c_sim.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r2c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r2c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY IEEE;

lib/misc/dpram_1w1r2c_xil.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r2c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r2c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY IEEE;

lib/misc/dpram_1w1r_dist.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY IEEE;

lib/misc/dpram_1w2r1c_sim.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w2r1c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w2r1c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/misc/dpram_1w2r1c_xil.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w2r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w2r1c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/misc/dpram_2w2r.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009-01-14 20:26:29 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009/01/14 20:26:29 Jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/misc/dpram_2w2r1c_sim.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r1c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r1c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/misc/dpram_2w2r1c_xil.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r1c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/misc/dpram_2w2r2c_sim.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r2c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r2c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/misc/dpram_2w2r2c_xil.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r2c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r2c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/misc/flash_port_wb.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.2 2010-03-13 11:06:43 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.2 2010/03/13 11:06:43 Jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

lib/misc/lcd_port.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

lib/misc/oneshot.vhd

@@ -17,7 +17,7 @@
 -- Additional Comments:
 -- 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
 -----------------------------------------------------------------------
 -- Component Template
 --

lib/misc/pkg_template.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
 -----------------------------------------------------------------------
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;

lib/misc/singleshot.vhd

@@ -17,7 +17,7 @@
 -- Additional Comments:
 -- 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
 -----------------------------------------------------------------------
 -- Component Template
 --

lib/misc/tb_template.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
 -----------------------------------------------------------------------
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;

lib/misc/utils_pkg.vhd

@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.6 2010-03-22 07:25:40 Jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.6 2010/03/22 07:25:40 Jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/radio/ddc/src/syn_ddc.vhd

@@ -20,8 +20,8 @@ library ieee_proposed;
 use ieee_proposed.math_utility_pkg.all;
 use ieee_proposed.fixed_pkg.all;
 
-library altera;
+--library altera;
-use altera.altera_syn_attributes.all;
+--use altera.altera_syn_attributes.all;
 
 library work;
 use work.fixed_util_pkg.all;
@@ -65,13 +65,8 @@ use work.fixed_util_pkg.all;
 		usb_flagc			: in  std_logic;
 		
 		cl_clk_out			: out std_logic;
-		cl_dout				: out unsigned(23 downto 0);
+		cl_dout				: out unsigned(20 downto 0);
-		cl_pat_sel			: out std_logic;
-		cl_prbs_en			: out std_logic;
-		cl_ds_opt			: out std_logic;
-		cl_bal				: out std_logic;
 		cl_pd_n				: out std_logic;
-		cl_tsen				: in  std_logic;
 		
 		reg_aen				: in  std_logic;
 		reg_dio				: inout unsigned(7 downto 0);
@@ -153,18 +148,28 @@ ARCHITECTURE behavior OF syn_ddc IS
 	SIGNAL fifo_usb_in	 	: fifo_usb_array_t;
 	SIGNAL fifo_usb_out	 	: unsigned (15 downto 0);
 	
+	SIGNAL cl_clk			: std_logic;
+	SIGNAL fifo_cl_we		: std_logic;
+	SIGNAL fifo_cl_re		: std_logic;
+	SIGNAL fifo_cl_ff		: std_logic;
+	SIGNAL fifo_cl_ef		: std_logic;
+	SIGNAL fifo_cl_aff		: std_logic;
+	SIGNAL fifo_cl_aef		: std_logic;
+	
+	SIGNAL fifo_cl_in	 	: unsigned (63 downto 0);
+	SIGNAL fifo_cl_out	 	: unsigned (63 downto 0);
+
 	SIGNAL fifo_usb_we_pipe	: unsigned(3 downto 0);
 	SIGNAL enable			: std_logic;
 	SIGNAL ddc_din_vld		: std_logic;
 	SIGNAL ddc_dout_vld		: std_logic;
 
-	SIGNAL cl_we_pipe		: unsigned(1 downto 0);
+	SIGNAL cl_rst_pipe	 	: unsigned (63 downto 0);
-	type cl_data_array_t is array (0 to 1) of unsigned (31 downto 0);
+	SIGNAL cl_rst			: std_logic;
-	SIGNAL cl_sd_data	 	: cl_data_array_t;
+	SIGNAL cl_phase			: unsigned(1 downto 0);
-	
+	SIGNAL cl_data		 	: unsigned(20 downto 0);
-	SIGNAL cl_dout_L		: std_logic_vector(24 downto 0);
+	subtype cl_clkgen_cnt_t is natural range 0 to (2*cic_ratio/2/5)-1;
-	SIGNAL cl_dout_H		: std_logic_vector(24 downto 0);
+	SIGNAL cl_clkgen_cnt	: cl_clkgen_cnt_t;
-	SIGNAL cl_dout_clk		: std_logic_vector(24 downto 0);
 
 BEGIN
 
@@ -251,7 +256,7 @@ proc_register_write:
 		if rising_edge(adc_clk) then
 --		if rising_edge(usb_usbclk) then
 			if rst = '1' then
-				reg_lo_nco_rst	<= '0';
+				reg_lo_nco_rst	<= '1';
 				reg_lo_nco_en	<= '0';
 			elsif reg_en_data = '1' then
 				case reg_addr is
@@ -296,20 +301,17 @@ proc_adc_input_register:
 	process(adc_clk)
 	begin
 		if rising_edge(adc_clk) then
-			ddc_din_vld	<= enable;
-			if enable = '1' then
 			ddc_din_i	<= sfixed(resize(adc_da, nbits_in));
-			end if;	
+			ddc_din_vld	<= reg_lo_nco_en;
 		end if;	
 	end process;
 
 	ddc_din_q	<= to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
 	
-	enable		<= '1';
 	adc_rand	<= '0';
 	adc_pga		<= '0';
 	adc_dith	<= '0';
-	adc_shdn	<= not enable;
+	adc_shdn	<= not reg_lo_nco_en;
 
 ----------------------------------------------------------
 -- USB FIFO output
@@ -323,8 +325,8 @@ proc_usb_interleave_iq:
 				fifo_usb_we_pipe			<= (others => '0');
 			elsif ddc_dout_vld = '1' then
 				fifo_usb_we_pipe			<= (others => '1');
-				i					:= unsigned(ddc_dout_i);
+				i					:= to_unsigned(ufixed(ddc_dout_i));
-				q					:= unsigned(ddc_dout_q);
+				q					:= to_unsigned(ufixed(ddc_dout_q));
 				fifo_usb_in(0)		<= i(15 downto 0);
 				fifo_usb_in(1)		<= i(31 downto 16);
 				fifo_usb_in(2)		<= q(15 downto 0);
@@ -372,48 +374,89 @@ inst_usbfifo: entity work.fifo_async
 
 
 ----------------------------------------------------------
--- Channel-Link DDR output
+-- Channel-Link output
 ----------------------------------------------------------
-proc_cl_interleave_iq:
+inst_cl_fifo: entity work.fifo_async
+	GENERIC MAP 
+	(
+		addr_width			=> 4,
+		data_width			=> 64,
+		almost_full_thresh	=> 96,
+		almost_empty_thresh	=> 32
+	)
+	PORT MAP
+	(
+		rst				=> rst,
+		clk_w			=> adc_clk,
+		clk_r			=> cl_clk,
+		we				=> fifo_cl_we,
+		re				=> fifo_cl_re,
+		data_w			=> fifo_cl_in,
+		data_r			=> fifo_cl_out,
+		fifo_full		=> fifo_cl_ff,
+		fifo_empty		=> fifo_cl_ef,
+		fifo_afull		=> fifo_cl_aff,
+		fifo_aempty		=> fifo_cl_aef
+		
+	);
+
+	fifo_cl_in			<= to_unsigned(ufixed(ddc_dout_i)) & to_unsigned(ufixed(ddc_dout_i));
+	fifo_cl_we			<= ddc_dout_vld;
+	fifo_cl_re			<= '1';
+	
+proc_cl_clkgen:
 	process(adc_clk)
-	variable i, q : unsigned(31 downto 0);
 	begin
 		if rising_edge(adc_clk) then
 			if rst = '1' then
-				cl_we_pipe		<= (others => '0');
+				cl_rst_pipe		<= (others => '1');
-			elsif ddc_dout_vld = '1' then
+				cl_clkgen_cnt	<= cl_clkgen_cnt_t'high;
-				cl_we_pipe		<= (others => '1');
+				cl_clk			<= '0';
-				i				:= unsigned(ddc_dout_i);
-				q				:= unsigned(ddc_dout_q);
-				cl_sd_data(0)	<= i;
-				cl_sd_data(1)	<= q;
 			else
-				cl_we_pipe		<= cl_we_pipe(cl_we_pipe'left-1 downto 0) & '0';
+				if cl_clkgen_cnt = 0 then
-				cl_sd_data(0)	<= cl_sd_data(1);
+					cl_clkgen_cnt	<= cl_clkgen_cnt_t'high;
+					cl_clk			<= not cl_clk;
+					cl_rst_pipe		<= cl_rst_pipe(cl_rst_pipe'left-1 downto 0) & '0';
+				else
+					cl_clkgen_cnt <= cl_clkgen_cnt - 1;
+				end if;
 			end if;
 		end if;	
 	end process;
 
-inst_cl_ddr_out: entity work.cl_ddr_out
+	cl_rst	<= cl_rst_pipe(cl_rst_pipe'left);
-	PORT MAP
-	(
-		aclr		=> rst,
-		datain_h	=> cl_dout_H,
-		datain_l	=> cl_dout_L,
-		outclock	=> adc_clk,
-		outclocken	=> '1',
-		dataout		=> cl_dout_clk
-	);
 	
-	cl_dout_H		<= '0' & cl_we_pipe(cl_we_pipe'left) & "0000000" & std_logic_vector(cl_sd_data(0)(31 downto 16));
+proc_cl_interleave_iq:
-	cl_dout_L		<= '1' & cl_we_pipe(cl_we_pipe'left) & "0000000" & std_logic_vector(cl_sd_data(0)(15 downto 0));
+	process(cl_clk)
-	cl_dout			<= unsigned(cl_dout_clk(23 downto 0));	
+	variable i, q : unsigned(31 downto 0);
-	cl_clk_out		<= cl_dout_clk(24);
+	begin
-	cl_pat_sel		<= '0';
+		if rising_edge(cl_clk) then
-	cl_prbs_en		<= '0';
+			if cl_rst = '1' then
-	cl_ds_opt		<= '0';
+				cl_phase		<= (others => '0');
-	cl_bal			<= '0';
+			else
-	cl_pd_n			<= '1';
+				i := fifo_cl_out(31 downto 0);
+				q := fifo_cl_out(63 downto 32);
+				if cl_phase(1) = '0' then
+					if cl_phase(0) = '0' then
+						cl_data		<= not fifo_cl_ef & cl_phase & "00" & i(15 downto 0);
+					else
+						cl_data		<= not fifo_cl_ef & cl_phase & "00" & i(31 downto 16);
+					end if;
+				else
+					if cl_phase(0) = '0' then
+						cl_data		<= not fifo_cl_ef & cl_phase & "00" & q(15 downto 0);
+					else
+						cl_data		<= not fifo_cl_ef & cl_phase & "00" & q(31 downto 16);
+					end if;
+				end if;
+				cl_phase	<= cl_phase + 1;
+			end if;	
+		end if;	
+	end process;
+	
+	cl_dout			<= cl_data;	
+	cl_clk_out		<= cl_clk;
+	cl_pd_n			<= not cl_rst;
 
 ----------------------------------------------------------
 END;

lib/rams/dpram_1w1r2c_ra_sim.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY IEEE;

lib/rams/dpram_1w1r2c_ra_xil.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY IEEE;

lib/rams/dpram_1w1r2c_ro_sim.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY IEEE;

lib/rams/dpram_1w1r2c_ro_xil.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY IEEE;

lib/rams/dpram_2w2r2c_ra_sim.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/rams/dpram_2w2r2c_ra_xil.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/rams/dpram_2w2r2c_ro_sim.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

lib/rams/dpram_2w2r2c_ro_xil.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
+-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;

projects/mips_sys/sim/tb_mips_sys.fdo

@@ -37,7 +37,7 @@ vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
 vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
 vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
 vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
-vcom -explicit  -93 "../src/bootloader.ROM.vhd"
+vcom -explicit  -93 "../src/bootloader_flash.ROM.vhd"
 vcom -explicit  -93 "../../../lib/misc/rom_wb.vhd"
 
 # VGA

projects/mips_sys/src/tb_mips_sys.vhd

@@ -42,6 +42,8 @@ ARCHITECTURE behavior OF tb_mips_sys IS
 	constant AC97_CLK_PERIOD	: time := 83 ns;
 	constant ETH_CLK_PERIOD		: time := 7.7 ns;
 	constant LOOP_BACK_EN		: std_logic := '1';
+	constant WITH_TLB				: boolean := true;
+	constant KSEG_01_TRANSLATED		: boolean := true;
 	signal sys_rst_n_in : std_logic := '0';
 	signal sys_clk_in : std_logic := '1';
 	signal dip  : unsigned(7 downto 0) := (others => '0');
@@ -146,7 +148,9 @@ uut: entity work.mips_sys
 	GENERIC MAP
 	(
 		sys_freq_in			=> 100.000,
-		cpu_freq			=> 100.000,
+		cpu_freq			=> 60.000,
+		WITH_TLB			=> WITH_TLB,
+		TRANSLATE_KSEG0_1	=> KSEG_01_TRANSLATED,
 		sdram_phaseshift	=> 0,
 		tsvga				=> ts_vga_800_600_72
 	)
@@ -365,7 +369,7 @@ ac97_clk_gen : PROCESS
 
 FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a)
 	type file_t is file of integer;
-	file load_flash : file_t open read_mode is "blittertest_tb.elf.flash.bin";
+	file load_flash : file_t open read_mode is "test_dcache_sim.elf.flash.bin";
 	variable instr : integer;
 	variable index : natural;
 	variable temp : signed(31 downto 0);