- commit local changes after CVS2SVN
git-svn-id: http://moon:8086/svn/vhdl/trunk@1036 cc03376c-175c-47c8-b038-4cd826a8556b
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-142
@@ -1,142 +1,142 @@
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-------------------------------------------------
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-- Signal Debouncer
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-- Jeff Bazinet
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-- February 14, 2002
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-----------------------------------------------------------------------
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-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library lpm;
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use lpm.lpm_components.lpm_counter;
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entity debounce is
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generic(BUFFER_WIDTH: positive:= 30;
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CLOCK_DIV: positive:= 15
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);
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port( clock: in std_logic;
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reset: in std_logic;
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signal_in: in std_logic;
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signal_out: out std_logic
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);
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end entity debounce;
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architecture rtl of debounce is
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---------------------------------------------------------------
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-- SIGNAL DECLARATION
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---------------------------------------------------------------
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-- General
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signal reset_n: std_logic;
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-- SLOW CLOCK GENERATION
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signal clock_reg: std_logic_vector(CLOCK_DIV-1 downto 0);
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signal clock_reg_high: std_logic_vector(CLOCK_DIV-1 downto 1);
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signal clock_slow: std_logic;
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signal clock_slow_wire: std_logic;
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-- DATA BUFFER FILL
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signal counter_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
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signal data_buffer_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
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-- CHECK FOR DEBOUNCE STABILITY
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signal stable: std_logic;
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signal stable_old: std_logic;
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signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0);
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-- PUSH BUTTON ENABLE
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signal button_pushed: std_logic;
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begin
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---------------------------------------------------------------
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-- SLOW CLOCK GENERATION
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---------------------------------------------------------------
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COUNTER_1: lpm_counter
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generic map (lpm_width => CLOCK_DIV)
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port map (
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clock => clock,
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sclr => reset_n,
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cout => clock_slow_wire
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);
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process (clock) is
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begin
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clock_slow <= clock_slow_wire;
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end process;
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---------------------------------------------------------------
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-- DATA BUFFER FILL
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---------------------------------------------------------------
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process (clock) is
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begin
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if (reset = '0') then
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-- Initialization
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data_buffer_reg <= (others => '1');
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elsif rising_edge(clock_slow) then
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data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in;
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end if;
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end process;
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---------------------------------------------------------------
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-- CHECK FOR DEBOUNCE STABILITY
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---------------------------------------------------------------
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process (clock) is
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begin
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if (reset = '0') then
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-- Initialization
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stable <= '0';
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stable_old <= '0';
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stable_state_reg <= (others => '0');
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elsif rising_edge(clock) then
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if (data_buffer_reg = stable_state_reg) then
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stable <= '1';
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stable_state_reg <= (others => '0');
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else
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stable <= '0';
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end if;
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stable_old <= stable;
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end if;
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end process;
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---------------------------------------------------------------
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-- PUSH BUTTON ENABLE
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---------------------------------------------------------------
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process (clock) is
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begin
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if (reset = '0') then
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-- Initialization
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button_pushed <= '0';
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elsif rising_edge(clock) then
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if (stable_old = '0' and stable = '1') then
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button_pushed <= '1';
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else
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button_pushed <= '0';
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end if;
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end if;
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end process;
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---------------------------------------------------------------
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---------------------------------------------------------------
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signal_out <= button_pushed;
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reset_n <= not reset;
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end rtl;
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-------------------------------------------------
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-- Signal Debouncer
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-- Jeff Bazinet
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-- February 14, 2002
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-----------------------------------------------------------------------
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-- $Header: D:\usr\cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library lpm;
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use lpm.lpm_components.lpm_counter;
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entity debounce is
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generic(BUFFER_WIDTH: positive:= 30;
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CLOCK_DIV: positive:= 15
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);
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port( clock: in std_logic;
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reset: in std_logic;
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signal_in: in std_logic;
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signal_out: out std_logic
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);
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end entity debounce;
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architecture rtl of debounce is
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---------------------------------------------------------------
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-- SIGNAL DECLARATION
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---------------------------------------------------------------
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-- General
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signal reset_n: std_logic;
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-- SLOW CLOCK GENERATION
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signal clock_reg: std_logic_vector(CLOCK_DIV-1 downto 0);
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signal clock_reg_high: std_logic_vector(CLOCK_DIV-1 downto 1);
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signal clock_slow: std_logic;
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signal clock_slow_wire: std_logic;
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-- DATA BUFFER FILL
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signal counter_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
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signal data_buffer_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
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-- CHECK FOR DEBOUNCE STABILITY
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signal stable: std_logic;
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signal stable_old: std_logic;
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signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0);
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-- PUSH BUTTON ENABLE
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signal button_pushed: std_logic;
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begin
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---------------------------------------------------------------
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-- SLOW CLOCK GENERATION
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---------------------------------------------------------------
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COUNTER_1: lpm_counter
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generic map (lpm_width => CLOCK_DIV)
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port map (
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clock => clock,
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sclr => reset_n,
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cout => clock_slow_wire
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);
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process (clock) is
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begin
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clock_slow <= clock_slow_wire;
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end process;
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---------------------------------------------------------------
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-- DATA BUFFER FILL
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---------------------------------------------------------------
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process (clock) is
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begin
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if (reset = '0') then
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-- Initialization
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data_buffer_reg <= (others => '1');
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elsif rising_edge(clock_slow) then
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data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in;
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end if;
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end process;
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---------------------------------------------------------------
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-- CHECK FOR DEBOUNCE STABILITY
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---------------------------------------------------------------
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process (clock) is
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begin
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if (reset = '0') then
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-- Initialization
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stable <= '0';
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stable_old <= '0';
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stable_state_reg <= (others => '0');
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elsif rising_edge(clock) then
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if (data_buffer_reg = stable_state_reg) then
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stable <= '1';
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stable_state_reg <= (others => '0');
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else
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stable <= '0';
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end if;
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stable_old <= stable;
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end if;
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end process;
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---------------------------------------------------------------
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-- PUSH BUTTON ENABLE
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---------------------------------------------------------------
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process (clock) is
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begin
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if (reset = '0') then
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-- Initialization
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button_pushed <= '0';
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elsif rising_edge(clock) then
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if (stable_old = '0' and stable = '1') then
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button_pushed <= '1';
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else
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button_pushed <= '0';
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end if;
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end if;
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end process;
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---------------------------------------------------------------
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---------------------------------------------------------------
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signal_out <= button_pushed;
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reset_n <= not reset;
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end rtl;
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