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git-svn-id: http://moon:8086/svn/vhdl/trunk@1036 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2014-07-20 13:30:14 +00:00
parent 175cf3a4f4
commit 70e48af3ab
58 changed files with 9720 additions and 9650 deletions
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lib/misc/async_port_wb.vhd
+317 -317
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@@ -1,317 +1,317 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010-02-09 09:56:37 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.async_types.all;
------------------------------------------------------------------
entity async_port_wb is
Generic
(
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
page_mode_en : in STD_LOGIC;
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
async_wr : out std_logic;
async_rd : out std_logic;
async_be : out unsigned(byte_sel_width-1 downto 0);
async_rst : out std_logic
);
end async_port_wb;
architecture Behavioral of async_port_wb is
type async_t is record
cs : std_logic;
wr : std_logic;
rd : std_logic;
rst : std_logic;
drive_d : std_logic;
end record;
type async_state_t is (start, reset, idle, leadin, pulse, leadout, release);
signal s, sn : async_state_t;
signal as : async_t;
signal ack : std_logic;
signal cc_rst : std_logic;
signal cycle_cnt : natural range 0 to 31;
signal cycle_reload : natural range 0 to 31;
signal rdy : std_logic;
signal rdyo : std_logic;
signal en : std_logic;
signal is_idle : std_logic;
signal DAT_I_r : unsigned(data_width-1 downto 0);
signal SEL_I_r : unsigned(byte_sel_width-1 downto 0);
signal WE_I_r : std_logic;
signal ADDR_I_r : unsigned(addr_width-1 downto 0);
signal page_mode_en_r : std_logic;
signal do_page_read : std_logic;
------------------------------------------------------------------
begin
ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk) > 0 report "Read pulse length must be greater than zero!" severity failure;
ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk) > 0 report "Write pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) > 1)) report "Read page pulse length must be greater than one!" severity failure;
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;
do_page_read <= '1' when (async_timespec.can_page_rd and (WE_I = '0') and (WE_I_r = '0') and (ADDR_I(addr_width-1 downto async_timespec.nbits_page_rd) = ADDR_I_r(addr_width-1 downto async_timespec.nbits_page_rd))) else '0';
proc_cycle_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if cc_rst = '1' then
cycle_cnt <= cycle_reload;
elsif cycle_cnt /= 0 then
cycle_cnt <= cycle_cnt - 1;
end if;
end if;
end process;
------------------------------------------------------------------
proc_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
s <= start;
else
s <= sn;
end if;
end if;
end process;
proc_state:
process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
begin
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
as.wr <= '0';
as.rd <= '0';
as.drive_d <= '0';
ack <= '0';
rdy <= '0';
is_idle <= '0';
sn <= s;
case s is
when start =>
cc_rst <= '1';
sn <= reset;
when reset =>
as.rst <= '1';
if cycle_cnt = 0 then
sn <= idle;
end if;
when idle =>
rdy <= '1';
is_idle <= '1';
if en = '1' then
as.cs <= '1';
cc_rst <= '1';
if to_cycles(async_timespec.T_leadin, f_sysclk) = 0 then
sn <= pulse;
if WE_I = '1' then
cycle_reload <= 0;
sn <= leadin; -- always lead-in for writes
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
as.rd <= '1';
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk) - 1;
sn <= leadin;
end if;
end if;
when leadin =>
as.cs <= '1';
as.rd <= not WE_I_r;
as.drive_d <= WE_I_r;
as.wr <= WE_I_r;
if cycle_cnt = 0 then
cc_rst <= '1';
sn <= pulse;
if WE_I_r = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk) - 1;
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
end if;
end if;
when pulse =>
as.cs <= '1';
as.rd <= not WE_I_r;
as.drive_d <= WE_I_r;
as.wr <= WE_I_r;
if cycle_cnt = 0 then
as.wr <= '0';
cc_rst <= '1';
ack <= not WE_I_r;
rdy <= do_page_read;
if en = '1' and do_page_read = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) - 1;
sn <= pulse;
elsif to_cycles(async_timespec.T_leadout, f_sysclk) = 0 then
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
sn <= release;
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk) - 1;
sn <= leadout;
end if;
end if;
when leadout =>
as.cs <= '1';
as.drive_d <= WE_I_r;
if cycle_cnt = 0 then
cc_rst <= '1';
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
sn <= release;
end if;
end if;
when release =>
if cycle_cnt = 0 then
sn <= idle;
end if;
when others =>
sn <= idle;
end case;
end process;
------------------------------------------------------------------
output_ctrl:
process(CLK_I)
begin
if rising_edge(CLK_I) then
async_cs <= (not async_timespec.pol_cs) xor as.cs;
async_wr <= (not async_timespec.pol_we) xor as.wr;
async_rd <= (not async_timespec.pol_oe) xor as.rd;
async_rst <= (not async_timespec.pol_rst) xor as.rst;
end if;
end process;
------------------------------------------------------------------
din_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if as.rd = '1' then
DAT_O(data_width-1 downto 0) <= async_d;
end if;
end if;
end process;
------------------------------------------------------------------
output_addr:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
async_a <= (others => '0');
SEL_I_r <= (others => '0');
elsif en = '1' and rdy = '1' then
async_a <= ADDR_I(addr_width-1 downto 0);
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I(byte_sel_width-1 downto 0));
SEL_I_r <= SEL_I(byte_sel_width-1 downto 0);
if is_idle = '1' then
ADDR_I_r <= ADDR_I(addr_width-1 downto 0);
end if;
end if;
end if;
end process;
------------------------------------------------------------------
data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
page_mode_en_r <= page_mode_en;
if en = '1' and rdy = '1' then
DAT_I_r <= DAT_I(data_width-1 downto 0);
WE_I_r <= WE_I;
end if;
end if;
end process;
------------------------------------------------------------------
output_SRDY:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
rdyo <= '1';
elsif en = '1' then
rdyo <= rdy and not rdyo;
end if;
end if;
end process;
------------------------------------------------------------------
output_ACK:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= ack;
end if;
end if;
end process;
------------------------------------------------------------------
output_data:
process(CLK_I)
begin
if rising_edge(CLK_I) then
async_d <= (others => 'Z');
if as.drive_d = '1' then
async_d <= DAT_I_r;
end if;
end if;
end process;
------------------------------------------------------------------
end Behavioral;
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010/02/09 09:56:37 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.async_types.all;
------------------------------------------------------------------
entity async_port_wb is
Generic
(
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
page_mode_en : in STD_LOGIC;
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
async_wr : out std_logic;
async_rd : out std_logic;
async_be : out unsigned(byte_sel_width-1 downto 0);
async_rst : out std_logic
);
end async_port_wb;
architecture Behavioral of async_port_wb is
type async_t is record
cs : std_logic;
wr : std_logic;
rd : std_logic;
rst : std_logic;
drive_d : std_logic;
end record;
type async_state_t is (start, reset, idle, leadin, pulse, leadout, release);
signal s, sn : async_state_t;
signal as : async_t;
signal ack : std_logic;
signal cc_rst : std_logic;
signal cycle_cnt : natural range 0 to 31;
signal cycle_reload : natural range 0 to 31;
signal rdy : std_logic;
signal rdyo : std_logic;
signal en : std_logic;
signal is_idle : std_logic;
signal DAT_I_r : unsigned(data_width-1 downto 0);
signal SEL_I_r : unsigned(byte_sel_width-1 downto 0);
signal WE_I_r : std_logic;
signal ADDR_I_r : unsigned(addr_width-1 downto 0);
signal page_mode_en_r : std_logic;
signal do_page_read : std_logic;
------------------------------------------------------------------
begin
ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk) > 0 report "Read pulse length must be greater than zero!" severity failure;
ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk) > 0 report "Write pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) > 1)) report "Read page pulse length must be greater than one!" severity failure;
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;
do_page_read <= '1' when (async_timespec.can_page_rd and (WE_I = '0') and (WE_I_r = '0') and (ADDR_I(addr_width-1 downto async_timespec.nbits_page_rd) = ADDR_I_r(addr_width-1 downto async_timespec.nbits_page_rd))) else '0';
proc_cycle_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if cc_rst = '1' then
cycle_cnt <= cycle_reload;
elsif cycle_cnt /= 0 then
cycle_cnt <= cycle_cnt - 1;
end if;
end if;
end process;
------------------------------------------------------------------
proc_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
s <= start;
else
s <= sn;
end if;
end if;
end process;
proc_state:
process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
begin
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
as.wr <= '0';
as.rd <= '0';
as.drive_d <= '0';
ack <= '0';
rdy <= '0';
is_idle <= '0';
sn <= s;
case s is
when start =>
cc_rst <= '1';
sn <= reset;
when reset =>
as.rst <= '1';
if cycle_cnt = 0 then
sn <= idle;
end if;
when idle =>
rdy <= '1';
is_idle <= '1';
if en = '1' then
as.cs <= '1';
cc_rst <= '1';
if to_cycles(async_timespec.T_leadin, f_sysclk) = 0 then
sn <= pulse;
if WE_I = '1' then
cycle_reload <= 0;
sn <= leadin; -- always lead-in for writes
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
as.rd <= '1';
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk) - 1;
sn <= leadin;
end if;
end if;
when leadin =>
as.cs <= '1';
as.rd <= not WE_I_r;
as.drive_d <= WE_I_r;
as.wr <= WE_I_r;
if cycle_cnt = 0 then
cc_rst <= '1';
sn <= pulse;
if WE_I_r = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk) - 1;
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
end if;
end if;
when pulse =>
as.cs <= '1';
as.rd <= not WE_I_r;
as.drive_d <= WE_I_r;
as.wr <= WE_I_r;
if cycle_cnt = 0 then
as.wr <= '0';
cc_rst <= '1';
ack <= not WE_I_r;
rdy <= do_page_read;
if en = '1' and do_page_read = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) - 1;
sn <= pulse;
elsif to_cycles(async_timespec.T_leadout, f_sysclk) = 0 then
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
sn <= release;
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk) - 1;
sn <= leadout;
end if;
end if;
when leadout =>
as.cs <= '1';
as.drive_d <= WE_I_r;
if cycle_cnt = 0 then
cc_rst <= '1';
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
sn <= release;
end if;
end if;
when release =>
if cycle_cnt = 0 then
sn <= idle;
end if;
when others =>
sn <= idle;
end case;
end process;
------------------------------------------------------------------
output_ctrl:
process(CLK_I)
begin
if rising_edge(CLK_I) then
async_cs <= (not async_timespec.pol_cs) xor as.cs;
async_wr <= (not async_timespec.pol_we) xor as.wr;
async_rd <= (not async_timespec.pol_oe) xor as.rd;
async_rst <= (not async_timespec.pol_rst) xor as.rst;
end if;
end process;
------------------------------------------------------------------
din_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if as.rd = '1' then
DAT_O(data_width-1 downto 0) <= async_d;
end if;
end if;
end process;
------------------------------------------------------------------
output_addr:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
async_a <= (others => '0');
SEL_I_r <= (others => '0');
elsif en = '1' and rdy = '1' then
async_a <= ADDR_I(addr_width-1 downto 0);
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I(byte_sel_width-1 downto 0));
SEL_I_r <= SEL_I(byte_sel_width-1 downto 0);
if is_idle = '1' then
ADDR_I_r <= ADDR_I(addr_width-1 downto 0);
end if;
end if;
end if;
end process;
------------------------------------------------------------------
data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
page_mode_en_r <= page_mode_en;
if en = '1' and rdy = '1' then
DAT_I_r <= DAT_I(data_width-1 downto 0);
WE_I_r <= WE_I;
end if;
end if;
end process;
------------------------------------------------------------------
output_SRDY:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
rdyo <= '1';
elsif en = '1' then
rdyo <= rdy and not rdyo;
end if;
end if;
end process;
------------------------------------------------------------------
output_ACK:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= ack;
end if;
end if;
end process;
------------------------------------------------------------------
output_data:
process(CLK_I)
begin
if rising_edge(CLK_I) then
async_d <= (others => 'Z');
if as.drive_d = '1' then
async_d <= DAT_I_r;
end if;
end if;
end process;
------------------------------------------------------------------
end Behavioral;
lib/misc/bbfifo.vhd
+123 -123
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@@ -1,123 +1,123 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008-10-20 19:26:01 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity bbfifo is
Generic
(
depth : integer := 2;
data_width : integer := 8
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
re : in STD_LOGIC;
we : in STD_LOGIC;
ready : out STD_LOGIC;
avail : out STD_LOGIC;
din : in unsigned(data_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
end bbfifo;
architecture Behavioral of bbfifo is
type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
signal req : unsigned(0 to depth);
signal rdy : unsigned(1 to depth+1);
signal bucket_array : bucket_array_t;
signal ce_in : unsigned(1 to depth);
signal ce_out : unsigned(1 to depth);
begin
req(0) <= we;
rdy(depth+1) <= re;
ready <= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0';
avail <= req(depth);
bucket_array(0) <= din;
dout <= bucket_array(depth);
gen_ce:
for i in 1 to depth generate
begin
process (rdy, req)
begin
ce_in(i) <= not req(i) and req(i-1);
end process;
end generate;
gen_rdy:
for i in 1 to depth generate
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
rdy(i) <= '1';
elsif req(i-1) = '1' then
rdy(i) <= rdy(i+1);
end if;
end if;
end process;
end generate;
gen_req:
for i in 1 to depth generate
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
req(i) <= '0';
elsif rdy(i+1) = '1' then
req(i) <= req(i-1);
end if;
end if;
end process;
end generate;
gen_data:
for i in 1 to depth generate
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
bucket_array(i) <= (others => '0');
elsif req(i-1) = '1' then
bucket_array(i) <= bucket_array(i-1);
end if;
end if;
end process;
end generate;
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008/10/20 19:26:01 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity bbfifo is
Generic
(
depth : integer := 2;
data_width : integer := 8
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
re : in STD_LOGIC;
we : in STD_LOGIC;
ready : out STD_LOGIC;
avail : out STD_LOGIC;
din : in unsigned(data_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
end bbfifo;
architecture Behavioral of bbfifo is
type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
signal req : unsigned(0 to depth);
signal rdy : unsigned(1 to depth+1);
signal bucket_array : bucket_array_t;
signal ce_in : unsigned(1 to depth);
signal ce_out : unsigned(1 to depth);
begin
req(0) <= we;
rdy(depth+1) <= re;
ready <= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0';
avail <= req(depth);
bucket_array(0) <= din;
dout <= bucket_array(depth);
gen_ce:
for i in 1 to depth generate
begin
process (rdy, req)
begin
ce_in(i) <= not req(i) and req(i-1);
end process;
end generate;
gen_rdy:
for i in 1 to depth generate
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
rdy(i) <= '1';
elsif req(i-1) = '1' then
rdy(i) <= rdy(i+1);
end if;
end if;
end process;
end generate;
gen_req:
for i in 1 to depth generate
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
req(i) <= '0';
elsif rdy(i+1) = '1' then
req(i) <= req(i-1);
end if;
end if;
end process;
end generate;
gen_data:
for i in 1 to depth generate
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
bucket_array(i) <= (others => '0');
elsif req(i-1) = '1' then
bucket_array(i) <= bucket_array(i-1);
end if;
end if;
end process;
end generate;
end Behavioral;
lib/misc/debounce.vhd
+91 -91
View File
@@ -1,91 +1,91 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:34:24 10/23/05
-- Design Name:
-- Module Name: debounce - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity debounce is
Generic ( ncyc_latency : integer := 100);
Port ( rst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
end debounce;
architecture Behavioral of debounce is
type debounce_state_t is (init_st, wait_st, rel_st);
signal debounce_cs : debounce_state_t;
signal debounce_ns : debounce_state_t;
signal count : integer range 0 to ncyc_latency;
signal input_last : std_logic;
begin
debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input)
begin
if (rst = '1') then
count <= 0;
output <= input;
input_last <= input;
else
if rising_edge(clk) then
debounce_cs <= debounce_ns;
if (debounce_cs = wait_st) then
if (count /= 0) then
count <= count - 1;
end if;
else
count <= ncyc_latency;
if (debounce_cs = rel_st) then
output <= input;
input_last <= input;
end if;
end if;
end if;
end if;
end process;
debounce_in: process(rst, clk, input, input_last, debounce_cs, count)
begin
debounce_ns <= debounce_cs;
case debounce_cs is
when init_st =>
if (input /= input_last) then
debounce_ns <= wait_st;
end if;
when wait_st =>
if (count = 0) then
debounce_ns <= rel_st;
end if;
when others =>
debounce_ns <= init_st;
end case;
end process;
end Behavioral;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:34:24 10/23/05
-- Design Name:
-- Module Name: debounce - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity debounce is
Generic ( ncyc_latency : integer := 100);
Port ( rst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
end debounce;
architecture Behavioral of debounce is
type debounce_state_t is (init_st, wait_st, rel_st);
signal debounce_cs : debounce_state_t;
signal debounce_ns : debounce_state_t;
signal count : integer range 0 to ncyc_latency;
signal input_last : std_logic;
begin
debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input)
begin
if (rst = '1') then
count <= 0;
output <= input;
input_last <= input;
else
if rising_edge(clk) then
debounce_cs <= debounce_ns;
if (debounce_cs = wait_st) then
if (count /= 0) then
count <= count - 1;
end if;
else
count <= ncyc_latency;
if (debounce_cs = rel_st) then
output <= input;
input_last <= input;
end if;
end if;
end if;
end if;
end process;
debounce_in: process(rst, clk, input, input_last, debounce_cs, count)
begin
debounce_ns <= debounce_cs;
case debounce_cs is
when init_st =>
if (input /= input_last) then
debounce_ns <= wait_st;
end if;
when wait_st =>
if (count = 0) then
debounce_ns <= rel_st;
end if;
when others =>
debounce_ns <= init_st;
end case;
end process;
end Behavioral;
lib/misc/debounce2.vhd
+142 -142
View File
@@ -1,142 +1,142 @@
-------------------------------------------------
-- Signal Debouncer
-- Jeff Bazinet
-- February 14, 2002
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.lpm_counter;
entity debounce is
generic(BUFFER_WIDTH: positive:= 30;
CLOCK_DIV: positive:= 15
);
port( clock: in std_logic;
reset: in std_logic;
signal_in: in std_logic;
signal_out: out std_logic
);
end entity debounce;
architecture rtl of debounce is
---------------------------------------------------------------
-- SIGNAL DECLARATION
---------------------------------------------------------------
-- General
signal reset_n: std_logic;
-- SLOW CLOCK GENERATION
signal clock_reg: std_logic_vector(CLOCK_DIV-1 downto 0);
signal clock_reg_high: std_logic_vector(CLOCK_DIV-1 downto 1);
signal clock_slow: std_logic;
signal clock_slow_wire: std_logic;
-- DATA BUFFER FILL
signal counter_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
signal data_buffer_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
-- CHECK FOR DEBOUNCE STABILITY
signal stable: std_logic;
signal stable_old: std_logic;
signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0);
-- PUSH BUTTON ENABLE
signal button_pushed: std_logic;
begin
---------------------------------------------------------------
-- SLOW CLOCK GENERATION
---------------------------------------------------------------
COUNTER_1: lpm_counter
generic map (lpm_width => CLOCK_DIV)
port map (
clock => clock,
sclr => reset_n,
cout => clock_slow_wire
);
process (clock) is
begin
clock_slow <= clock_slow_wire;
end process;
---------------------------------------------------------------
-- DATA BUFFER FILL
---------------------------------------------------------------
process (clock) is
begin
if (reset = '0') then
-- Initialization
data_buffer_reg <= (others => '1');
elsif rising_edge(clock_slow) then
data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in;
end if;
end process;
---------------------------------------------------------------
-- CHECK FOR DEBOUNCE STABILITY
---------------------------------------------------------------
process (clock) is
begin
if (reset = '0') then
-- Initialization
stable <= '0';
stable_old <= '0';
stable_state_reg <= (others => '0');
elsif rising_edge(clock) then
if (data_buffer_reg = stable_state_reg) then
stable <= '1';
stable_state_reg <= (others => '0');
else
stable <= '0';
end if;
stable_old <= stable;
end if;
end process;
---------------------------------------------------------------
-- PUSH BUTTON ENABLE
---------------------------------------------------------------
process (clock) is
begin
if (reset = '0') then
-- Initialization
button_pushed <= '0';
elsif rising_edge(clock) then
if (stable_old = '0' and stable = '1') then
button_pushed <= '1';
else
button_pushed <= '0';
end if;
end if;
end process;
---------------------------------------------------------------
---------------------------------------------------------------
signal_out <= button_pushed;
reset_n <= not reset;
end rtl;
-------------------------------------------------
-- Signal Debouncer
-- Jeff Bazinet
-- February 14, 2002
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.lpm_counter;
entity debounce is
generic(BUFFER_WIDTH: positive:= 30;
CLOCK_DIV: positive:= 15
);
port( clock: in std_logic;
reset: in std_logic;
signal_in: in std_logic;
signal_out: out std_logic
);
end entity debounce;
architecture rtl of debounce is
---------------------------------------------------------------
-- SIGNAL DECLARATION
---------------------------------------------------------------
-- General
signal reset_n: std_logic;
-- SLOW CLOCK GENERATION
signal clock_reg: std_logic_vector(CLOCK_DIV-1 downto 0);
signal clock_reg_high: std_logic_vector(CLOCK_DIV-1 downto 1);
signal clock_slow: std_logic;
signal clock_slow_wire: std_logic;
-- DATA BUFFER FILL
signal counter_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
signal data_buffer_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
-- CHECK FOR DEBOUNCE STABILITY
signal stable: std_logic;
signal stable_old: std_logic;
signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0);
-- PUSH BUTTON ENABLE
signal button_pushed: std_logic;
begin
---------------------------------------------------------------
-- SLOW CLOCK GENERATION
---------------------------------------------------------------
COUNTER_1: lpm_counter
generic map (lpm_width => CLOCK_DIV)
port map (
clock => clock,
sclr => reset_n,
cout => clock_slow_wire
);
process (clock) is
begin
clock_slow <= clock_slow_wire;
end process;
---------------------------------------------------------------
-- DATA BUFFER FILL
---------------------------------------------------------------
process (clock) is
begin
if (reset = '0') then
-- Initialization
data_buffer_reg <= (others => '1');
elsif rising_edge(clock_slow) then
data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in;
end if;
end process;
---------------------------------------------------------------
-- CHECK FOR DEBOUNCE STABILITY
---------------------------------------------------------------
process (clock) is
begin
if (reset = '0') then
-- Initialization
stable <= '0';
stable_old <= '0';
stable_state_reg <= (others => '0');
elsif rising_edge(clock) then
if (data_buffer_reg = stable_state_reg) then
stable <= '1';
stable_state_reg <= (others => '0');
else
stable <= '0';
end if;
stable_old <= stable;
end if;
end process;
---------------------------------------------------------------
-- PUSH BUTTON ENABLE
---------------------------------------------------------------
process (clock) is
begin
if (reset = '0') then
-- Initialization
button_pushed <= '0';
elsif rising_edge(clock) then
if (stable_old = '0' and stable = '1') then
button_pushed <= '1';
else
button_pushed <= '0';
end if;
end if;
end process;
---------------------------------------------------------------
---------------------------------------------------------------
signal_out <= button_pushed;
reset_n <= not reset;
end rtl;
lib/misc/dpram_1w1r.vhd
+79 -79
View File
@@ -1,79 +1,79 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r is
Generic (
addr_width : integer := 3;
data_width : integer := 8
);
Port (
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r;
architecture Behavioral of dpram_1w1r is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
process (clka)
begin
if clka'event and clka = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clkb)
begin
if clkb'event and clkb = '1' then
if en_b = '1' then
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r is
Generic (
addr_width : integer := 3;
data_width : integer := 8
);
Port (
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r;
architecture Behavioral of dpram_1w1r is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
process (clka)
begin
if clka'event and clka = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clkb)
begin
if clkb'event and clkb = '1' then
if en_b = '1' then
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
lib/misc/dpram_1w1r1c_sim.vhd
+77 -77
View File
@@ -1,77 +1,77 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r1c_sim.vhd,v 1.1 2013-02-07 14:15:37 jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r1c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r1c;
architecture Behavioral of dpram_1w1r1c is
signal addr_b_r : unsigned (addr_width-1 downto 0);
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
if en_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
dout_b <= RAM(to_integer(addr_b_r));
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r1c_sim.vhd,v 1.1 2013/02/07 14:15:37 jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r1c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r1c;
architecture Behavioral of dpram_1w1r1c is
signal addr_b_r : unsigned (addr_width-1 downto 0);
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
if en_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
dout_b <= RAM(to_integer(addr_b_r));
end Behavioral;
lib/misc/dpram_1w1r1c_xil.vhd
+77 -77
View File
@@ -1,77 +1,77 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r1c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r1c;
architecture Behavioral of dpram_1w1r1c is
signal addr_b_r : unsigned (addr_width-1 downto 0);
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
if en_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
dout_b <= RAM(to_integer(addr_b_r));
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r1c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r1c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r1c;
architecture Behavioral of dpram_1w1r1c is
signal addr_b_r : unsigned (addr_width-1 downto 0);
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
if en_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
dout_b <= RAM(to_integer(addr_b_r));
end Behavioral;
lib/misc/dpram_1w1r2c_sim.vhd
+82 -82
View File
@@ -1,82 +1,82 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r2c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r2c is
Generic (
addr_width : integer := 3;
data_width : integer := 8
);
Port (
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r2c;
architecture Behavioral of dpram_1w1r2c is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
signal addr_b_r : unsigned (addr_width-1 downto 0);
begin
dout_b <= RAM(to_integer(addr_b_r));
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r2c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r2c is
Generic (
addr_width : integer := 3;
data_width : integer := 8
);
Port (
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r2c;
architecture Behavioral of dpram_1w1r2c is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
signal addr_b_r : unsigned (addr_width-1 downto 0);
begin
dout_b <= RAM(to_integer(addr_b_r));
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
lib/misc/dpram_1w1r2c_xil.vhd
+82 -82
View File
@@ -1,82 +1,82 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r2c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r2c is
Generic (
addr_width : integer := 3;
data_width : integer := 8
);
Port (
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r2c;
architecture Behavioral of dpram_1w1r2c is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
signal addr_b_r : unsigned (addr_width-1 downto 0);
begin
dout_b <= RAM(to_integer(addr_b_r));
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r2c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r2c is
Generic (
addr_width : integer := 3;
data_width : integer := 8
);
Port (
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r2c;
architecture Behavioral of dpram_1w1r2c is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
signal addr_b_r : unsigned (addr_width-1 downto 0);
begin
dout_b <= RAM(to_integer(addr_b_r));
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
lib/misc/dpram_1w1r_dist.vhd
+84 -84
View File
@@ -1,84 +1,84 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r_dist is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r_dist;
architecture Behavioral of dpram_1w1r_dist is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
attribute ram_style : string;
attribute ram_style of RAM: signal is "distributed";
begin
process (clka)
begin
if clka'event and clka = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clkb)
begin
if clkb'event and clkb = '1' then
if en_b = '1' then
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r_dist is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r_dist;
architecture Behavioral of dpram_1w1r_dist is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
attribute ram_style : string;
attribute ram_style of RAM: signal is "distributed";
begin
process (clka)
begin
if clka'event and clka = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clkb)
begin
if clkb'event and clkb = '1' then
if en_b = '1' then
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
lib/misc/dpram_1w2r1c_sim.vhd
+86 -86
View File
@@ -1,86 +1,86 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w2r1c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_1w2r1c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w2r1c;
architecture Behavioral of dpram_1w2r1c is
constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r));
process (clk)
begin
if clk'event and clk = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
addr_a_r <= addr_a;
end if;
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
if en_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w2r1c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_1w2r1c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w2r1c;
architecture Behavioral of dpram_1w2r1c is
constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r));
process (clk)
begin
if clk'event and clk = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
addr_a_r <= addr_a;
end if;
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
if en_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
lib/misc/dpram_1w2r1c_xil.vhd
+80 -80
View File
@@ -1,80 +1,80 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w2r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_1w2r1c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w2r1c;
architecture Behavioral of dpram_1w2r1c is
begin
inst_dpram: entity work.dpram_2w2r2c
GENERIC MAP
(
addr_width => addr_width,
data_width => data_width
)
PORT MAP
(
clk_a => clk,
clk_b => clk,
en_a => en_a,
en_b => en_b,
we_a => we_a,
we_b => '0',
addr_a => addr_a,
addr_b => addr_b,
din_a => din_a,
din_b => din_a,
dout_a => dout_a,
dout_b => dout_b
);
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w2r1c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_1w2r1c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w2r1c;
architecture Behavioral of dpram_1w2r1c is
begin
inst_dpram: entity work.dpram_2w2r2c
GENERIC MAP
(
addr_width => addr_width,
data_width => data_width
)
PORT MAP
(
clk_a => clk,
clk_b => clk,
en_a => en_a,
en_b => en_b,
we_a => we_a,
we_b => '0',
addr_a => addr_a,
addr_b => addr_b,
din_a => din_a,
din_b => din_a,
dout_a => dout_a,
dout_b => dout_b
);
end Behavioral;
lib/misc/dpram_2w2r.vhd
+88 -88
View File
@@ -1,88 +1,88 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009-01-14 20:26:29 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r;
architecture Behavioral of dpram_2w2r is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
begin
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
end if;
dout_a <= RAM(to_integer(addr_a));
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
end if;
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009/01/14 20:26:29 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r;
architecture Behavioral of dpram_2w2r is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
begin
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
end if;
dout_a <= RAM(to_integer(addr_a));
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
end if;
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
lib/misc/dpram_2w2r1c_sim.vhd
+88 -88
View File
@@ -1,88 +1,88 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r1c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r1c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r1c;
architecture Behavioral of dpram_2w2r1c is
constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
signal contention : std_logic;
begin
dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r));
contention <= en_a and we_a and en_b and we_b;
process (clk)
begin
if clk'event and clk = '1' then
assert contention = '0' report "dpram_2w2r1c: Simultaneous write on Port A and Port B!" severity warning;
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
addr_a_r <= addr_a;
end if;
if en_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) <= din_b;
end if;
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r1c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r1c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r1c;
architecture Behavioral of dpram_2w2r1c is
constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
signal contention : std_logic;
begin
dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r));
contention <= en_a and we_a and en_b and we_b;
process (clk)
begin
if clk'event and clk = '1' then
assert contention = '0' report "dpram_2w2r1c: Simultaneous write on Port A and Port B!" severity warning;
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
addr_a_r <= addr_a;
end if;
if en_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) <= din_b;
end if;
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
lib/misc/dpram_2w2r1c_xil.vhd
+82 -82
View File
@@ -1,82 +1,82 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r1c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r1c;
architecture Behavioral of dpram_2w2r1c is
begin
inst_dpram: entity work.dpram_2w2r2c
GENERIC MAP
(
addr_width => addr_width,
data_width => data_width
)
PORT MAP
(
clk_a => clk,
clk_b => clk,
en_a => en_a,
en_b => en_b,
we_a => we_a,
we_b => we_b,
addr_a => addr_a,
addr_b => addr_b,
din_a => din_a,
din_b => din_a,
dout_a => dout_a,
dout_b => dout_b
);
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r1c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r1c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r1c;
architecture Behavioral of dpram_2w2r1c is
begin
inst_dpram: entity work.dpram_2w2r2c
GENERIC MAP
(
addr_width => addr_width,
data_width => data_width
)
PORT MAP
(
clk_a => clk,
clk_b => clk,
en_a => en_a,
en_b => en_b,
we_a => we_a,
we_b => we_b,
addr_a => addr_a,
addr_b => addr_b,
din_a => din_a,
din_b => din_a,
dout_a => dout_a,
dout_b => dout_b
);
end Behavioral;
lib/misc/dpram_2w2r2c_sim.vhd
+95 -95
View File
@@ -1,95 +1,95 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r2c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r2c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r2c;
architecture Behavioral of dpram_2w2r2c is
constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r));
process (clk_a, clk_b)
begin
if clk_a'event and clk_a = '1' and en_a = '1' and we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
elsif clk_b'event and clk_b = '1' and en_b = '1' and we_b = '1' then
RAM(to_integer(addr_b)) <= din_b;
end if;
end process;
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
addr_a_r <= addr_a;
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r2c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r2c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r2c;
architecture Behavioral of dpram_2w2r2c is
constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r));
process (clk_a, clk_b)
begin
if clk_a'event and clk_a = '1' and en_a = '1' and we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
elsif clk_b'event and clk_b = '1' and en_b = '1' and we_b = '1' then
RAM(to_integer(addr_b)) <= din_b;
end if;
end process;
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
addr_a_r <= addr_a;
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
lib/misc/dpram_2w2r2c_xil.vhd
+93 -93
View File
@@ -1,93 +1,93 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r2c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r2c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r2c;
architecture Behavioral of dpram_2w2r2c is
constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
begin
dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r));
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
end if;
addr_a_r <= addr_a;
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
end if;
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r2c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r2c is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r2c;
architecture Behavioral of dpram_2w2r2c is
constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
begin
dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r));
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
end if;
addr_a_r <= addr_a;
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
end if;
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
lib/misc/flash_port_wb.vhd
+293 -293
View File
@@ -1,293 +1,293 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.2 2010-03-13 11:06:43 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.async_types.all;
------------------------------------------------------------------
entity flash_port_wb is
Generic
(
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
async_timespec : async_timespec_t
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
port_bsyi : in std_logic;
port_bsyo : out std_logic;
port_a : out unsigned(addr_width-1 downto 0);
port_di : in unsigned(data_width-1 downto 0);
port_do : out unsigned(data_width-1 downto 0);
port_d_drv : out STD_LOGIC;
port_wr : out STD_LOGIC;
port_rd : out STD_LOGIC;
flash_cs : out std_logic;
flash_rst : out std_logic
);
end flash_port_wb;
architecture Behavioral of flash_port_wb is
type async_t is record
cs : std_logic;
wr : std_logic;
rd : std_logic;
rst : std_logic;
drive_d : std_logic;
end record;
type async_state_t is (start, reset, idle, go, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
signal s, sn : async_state_t;
signal as : async_t;
signal ack : std_logic;
signal cc_rst : std_logic;
signal cycle_cnt : natural range 0 to 31;
signal cycle_reload : natural range 0 to 31;
signal rdy : std_logic;
signal rdyo : std_logic;
signal en : std_logic;
signal we_reg : std_logic;
signal data_reg : unsigned(data_width-1 downto 0);
signal addr_reg : unsigned(addr_width-1 downto 0);
------------------------------------------------------------------
begin
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;
port_a <= addr_reg;
port_do <= data_reg;
port_d_drv <= as.drive_d;
port_wr <= (not async_timespec.pol_we) xor as.wr;
port_rd <= (not async_timespec.pol_oe) xor as.rd;
proc_cycle_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if cc_rst = '1' then
cycle_cnt <= cycle_reload;
elsif cycle_cnt /= 0 then
cycle_cnt <= cycle_cnt - 1;
end if;
end if;
end process;
------------------------------------------------------------------
proc_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
s <= start;
else
s <= sn;
end if;
end if;
end process;
proc_state:
process(s, cycle_cnt, en, we_reg, port_bsyi)
begin
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
as.wr <= '0';
as.rd <= '0';
as.drive_d <= '0';
ack <= '0';
rdy <= '0';
port_bsyo <= '1';
sn <= s;
case s is
when start =>
cc_rst <= '1';
sn <= reset;
when reset =>
as.rst <= '1';
if cycle_cnt = 0 then
sn <= idle;
end if;
when idle =>
port_bsyo <= '0';
rdy <= '1';
if en = '1' then
sn <= go;
end if;
when go =>
port_bsyo <= '0';
if port_bsyi = '0' then
as.cs <= '1';
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk)-1;
if we_reg = '0' then
sn <= leadin_rd;
else
sn <= leadin_wr;
end if;
end if;
when leadin_rd =>
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk)-1;
as.rd <= '1';
sn <= read;
end if;
when leadin_wr =>
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk)-1;
as.wr <= '1';
as.drive_d <= '1';
sn <= write;
end if;
when read =>
as.cs <= '1';
as.rd <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
-- as.rd <= '0';
sn <= leadout_rd;
ack <= '1';
end if;
when write =>
as.drive_d <= '1';
as.cs <= '1';
as.wr <= '1';
if cycle_cnt = 0 then
as.wr <= '0';
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
sn <= leadout_wr;
-- ack <= '1';
end if;
when leadout_rd =>
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
sn <= release;
as.cs <= '0';
end if;
when leadout_wr =>
as.cs <= '1';
as.drive_d <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
sn <= release;
as.cs <= '0';
end if;
when release =>
if cycle_cnt = 0 then
sn <= idle;
end if;
when others =>
sn <= idle;
end case;
end process;
------------------------------------------------------------------
output_ctrl:
process(CLK_I)
begin
if rising_edge(CLK_I) then
flash_cs <= (not async_timespec.pol_cs) xor as.cs;
flash_rst <= (not async_timespec.pol_rst) xor as.rst;
end if;
end process;
------------------------------------------------------------------
din_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if as.rd = '1' then
DAT_O(data_width-1 downto 0) <= port_di;
end if;
end if;
end process;
------------------------------------------------------------------
data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if en = '1' and rdy = '1' then
we_reg <= WE_I;
data_reg <= DAT_I(data_width-1 downto 0);
end if;
end if;
end process;
------------------------------------------------------------------
addr_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if en = '1' and rdy = '1' then
addr_reg <= ADDR_I(addr_width-1 downto 0);
end if;
end if;
end process;
------------------------------------------------------------------
output_SRDY:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
rdyo <= '1';
elsif en = '1' then
rdyo <= rdy and not rdyo;
end if;
end if;
end process;
------------------------------------------------------------------
output_ACK:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= ack;
end if;
end if;
end process;
------------------------------------------------------------------
end Behavioral;
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.2 2010/03/13 11:06:43 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.async_types.all;
------------------------------------------------------------------
entity flash_port_wb is
Generic
(
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
async_timespec : async_timespec_t
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
port_bsyi : in std_logic;
port_bsyo : out std_logic;
port_a : out unsigned(addr_width-1 downto 0);
port_di : in unsigned(data_width-1 downto 0);
port_do : out unsigned(data_width-1 downto 0);
port_d_drv : out STD_LOGIC;
port_wr : out STD_LOGIC;
port_rd : out STD_LOGIC;
flash_cs : out std_logic;
flash_rst : out std_logic
);
end flash_port_wb;
architecture Behavioral of flash_port_wb is
type async_t is record
cs : std_logic;
wr : std_logic;
rd : std_logic;
rst : std_logic;
drive_d : std_logic;
end record;
type async_state_t is (start, reset, idle, go, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
signal s, sn : async_state_t;
signal as : async_t;
signal ack : std_logic;
signal cc_rst : std_logic;
signal cycle_cnt : natural range 0 to 31;
signal cycle_reload : natural range 0 to 31;
signal rdy : std_logic;
signal rdyo : std_logic;
signal en : std_logic;
signal we_reg : std_logic;
signal data_reg : unsigned(data_width-1 downto 0);
signal addr_reg : unsigned(addr_width-1 downto 0);
------------------------------------------------------------------
begin
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;
port_a <= addr_reg;
port_do <= data_reg;
port_d_drv <= as.drive_d;
port_wr <= (not async_timespec.pol_we) xor as.wr;
port_rd <= (not async_timespec.pol_oe) xor as.rd;
proc_cycle_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if cc_rst = '1' then
cycle_cnt <= cycle_reload;
elsif cycle_cnt /= 0 then
cycle_cnt <= cycle_cnt - 1;
end if;
end if;
end process;
------------------------------------------------------------------
proc_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
s <= start;
else
s <= sn;
end if;
end if;
end process;
proc_state:
process(s, cycle_cnt, en, we_reg, port_bsyi)
begin
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
as.wr <= '0';
as.rd <= '0';
as.drive_d <= '0';
ack <= '0';
rdy <= '0';
port_bsyo <= '1';
sn <= s;
case s is
when start =>
cc_rst <= '1';
sn <= reset;
when reset =>
as.rst <= '1';
if cycle_cnt = 0 then
sn <= idle;
end if;
when idle =>
port_bsyo <= '0';
rdy <= '1';
if en = '1' then
sn <= go;
end if;
when go =>
port_bsyo <= '0';
if port_bsyi = '0' then
as.cs <= '1';
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk)-1;
if we_reg = '0' then
sn <= leadin_rd;
else
sn <= leadin_wr;
end if;
end if;
when leadin_rd =>
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk)-1;
as.rd <= '1';
sn <= read;
end if;
when leadin_wr =>
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk)-1;
as.wr <= '1';
as.drive_d <= '1';
sn <= write;
end if;
when read =>
as.cs <= '1';
as.rd <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
-- as.rd <= '0';
sn <= leadout_rd;
ack <= '1';
end if;
when write =>
as.drive_d <= '1';
as.cs <= '1';
as.wr <= '1';
if cycle_cnt = 0 then
as.wr <= '0';
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
sn <= leadout_wr;
-- ack <= '1';
end if;
when leadout_rd =>
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
sn <= release;
as.cs <= '0';
end if;
when leadout_wr =>
as.cs <= '1';
as.drive_d <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
sn <= release;
as.cs <= '0';
end if;
when release =>
if cycle_cnt = 0 then
sn <= idle;
end if;
when others =>
sn <= idle;
end case;
end process;
------------------------------------------------------------------
output_ctrl:
process(CLK_I)
begin
if rising_edge(CLK_I) then
flash_cs <= (not async_timespec.pol_cs) xor as.cs;
flash_rst <= (not async_timespec.pol_rst) xor as.rst;
end if;
end process;
------------------------------------------------------------------
din_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if as.rd = '1' then
DAT_O(data_width-1 downto 0) <= port_di;
end if;
end if;
end process;
------------------------------------------------------------------
data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if en = '1' and rdy = '1' then
we_reg <= WE_I;
data_reg <= DAT_I(data_width-1 downto 0);
end if;
end if;
end process;
------------------------------------------------------------------
addr_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if en = '1' and rdy = '1' then
addr_reg <= ADDR_I(addr_width-1 downto 0);
end if;
end if;
end process;
------------------------------------------------------------------
output_SRDY:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
rdyo <= '1';
elsif en = '1' then
rdyo <= rdy and not rdyo;
end if;
end if;
end process;
------------------------------------------------------------------
output_ACK:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= ack;
end if;
end if;
end process;
------------------------------------------------------------------
end Behavioral;
lib/misc/lcd_port.vhd
+69 -69
View File
@@ -1,69 +1,69 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
------------------------------------------------------------------
entity lcd_port is
Port (
rst : in std_logic;
clk : in std_logic;
we : in std_logic;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
lcd_d : inout unsigned(3 downto 0);
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic
);
end lcd_port;
architecture Behavioral of lcd_port is
constant clcd_e : integer := 7;
constant clcd_rs : integer := 6;
constant clcd_rw : integer := 5;
type lcd_t is record
d : unsigned(3 downto 0);
e : std_logic;
rs : std_logic;
rw : std_logic;
end record;
------------------------------------------------------------------
begin
proc_lcd_port:
process(rst, clk)
variable vlcd : lcd_t;
begin
if (rst = '1') then
dout <= (others => '0');
vlcd.d := (others => '0');
vlcd.e := '0';
vlcd.rw := '1';
vlcd.rs := '0';
elsif rising_edge(clk) then
dout <= unsigned("0000" & lcd_d);
if we = '1' then
vlcd.d := din(3 downto 0);
vlcd.e := din(clcd_e);
vlcd.rs := din(clcd_rs);
vlcd.rw := din(clcd_rw);
end if;
end if;
if vlcd.rw = '0' then
lcd_d <= unsigned(vlcd.d);
else
lcd_d <= (others => 'Z');
end if;
lcd_e <= vlcd.e;
lcd_rs <= vlcd.rs;
lcd_rw <= vlcd.rw;
end process;
------------------------------------------------------------------
end Behavioral;
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
------------------------------------------------------------------
entity lcd_port is
Port (
rst : in std_logic;
clk : in std_logic;
we : in std_logic;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
lcd_d : inout unsigned(3 downto 0);
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic
);
end lcd_port;
architecture Behavioral of lcd_port is
constant clcd_e : integer := 7;
constant clcd_rs : integer := 6;
constant clcd_rw : integer := 5;
type lcd_t is record
d : unsigned(3 downto 0);
e : std_logic;
rs : std_logic;
rw : std_logic;
end record;
------------------------------------------------------------------
begin
proc_lcd_port:
process(rst, clk)
variable vlcd : lcd_t;
begin
if (rst = '1') then
dout <= (others => '0');
vlcd.d := (others => '0');
vlcd.e := '0';
vlcd.rw := '1';
vlcd.rs := '0';
elsif rising_edge(clk) then
dout <= unsigned("0000" & lcd_d);
if we = '1' then
vlcd.d := din(3 downto 0);
vlcd.e := din(clcd_e);
vlcd.rs := din(clcd_rs);
vlcd.rw := din(clcd_rw);
end if;
end if;
if vlcd.rw = '0' then
lcd_d <= unsigned(vlcd.d);
else
lcd_d <= (others => 'Z');
end if;
lcd_e <= vlcd.e;
lcd_rs <= vlcd.rs;
lcd_rw <= vlcd.rw;
end process;
------------------------------------------------------------------
end Behavioral;
lib/misc/oneshot.vhd
+223 -223
View File
@@ -1,223 +1,223 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:52:19 10/22/05
-- Design Name:
-- Module Name: oneshot - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
-- Component Template
--
-- COMPONENT oneshot
-- GENERIC (mode : integer);
-- PORT(
-- rst : IN std_logic;
-- clk : IN std_logic;
-- input : IN std_logic;
-- output : OUT std_logic
-- );
-- END COMPONENT;
--
-- Instantation Template
--
-- oneshot_int: oneshot
-- GENERIC MAP (
-- mode => 1)
-- PORT MAP(
-- rst => ,
-- clk => ,
-- input => ,
-- output =>
-- );
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity oneshot is
Generic ( mode : integer range 0 to 2 := 1);
Port ( rst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
end oneshot;
architecture Behavioral of oneshot is
type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st);
signal shot_cs : shot_state_t;
signal shot_ns : shot_state_t;
begin
mode_0:
if mode = 0 generate
begin
shot_clk: process(rst, clk, shot_ns, input)
begin
if (rst = '1') then
if (input = '1') then
shot_cs <= release_pos_st;
else
shot_cs <= release_neg_st;
end if;
else
if rising_edge(clk) then
shot_cs <= shot_ns;
end if;
end if;
end process;
shot_in: process(rst, clk, input, shot_cs)
begin
shot_ns <= shot_cs;
case shot_cs is
when release_pos_st =>
if (input = '0') then
shot_ns <= shot_neg_st;
end if;
when shot_neg_st =>
shot_ns <= release_neg_st;
when release_neg_st =>
if (input = '1') then
shot_ns <= release_pos_st;
end if;
when others => null;
end case;
end process;
shot_out: process(shot_cs)
begin
output <= '0';
case shot_cs is
when shot_pos_st =>
output <= '1';
when shot_neg_st =>
output <= '1';
when others => null;
end case;
end process;
end generate;
mode_1:
if mode = 1 generate
begin
shot_clk: process(rst, clk, shot_ns, input)
begin
if (rst = '1') then
if (input = '1') then
shot_cs <= release_pos_st;
else
shot_cs <= release_neg_st;
end if;
else
if rising_edge(clk) then
shot_cs <= shot_ns;
end if;
end if;
end process;
shot_in: process(rst, clk, input, shot_cs)
begin
shot_ns <= shot_cs;
case shot_cs is
when shot_pos_st =>
shot_ns <= release_pos_st;
when release_pos_st =>
if (input = '0') then
shot_ns <= release_neg_st;
end if;
when release_neg_st =>
if (input = '1') then
shot_ns <= shot_pos_st;
end if;
when others => null;
end case;
end process;
shot_out: process(shot_cs)
begin
output <= '0';
case shot_cs is
when shot_pos_st =>
output <= '1';
when shot_neg_st =>
output <= '1';
when others => null;
end case;
end process;
end generate;
mode_2:
if mode = 2 generate
begin
shot_clk: process(rst, clk, shot_ns, input)
begin
if (rst = '1') then
if (input = '1') then
shot_cs <= release_pos_st;
else
shot_cs <= release_neg_st;
end if;
else
if rising_edge(clk) then
shot_cs <= shot_ns;
end if;
end if;
end process;
shot_in: process(rst, clk, input, shot_cs)
begin
shot_ns <= shot_cs;
case shot_cs is
when shot_pos_st =>
shot_ns <= release_pos_st;
when release_pos_st =>
if (input = '0') then
shot_ns <= shot_neg_st;
end if;
when shot_neg_st =>
shot_ns <= release_neg_st;
when release_neg_st =>
if (input = '1') then
shot_ns <= shot_pos_st;
end if;
end case;
end process;
shot_out: process(shot_cs)
begin
output <= '0';
case shot_cs is
when shot_pos_st =>
output <= '1';
when shot_neg_st =>
output <= '1';
when others => null;
end case;
end process;
end generate;
end Behavioral;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:52:19 10/22/05
-- Design Name:
-- Module Name: oneshot - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
-- Component Template
--
-- COMPONENT oneshot
-- GENERIC (mode : integer);
-- PORT(
-- rst : IN std_logic;
-- clk : IN std_logic;
-- input : IN std_logic;
-- output : OUT std_logic
-- );
-- END COMPONENT;
--
-- Instantation Template
--
-- oneshot_int: oneshot
-- GENERIC MAP (
-- mode => 1)
-- PORT MAP(
-- rst => ,
-- clk => ,
-- input => ,
-- output =>
-- );
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity oneshot is
Generic ( mode : integer range 0 to 2 := 1);
Port ( rst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
end oneshot;
architecture Behavioral of oneshot is
type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st);
signal shot_cs : shot_state_t;
signal shot_ns : shot_state_t;
begin
mode_0:
if mode = 0 generate
begin
shot_clk: process(rst, clk, shot_ns, input)
begin
if (rst = '1') then
if (input = '1') then
shot_cs <= release_pos_st;
else
shot_cs <= release_neg_st;
end if;
else
if rising_edge(clk) then
shot_cs <= shot_ns;
end if;
end if;
end process;
shot_in: process(rst, clk, input, shot_cs)
begin
shot_ns <= shot_cs;
case shot_cs is
when release_pos_st =>
if (input = '0') then
shot_ns <= shot_neg_st;
end if;
when shot_neg_st =>
shot_ns <= release_neg_st;
when release_neg_st =>
if (input = '1') then
shot_ns <= release_pos_st;
end if;
when others => null;
end case;
end process;
shot_out: process(shot_cs)
begin
output <= '0';
case shot_cs is
when shot_pos_st =>
output <= '1';
when shot_neg_st =>
output <= '1';
when others => null;
end case;
end process;
end generate;
mode_1:
if mode = 1 generate
begin
shot_clk: process(rst, clk, shot_ns, input)
begin
if (rst = '1') then
if (input = '1') then
shot_cs <= release_pos_st;
else
shot_cs <= release_neg_st;
end if;
else
if rising_edge(clk) then
shot_cs <= shot_ns;
end if;
end if;
end process;
shot_in: process(rst, clk, input, shot_cs)
begin
shot_ns <= shot_cs;
case shot_cs is
when shot_pos_st =>
shot_ns <= release_pos_st;
when release_pos_st =>
if (input = '0') then
shot_ns <= release_neg_st;
end if;
when release_neg_st =>
if (input = '1') then
shot_ns <= shot_pos_st;
end if;
when others => null;
end case;
end process;
shot_out: process(shot_cs)
begin
output <= '0';
case shot_cs is
when shot_pos_st =>
output <= '1';
when shot_neg_st =>
output <= '1';
when others => null;
end case;
end process;
end generate;
mode_2:
if mode = 2 generate
begin
shot_clk: process(rst, clk, shot_ns, input)
begin
if (rst = '1') then
if (input = '1') then
shot_cs <= release_pos_st;
else
shot_cs <= release_neg_st;
end if;
else
if rising_edge(clk) then
shot_cs <= shot_ns;
end if;
end if;
end process;
shot_in: process(rst, clk, input, shot_cs)
begin
shot_ns <= shot_cs;
case shot_cs is
when shot_pos_st =>
shot_ns <= release_pos_st;
when release_pos_st =>
if (input = '0') then
shot_ns <= shot_neg_st;
end if;
when shot_neg_st =>
shot_ns <= release_neg_st;
when release_neg_st =>
if (input = '1') then
shot_ns <= shot_pos_st;
end if;
end case;
end process;
shot_out: process(shot_cs)
begin
output <= '0';
case shot_cs is
when shot_pos_st =>
output <= '1';
when shot_neg_st =>
output <= '1';
when others => null;
end case;
end process;
end generate;
end Behavioral;
lib/misc/pkg_template.vhd
+18 -18
View File
@@ -1,18 +1,18 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
package template_pkg is
-- Constants
-- Types
-- Functions
end template_pkg;
package body template_pkg is
end template_pkg;
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
package template_pkg is
-- Constants
-- Types
-- Functions
end template_pkg;
package body template_pkg is
end template_pkg;
lib/misc/singleshot.vhd
+155 -155
View File
@@ -1,155 +1,155 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:52:19 10/22/05
-- Design Name:
-- Module Name: singleshot - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
-- Component Template
--
-- COMPONENT singleshot
-- GENERIC (mode : integer);
-- PORT(
-- rst : IN std_logic;
-- clk : IN std_logic;
-- input : IN std_logic;
-- output : OUT std_logic
-- );
-- END COMPONENT;
--
-- Instantation Template
--
-- singleshot_int: oneshot
-- GENERIC MAP (
-- mode => 1)
-- PORT MAP(
-- rst => ,
-- clk => ,
-- input => ,
-- output =>
-- );
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity singleshot is
Generic ( mode : integer range 0 to 2 := 1);
Port ( rst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
end singleshot;
architecture Behavioral of singleshot is
type s_t is (idle, shot_in, active, shot_out);
signal s, sn : s_t;
begin
process (rst, clk, sn)
begin
if rising_edge(clk) then
if rst = '1' then
s <= idle;
else
s <= sn;
end if;
end if;
end process;
mode_1:
if mode = 1 generate
begin
process (input, s)
begin
output <= '0';
sn <= s;
case s is
when idle =>
if input = '1' then
sn <= shot_in;
end if;
when shot_in =>
output <= '1';
sn <= active;
when active =>
if input = '0' then
sn <= shot_out;
end if;
when shot_out =>
sn <= idle;
when others => null;
end case;
end process;
end generate;
mode_0:
if mode = 0 generate
begin
process (input, s)
begin
output <= '0';
sn <= s;
case s is
when idle =>
if input = '1' then
sn <= shot_in;
end if;
when shot_in =>
sn <= active;
when active =>
if input = '0' then
sn <= shot_out;
end if;
when shot_out =>
output <= '1';
sn <= idle;
when others => null;
end case;
end process;
end generate;
mode_2:
if mode = 2 generate
begin
process (input, s)
begin
output <= '0';
sn <= s;
case s is
when idle =>
if input = '1' then
sn <= shot_in;
end if;
when shot_in =>
output <= '1';
sn <= active;
when active =>
if input = '0' then
sn <= shot_out;
end if;
when shot_out =>
output <= '1';
sn <= idle;
when others => null;
end case;
end process;
end generate;
end Behavioral;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:52:19 10/22/05
-- Design Name:
-- Module Name: singleshot - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
-- Component Template
--
-- COMPONENT singleshot
-- GENERIC (mode : integer);
-- PORT(
-- rst : IN std_logic;
-- clk : IN std_logic;
-- input : IN std_logic;
-- output : OUT std_logic
-- );
-- END COMPONENT;
--
-- Instantation Template
--
-- singleshot_int: oneshot
-- GENERIC MAP (
-- mode => 1)
-- PORT MAP(
-- rst => ,
-- clk => ,
-- input => ,
-- output =>
-- );
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity singleshot is
Generic ( mode : integer range 0 to 2 := 1);
Port ( rst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
end singleshot;
architecture Behavioral of singleshot is
type s_t is (idle, shot_in, active, shot_out);
signal s, sn : s_t;
begin
process (rst, clk, sn)
begin
if rising_edge(clk) then
if rst = '1' then
s <= idle;
else
s <= sn;
end if;
end if;
end process;
mode_1:
if mode = 1 generate
begin
process (input, s)
begin
output <= '0';
sn <= s;
case s is
when idle =>
if input = '1' then
sn <= shot_in;
end if;
when shot_in =>
output <= '1';
sn <= active;
when active =>
if input = '0' then
sn <= shot_out;
end if;
when shot_out =>
sn <= idle;
when others => null;
end case;
end process;
end generate;
mode_0:
if mode = 0 generate
begin
process (input, s)
begin
output <= '0';
sn <= s;
case s is
when idle =>
if input = '1' then
sn <= shot_in;
end if;
when shot_in =>
sn <= active;
when active =>
if input = '0' then
sn <= shot_out;
end if;
when shot_out =>
output <= '1';
sn <= idle;
when others => null;
end case;
end process;
end generate;
mode_2:
if mode = 2 generate
begin
process (input, s)
begin
output <= '0';
sn <= s;
case s is
when idle =>
if input = '1' then
sn <= shot_in;
end if;
when shot_in =>
output <= '1';
sn <= active;
when active =>
if input = '0' then
sn <= shot_out;
end if;
when shot_out =>
output <= '1';
sn <= idle;
when others => null;
end case;
end process;
end generate;
end Behavioral;
lib/misc/tb_template.vhd
+63 -63
View File
@@ -1,63 +1,63 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.MATH_REAL.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE STD.TEXTIO.ALL;
-- LIBRARY WORK;
-- USE.YOURLIB.WHATELSE
ENTITY tb_template IS
END tb_template;
ARCHITECTURE behavior OF tb_template IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT your_comp
GENERIC
(
);
PORT
(
);
END COMPONENT;
--Constants
constant PERIOD : time := 10 ns;
--Inputs
signal clk : STD_LOGIC := '0';
--Outputs
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: your_comp
GENERIC MAP
(
)
PORT MAP
(
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
assert false report "Test finished" severity error;
wait;
END PROCESS;
END tb_template;
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.MATH_REAL.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE STD.TEXTIO.ALL;
-- LIBRARY WORK;
-- USE.YOURLIB.WHATELSE
ENTITY tb_template IS
END tb_template;
ARCHITECTURE behavior OF tb_template IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT your_comp
GENERIC
(
);
PORT
(
);
END COMPONENT;
--Constants
constant PERIOD : time := 10 ns;
--Inputs
signal clk : STD_LOGIC := '0';
--Outputs
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: your_comp
GENERIC MAP
(
)
PORT MAP
(
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
assert false report "Test finished" severity error;
wait;
END PROCESS;
END tb_template;
lib/misc/utils_pkg.vhd
+196 -196
View File
@@ -1,196 +1,196 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.6 2010-03-22 07:25:40 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
package utils_pkg is
-- Constants
-- Functions
function MIN (X, Y: INTEGER) return INTEGER;
function MAX (X, Y: INTEGER) return INTEGER;
function NextPowerOfTwo(x : real) return real;
function NextExpBaseTwo(x : real) return real;
function NextPowerOfTwo(x : natural) return natural;
function NextExpBaseTwo(x : natural) return natural;
function GCD(a, b : natural) return natural;
function LCM(a, b : natural) return natural;
function UTILS_PERIOD_NS(f_in_MHz : real) return real;
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural;
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural;
function f_correct(f : real) return natural;
end utils_pkg;
package body utils_pkg is
-------------------------------------------------------------
function MIN (X, Y: INTEGER) return INTEGER is
variable res : integer := X;
begin
if Y < X then
res := Y;
end if;
return res;
end MIN;
-------------------------------------------------------------
function MAX (X, Y: INTEGER) return INTEGER is
variable res : integer := X;
begin
if Y > X then
res := Y;
end if;
return res;
end MAX;
-------------------------------------------------------------
function NextExpBaseTwo(x : real) return real is
begin
return ceil(log2(x));
end NextExpBaseTwo;
-------------------------------------------------------------
function NextPowerOfTwo(x : real) return real is
begin
return 2.0**NextExpBaseTwo(x);
end NextPowerOfTwo;
-------------------------------------------------------------
function NextExpBaseTwo(x : natural) return natural is
begin
return natural(NextExpBaseTwo(real(x)));
end NextExpBaseTwo;
-------------------------------------------------------------
function NextPowerOfTwo(x : natural) return natural is
begin
return 2**NextExpBaseTwo(x);
end NextPowerOfTwo;
-------------------------------------------------------------
function GCD(a, b : natural) return natural is
variable aa : natural;
variable bb : natural;
begin
aa := a;
bb := b;
while bb /= 0 loop
if aa > bb then
aa := aa - bb;
else
bb := bb - aa;
end if;
end loop;
return aa;
end GCD;
-------------------------------------------------------------
function LCM(a, b : natural) return natural is
begin
return (a * b)/GCD(a, b);
end LCM;
-------------------------------------------------------------
function UTILS_PERIOD_NS(f_in_MHz : real) return real is
begin
return 1.0E3/f_in_MHz;
end UTILS_PERIOD_NS;
-------------------------------------------------------------
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural is
variable f_in : natural;
variable f_out : natural;
variable C : natural;
variable M : natural;
variable D : natural;
begin
C := f_correct(f_out_MHz);
if C < 2 then
C := f_correct(f_in_MHz);
end if;
f_out := natural(ceil(real(C)*f_out_MHz));
f_in := natural(ceil(real(C)*f_in_MHz));
M := LCM(f_in, f_out)/f_in;
D := f_in/GCD(f_in, f_out);
assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
if M = 1 then
M := 2;
end if;
return M;
end UTILS_FREQ_M;
-------------------------------------------------------------
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural is
variable f_in : natural;
variable f_out : natural;
variable C : natural;
variable M : natural;
variable D : natural;
begin
C := f_correct(f_out_MHz);
if C < 2 then
C := f_correct(f_in_MHz);
end if;
f_out := natural(ceil(real(C)*f_out_MHz));
f_in := natural(ceil(real(C)*f_in_MHz));
M := LCM(f_in, f_out)/f_in;
D := f_in/GCD(f_in, f_out);
assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
if M = 1 then
D := 2*D;
end if;
return D;
end UTILS_FREQ_D;
-------------------------------------------------------------
function f_correct(f : real) return natural is
constant MAX_ITER : positive := 100;
constant MAX_ERR : real := 0.01;
variable fpart : real;
variable err : real;
begin
for i in 1 to MAX_ITER loop
fpart := real(i)*f - ceil(real(i)*f);
err := abs(fpart);
if err < max_err then
return i;
end if;
end loop;
end f_correct;
-------------------------------------------------------------
end utils_pkg;
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.6 2010/03/22 07:25:40 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
package utils_pkg is
-- Constants
-- Functions
function MIN (X, Y: INTEGER) return INTEGER;
function MAX (X, Y: INTEGER) return INTEGER;
function NextPowerOfTwo(x : real) return real;
function NextExpBaseTwo(x : real) return real;
function NextPowerOfTwo(x : natural) return natural;
function NextExpBaseTwo(x : natural) return natural;
function GCD(a, b : natural) return natural;
function LCM(a, b : natural) return natural;
function UTILS_PERIOD_NS(f_in_MHz : real) return real;
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural;
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural;
function f_correct(f : real) return natural;
end utils_pkg;
package body utils_pkg is
-------------------------------------------------------------
function MIN (X, Y: INTEGER) return INTEGER is
variable res : integer := X;
begin
if Y < X then
res := Y;
end if;
return res;
end MIN;
-------------------------------------------------------------
function MAX (X, Y: INTEGER) return INTEGER is
variable res : integer := X;
begin
if Y > X then
res := Y;
end if;
return res;
end MAX;
-------------------------------------------------------------
function NextExpBaseTwo(x : real) return real is
begin
return ceil(log2(x));
end NextExpBaseTwo;
-------------------------------------------------------------
function NextPowerOfTwo(x : real) return real is
begin
return 2.0**NextExpBaseTwo(x);
end NextPowerOfTwo;
-------------------------------------------------------------
function NextExpBaseTwo(x : natural) return natural is
begin
return natural(NextExpBaseTwo(real(x)));
end NextExpBaseTwo;
-------------------------------------------------------------
function NextPowerOfTwo(x : natural) return natural is
begin
return 2**NextExpBaseTwo(x);
end NextPowerOfTwo;
-------------------------------------------------------------
function GCD(a, b : natural) return natural is
variable aa : natural;
variable bb : natural;
begin
aa := a;
bb := b;
while bb /= 0 loop
if aa > bb then
aa := aa - bb;
else
bb := bb - aa;
end if;
end loop;
return aa;
end GCD;
-------------------------------------------------------------
function LCM(a, b : natural) return natural is
begin
return (a * b)/GCD(a, b);
end LCM;
-------------------------------------------------------------
function UTILS_PERIOD_NS(f_in_MHz : real) return real is
begin
return 1.0E3/f_in_MHz;
end UTILS_PERIOD_NS;
-------------------------------------------------------------
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural is
variable f_in : natural;
variable f_out : natural;
variable C : natural;
variable M : natural;
variable D : natural;
begin
C := f_correct(f_out_MHz);
if C < 2 then
C := f_correct(f_in_MHz);
end if;
f_out := natural(ceil(real(C)*f_out_MHz));
f_in := natural(ceil(real(C)*f_in_MHz));
M := LCM(f_in, f_out)/f_in;
D := f_in/GCD(f_in, f_out);
assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
if M = 1 then
M := 2;
end if;
return M;
end UTILS_FREQ_M;
-------------------------------------------------------------
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural is
variable f_in : natural;
variable f_out : natural;
variable C : natural;
variable M : natural;
variable D : natural;
begin
C := f_correct(f_out_MHz);
if C < 2 then
C := f_correct(f_in_MHz);
end if;
f_out := natural(ceil(real(C)*f_out_MHz));
f_in := natural(ceil(real(C)*f_in_MHz));
M := LCM(f_in, f_out)/f_in;
D := f_in/GCD(f_in, f_out);
assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
if M = 1 then
D := 2*D;
end if;
return D;
end UTILS_FREQ_D;
-------------------------------------------------------------
function f_correct(f : real) return natural is
constant MAX_ITER : positive := 100;
constant MAX_ERR : real := 0.01;
variable fpart : real;
variable err : real;
begin
for i in 1 to MAX_ITER loop
fpart := real(i)*f - ceil(real(i)*f);
err := abs(fpart);
if err < max_err then
return i;
end if;
end loop;
end f_correct;
-------------------------------------------------------------
end utils_pkg;