- commit local changes after CVS2SVN
git-svn-id: http://moon:8086/svn/vhdl/trunk@1036 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -1,59 +1,74 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
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||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
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||||
add wave -noupdate -divider J-BUS
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/ack_i
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/srdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/mdat_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/addr_o
|
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add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/sel_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/we_o
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o
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||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/stb_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/mrdy_o
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add wave -noupdate -divider Busmaster
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||||
add wave -noupdate -format Logic /tb_busmaster_async/clk_o
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
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||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
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||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_finished
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||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_en
|
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_rdy
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||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_we
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/inst_uut/cmd_in
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add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/din
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add wave -noupdate -format Logic /tb_busmaster_async/din_rdy
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add wave -noupdate -format Logic /tb_busmaster_async/din_we
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add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/dout
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||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_vld
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_re
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cycle_busy
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_en
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_read_en
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add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/read_cnt
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o
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add wave -noupdate -divider RAM
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
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add wave -noupdate -format Literal /tb_busmaster_async/state
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add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/read_reg
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/ram64
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TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {31500000 ps} 0}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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update
|
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WaveRestoreZoom {0 ps} {42 us}
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||||
onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
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add wave -noupdate -divider J-BUS
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/ack_i
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/srdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/mdat_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/mdat_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/addr_o
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add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/sel_o
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/we_o
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/stb_o
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/mrdy_o
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add wave -noupdate -divider Busmaster
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add wave -noupdate -format Logic /tb_busmaster_async/clk_o
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
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add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/read_cnt
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write
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add wave -noupdate -format Literal -expand /tb_busmaster_async/inst_uut/debug
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_finished
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_en
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_rdy
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_we
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/inst_uut/cmd_in
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_fifo_empty
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_fifo_re
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/read_fifo_we
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add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/din
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add wave -noupdate -format Logic /tb_busmaster_async/din_rdy
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add wave -noupdate -format Logic /tb_busmaster_async/din_we
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add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/dout
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_vld
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_re
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cycle_busy
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cycle_active
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_en
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_read_en
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_fifo_we
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_fifo_full
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/read_fifo_re
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/read_fifo_full
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/read_fifo_empty
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write_fifo_re
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write_fifo_we
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write_fifo_full
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write_fifo_empty
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add wave -noupdate -divider RAM
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
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add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
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add wave -noupdate -format Literal /tb_busmaster_async/state
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add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/read_reg
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/ram64
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TreeUpdate [SetDefaultTree]
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||||
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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update
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WaveRestoreZoom {0 ps} {8639241 ps}
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+277
-277
@@ -1,277 +1,277 @@
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-----------------------------------------------------------------------
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-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.2 2013-08-04 17:58:37 jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.utils_pkg.all;
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use work.busmaster_types.all;
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------------------------------------------------------------------
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entity busmaster_async is
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Generic
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(
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DATA_WIDTH : natural := 32;
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FIFO_DEPTH : natural := 4
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);
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Port
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(
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clk : in std_logic;
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rst : in std_logic;
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cmd_cycle_finished : out std_logic;
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cmd_cycle_en : in std_logic;
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cmd_rdy : out std_logic;
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cmd_we : in std_logic;
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cmd_in : in bm_cmd_t;
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din : in unsigned(DATA_WIDTH-1 downto 0);
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din_rdy : out std_logic;
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din_we : in std_logic;
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dout : out unsigned(DATA_WIDTH-1 downto 0);
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dout_vld : out std_logic;
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dout_re : in std_logic;
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-- J-BUS signals
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RST_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC;
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ACK_I : in std_logic;
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SRDY_I : in std_logic;
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MDAT_I : in unsigned(DATA_WIDTH-1 downto 0);
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MDAT_O : out unsigned(DATA_WIDTH-1 downto 0);
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ADDR_O : out unsigned(31 downto 0);
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SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0);
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WE_O : out std_logic;
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CYC_O : out std_logic;
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STB_O : out std_logic;
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MRDY_O : out std_logic
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);
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end busmaster_async;
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architecture Behavioral of busmaster_async is
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-- Bus Command FIFO
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signal cmd_fifo_din : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
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signal cmd_fifo_dout : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
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signal cmd_fifo_re : std_logic;
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signal cmd_fifo_we : std_logic;
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signal cmd_fifo_full : std_logic;
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signal cmd_fifo_empty : std_logic;
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-- Bus Read FIFO
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signal read_fifo_re : std_logic;
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||||
signal read_fifo_we : std_logic;
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||||
signal read_fifo_full : std_logic;
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||||
signal read_fifo_empty : std_logic;
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signal write_fifo_re : std_logic;
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signal write_fifo_we : std_logic;
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||||
signal write_fifo_full : std_logic;
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signal write_fifo_empty : std_logic;
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signal cycle_busy : std_logic;
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signal cmd_en : std_logic;
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signal cmd_read_en : std_logic;
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signal read_cnt : integer range 0 to 65535;
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signal write : std_logic;
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signal jbus_cycle_busy : std_logic;
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type jbus_state_t is (init, ready, start, wait_finish, finish1, finish2, finish3);
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signal jbus_state : jbus_state_t;
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signal jbus_state_next : jbus_state_t;
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begin
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cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full;
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cmd_read_en <= cmd_en and not cmd_in.rw;
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write <= cmd_fifo_dout(32+DATA_WIDTH/8);
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dout_vld <= not read_fifo_empty;
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MRDY_O <= not read_fifo_full;
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read_fifo_we <= ACK_I and jbus_cycle_busy;
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read_fifo_re <= dout_re;
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ADDR_O <= cmd_fifo_dout(31 downto 0);
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SEL_O <= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32);
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WE_O <= write;
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cmd_fifo_din <= cmd_in.rw & cmd_in.sel & cmd_in.addr;
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cmd_rdy <= not cmd_fifo_full;
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cmd_fifo_we <= cmd_en;
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cmd_fifo_re <= SRDY_I and jbus_cycle_busy;
|
||||
|
||||
din_rdy <= not write_fifo_full;
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||||
write_fifo_we <= din_we;
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||||
write_fifo_re <= SRDY_I and jbus_cycle_busy and write and not cmd_fifo_empty;
|
||||
|
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CYC_O <= jbus_cycle_busy;
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||||
STB_O <= not cmd_fifo_empty;
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-- J-Bus domain
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proc_JBUS_to_local_cmd_cycle_finished:
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process(clk)
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begin
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||||
if rising_edge(clk) then
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cmd_cycle_finished <= not jbus_cycle_busy;
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||||
end if;
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end process;
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||||
|
||||
proc_JBUS_cycle:
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process(CLK_I)
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||||
begin
|
||||
if rising_edge(CLK_I) then
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||||
jbus_cycle_busy <= cycle_busy;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_bus_read_counter:
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process(clk)
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begin
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if rising_edge(clk) then
|
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if rst = '1' then
|
||||
read_cnt <= 0;
|
||||
elsif cmd_read_en = '1' and read_fifo_empty = '1' then
|
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read_cnt <= read_cnt + 1;
|
||||
elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then
|
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read_cnt <= read_cnt - 1;
|
||||
end if;
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end if;
|
||||
end process;
|
||||
|
||||
jbus_state_fsm_next:
|
||||
process(clk)
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begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
jbus_state <= init;
|
||||
else
|
||||
jbus_state <= jbus_state_next;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
jbus_state_fsm:
|
||||
process(jbus_state, cmd_we, cmd_fifo_empty, write_fifo_empty, read_cnt)
|
||||
begin
|
||||
|
||||
cycle_busy <= '0';
|
||||
jbus_state_next <= jbus_state;
|
||||
|
||||
case jbus_state is
|
||||
|
||||
when init =>
|
||||
jbus_state_next <= ready;
|
||||
|
||||
when ready =>
|
||||
if cmd_we = '1' or cmd_fifo_empty = '0' then
|
||||
jbus_state_next <= start;
|
||||
end if;
|
||||
|
||||
when start =>
|
||||
cycle_busy <= '1';
|
||||
if cmd_fifo_empty = '0' then
|
||||
jbus_state_next <= wait_finish;
|
||||
end if;
|
||||
|
||||
when wait_finish =>
|
||||
cycle_busy <= '1';
|
||||
if read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
|
||||
jbus_state_next <= finish1;
|
||||
end if;
|
||||
|
||||
-- Quick and dirty hack
|
||||
-- avoid buscycle to finish even if data available,
|
||||
-- caused by latency of async-FIFO empty flag
|
||||
when finish1 =>
|
||||
jbus_state_next <= finish2;
|
||||
|
||||
when finish2 =>
|
||||
jbus_state_next <= finish3;
|
||||
|
||||
when finish3 =>
|
||||
jbus_state_next <= ready;
|
||||
if cmd_fifo_empty = '0' then
|
||||
jbus_state_next <= wait_finish;
|
||||
end if;
|
||||
-- Quick and dirty hack
|
||||
|
||||
when others =>
|
||||
jbus_state_next <= ready;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Bus READ FIFO
|
||||
inst_BM_READ_FIFO: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_r => clk,
|
||||
clk_w => CLK_I,
|
||||
we => read_fifo_we,
|
||||
re => read_fifo_re,
|
||||
fifo_full => read_fifo_full,
|
||||
fifo_empty => read_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_r => dout,
|
||||
data_w => MDAT_I
|
||||
);
|
||||
|
||||
-- Bus WRITE FIFO
|
||||
inst_BM_WRITE_FIFO: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_r => CLK_I,
|
||||
clk_w => clk,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_r => MDAT_O,
|
||||
data_w => din
|
||||
);
|
||||
|
||||
-- Bus command FIFO
|
||||
inst_BM_CMD_FIFO: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => cmd_fifo_din'length,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_r => CLK_I,
|
||||
clk_w => clk,
|
||||
we => cmd_fifo_we,
|
||||
re => cmd_fifo_re,
|
||||
fifo_full => cmd_fifo_full,
|
||||
fifo_empty => cmd_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_r => cmd_fifo_dout,
|
||||
data_w => cmd_fifo_din
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.2 2013/08/04 17:58:37 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity busmaster_async is
|
||||
Generic
|
||||
(
|
||||
DATA_WIDTH : natural := 32;
|
||||
FIFO_DEPTH : natural := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
cmd_cycle_finished : out std_logic;
|
||||
cmd_cycle_en : in std_logic;
|
||||
cmd_rdy : out std_logic;
|
||||
cmd_we : in std_logic;
|
||||
|
||||
cmd_in : in bm_cmd_t;
|
||||
|
||||
din : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
din_rdy : out std_logic;
|
||||
din_we : in std_logic;
|
||||
|
||||
dout : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
dout_vld : out std_logic;
|
||||
dout_re : in std_logic;
|
||||
|
||||
-- J-BUS signals
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in std_logic;
|
||||
SRDY_I : in std_logic;
|
||||
MDAT_I : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
MDAT_O : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0);
|
||||
WE_O : out std_logic;
|
||||
CYC_O : out std_logic;
|
||||
STB_O : out std_logic;
|
||||
MRDY_O : out std_logic
|
||||
);
|
||||
end busmaster_async;
|
||||
|
||||
architecture Behavioral of busmaster_async is
|
||||
|
||||
-- Bus Command FIFO
|
||||
signal cmd_fifo_din : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_dout : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_re : std_logic;
|
||||
signal cmd_fifo_we : std_logic;
|
||||
signal cmd_fifo_full : std_logic;
|
||||
signal cmd_fifo_empty : std_logic;
|
||||
|
||||
-- Bus Read FIFO
|
||||
signal read_fifo_re : std_logic;
|
||||
signal read_fifo_we : std_logic;
|
||||
signal read_fifo_full : std_logic;
|
||||
signal read_fifo_empty : std_logic;
|
||||
signal write_fifo_re : std_logic;
|
||||
signal write_fifo_we : std_logic;
|
||||
signal write_fifo_full : std_logic;
|
||||
signal write_fifo_empty : std_logic;
|
||||
signal cycle_busy : std_logic;
|
||||
signal cmd_en : std_logic;
|
||||
signal cmd_read_en : std_logic;
|
||||
signal read_cnt : integer range 0 to 65535;
|
||||
signal write : std_logic;
|
||||
|
||||
signal jbus_cycle_busy : std_logic;
|
||||
|
||||
type jbus_state_t is (init, ready, start, wait_finish, finish1, finish2, finish3);
|
||||
signal jbus_state : jbus_state_t;
|
||||
signal jbus_state_next : jbus_state_t;
|
||||
|
||||
begin
|
||||
|
||||
cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full;
|
||||
cmd_read_en <= cmd_en and not cmd_in.rw;
|
||||
write <= cmd_fifo_dout(32+DATA_WIDTH/8);
|
||||
|
||||
dout_vld <= not read_fifo_empty;
|
||||
MRDY_O <= not read_fifo_full;
|
||||
read_fifo_we <= ACK_I and jbus_cycle_busy;
|
||||
read_fifo_re <= dout_re;
|
||||
ADDR_O <= cmd_fifo_dout(31 downto 0);
|
||||
SEL_O <= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32);
|
||||
WE_O <= write;
|
||||
|
||||
cmd_fifo_din <= cmd_in.rw & cmd_in.sel & cmd_in.addr;
|
||||
|
||||
cmd_rdy <= not cmd_fifo_full;
|
||||
|
||||
cmd_fifo_we <= cmd_en;
|
||||
cmd_fifo_re <= SRDY_I and jbus_cycle_busy;
|
||||
|
||||
din_rdy <= not write_fifo_full;
|
||||
write_fifo_we <= din_we;
|
||||
write_fifo_re <= SRDY_I and jbus_cycle_busy and write and not cmd_fifo_empty;
|
||||
|
||||
CYC_O <= jbus_cycle_busy;
|
||||
STB_O <= not cmd_fifo_empty;
|
||||
|
||||
|
||||
-- J-Bus domain
|
||||
proc_JBUS_to_local_cmd_cycle_finished:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
cmd_cycle_finished <= not jbus_cycle_busy;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_JBUS_cycle:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
jbus_cycle_busy <= cycle_busy;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_bus_read_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
read_cnt <= 0;
|
||||
elsif cmd_read_en = '1' and read_fifo_empty = '1' then
|
||||
read_cnt <= read_cnt + 1;
|
||||
elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then
|
||||
read_cnt <= read_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
jbus_state_fsm_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
jbus_state <= init;
|
||||
else
|
||||
jbus_state <= jbus_state_next;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
jbus_state_fsm:
|
||||
process(jbus_state, cmd_we, cmd_fifo_empty, write_fifo_empty, read_cnt)
|
||||
begin
|
||||
|
||||
cycle_busy <= '0';
|
||||
jbus_state_next <= jbus_state;
|
||||
|
||||
case jbus_state is
|
||||
|
||||
when init =>
|
||||
jbus_state_next <= ready;
|
||||
|
||||
when ready =>
|
||||
if cmd_we = '1' or cmd_fifo_empty = '0' then
|
||||
jbus_state_next <= start;
|
||||
end if;
|
||||
|
||||
when start =>
|
||||
cycle_busy <= '1';
|
||||
if cmd_fifo_empty = '0' then
|
||||
jbus_state_next <= wait_finish;
|
||||
end if;
|
||||
|
||||
when wait_finish =>
|
||||
cycle_busy <= '1';
|
||||
if read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
|
||||
jbus_state_next <= finish1;
|
||||
end if;
|
||||
|
||||
-- Quick and dirty hack
|
||||
-- avoid buscycle to finish even if data available,
|
||||
-- caused by latency of async-FIFO empty flag
|
||||
when finish1 =>
|
||||
jbus_state_next <= finish2;
|
||||
|
||||
when finish2 =>
|
||||
jbus_state_next <= finish3;
|
||||
|
||||
when finish3 =>
|
||||
jbus_state_next <= ready;
|
||||
if cmd_fifo_empty = '0' then
|
||||
jbus_state_next <= wait_finish;
|
||||
end if;
|
||||
-- Quick and dirty hack
|
||||
|
||||
when others =>
|
||||
jbus_state_next <= ready;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Bus READ FIFO
|
||||
inst_BM_READ_FIFO: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_r => clk,
|
||||
clk_w => CLK_I,
|
||||
we => read_fifo_we,
|
||||
re => read_fifo_re,
|
||||
fifo_full => read_fifo_full,
|
||||
fifo_empty => read_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_r => dout,
|
||||
data_w => MDAT_I
|
||||
);
|
||||
|
||||
-- Bus WRITE FIFO
|
||||
inst_BM_WRITE_FIFO: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_r => CLK_I,
|
||||
clk_w => clk,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_r => MDAT_O,
|
||||
data_w => din
|
||||
);
|
||||
|
||||
-- Bus command FIFO
|
||||
inst_BM_CMD_FIFO: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => cmd_fifo_din'length,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_r => CLK_I,
|
||||
clk_w => clk,
|
||||
we => cmd_fifo_we,
|
||||
re => cmd_fifo_re,
|
||||
fifo_full => cmd_fifo_full,
|
||||
fifo_empty => cmd_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_r => cmd_fifo_dout,
|
||||
data_w => cmd_fifo_din
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
+216
-216
@@ -1,216 +1,216 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.6 2013-08-03 19:31:19 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity busmaster_sync is
|
||||
Generic
|
||||
(
|
||||
DATA_WIDTH : natural := 32;
|
||||
FIFO_DEPTH : natural := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
cmd_cycle_finished : out std_logic;
|
||||
cmd_cycle_en : in std_logic;
|
||||
cmd_rdy : out std_logic;
|
||||
cmd_we : in std_logic;
|
||||
|
||||
cmd_in : in bm_cmd_t;
|
||||
|
||||
din : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
din_rdy : out std_logic;
|
||||
din_we : in std_logic;
|
||||
|
||||
dout : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
dout_vld : out std_logic;
|
||||
dout_re : in std_logic;
|
||||
|
||||
-- J-BUS signals
|
||||
ACK_I : in std_logic;
|
||||
SRDY_I : in std_logic;
|
||||
MDAT_I : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
MDAT_O : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0);
|
||||
WE_O : out std_logic;
|
||||
CYC_O : out std_logic;
|
||||
STB_O : out std_logic;
|
||||
MRDY_O : out std_logic
|
||||
);
|
||||
end busmaster_sync;
|
||||
|
||||
architecture Behavioral of busmaster_sync is
|
||||
|
||||
-- Bus Command FIFO
|
||||
signal cmd_fifo_din : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_dout : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_re : std_logic;
|
||||
signal cmd_fifo_we : std_logic;
|
||||
signal cmd_fifo_full : std_logic;
|
||||
signal cmd_fifo_empty : std_logic;
|
||||
|
||||
-- Bus Read FIFO
|
||||
signal read_fifo_re : std_logic;
|
||||
signal read_fifo_we : std_logic;
|
||||
signal read_fifo_full : std_logic;
|
||||
signal read_fifo_empty : std_logic;
|
||||
signal write_fifo_re : std_logic;
|
||||
signal write_fifo_we : std_logic;
|
||||
signal write_fifo_full : std_logic;
|
||||
signal write_fifo_empty : std_logic;
|
||||
signal cycle_busy : std_logic;
|
||||
signal cmd_en : std_logic;
|
||||
signal cmd_read_en : std_logic;
|
||||
signal read_cnt : integer range 0 to 65535;
|
||||
signal write : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full;
|
||||
cmd_read_en <= cmd_en and not cmd_in.rw;
|
||||
write <= cmd_fifo_dout(32+DATA_WIDTH/8);
|
||||
|
||||
dout_vld <= not read_fifo_empty;
|
||||
MRDY_O <= not read_fifo_full;
|
||||
read_fifo_we <= ACK_I and cycle_busy;
|
||||
read_fifo_re <= dout_re;
|
||||
ADDR_O <= cmd_fifo_dout(31 downto 0);
|
||||
SEL_O <= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32);
|
||||
WE_O <= write;
|
||||
|
||||
cmd_fifo_din <= cmd_in.rw & cmd_in.sel & cmd_in.addr;
|
||||
|
||||
cmd_rdy <= not cmd_fifo_full;
|
||||
|
||||
cmd_fifo_we <= cmd_en;
|
||||
cmd_fifo_re <= SRDY_I and cycle_busy;
|
||||
|
||||
din_rdy <= not write_fifo_full;
|
||||
write_fifo_we <= din_we;
|
||||
write_fifo_re <= SRDY_I and cycle_busy and write and not cmd_fifo_empty;
|
||||
|
||||
STB_O <= not cmd_fifo_empty;
|
||||
CYC_O <= cycle_busy;
|
||||
cmd_cycle_finished <= not cycle_busy;
|
||||
|
||||
-- proc_bus_read_counter:
|
||||
-- process(clk)
|
||||
-- begin
|
||||
-- if rising_edge(clk) then
|
||||
-- if rst = '1' then
|
||||
-- read_cnt <= 0;
|
||||
-- elsif cmd_read_en = '1' and read_fifo_we = '0' then
|
||||
-- read_cnt <= read_cnt + 1;
|
||||
-- elsif cmd_read_en = '0' and read_fifo_we = '1' then
|
||||
-- read_cnt <= read_cnt - 1;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
proc_bus_read_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
read_cnt <= 0;
|
||||
elsif cmd_read_en = '1' and read_fifo_empty = '1' then
|
||||
read_cnt <= read_cnt + 1;
|
||||
elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then
|
||||
read_cnt <= read_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_cycle_busy:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
cycle_busy <= '0';
|
||||
elsif cmd_cycle_en = '1' then
|
||||
if cmd_we = '1' then
|
||||
cycle_busy <= '1';
|
||||
end if;
|
||||
elsif read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
|
||||
cycle_busy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Bus READ FIFO
|
||||
inst_BM_READ_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => read_fifo_we,
|
||||
re => read_fifo_re,
|
||||
fifo_full => read_fifo_full,
|
||||
fifo_empty => read_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => MDAT_I,
|
||||
data_r => dout
|
||||
);
|
||||
|
||||
-- Bus WRITE FIFO
|
||||
inst_BM_WRITE_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => din,
|
||||
data_r => MDAT_O
|
||||
);
|
||||
|
||||
-- Bus command FIFO
|
||||
inst_BM_CMD_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => cmd_fifo_din'length,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => cmd_fifo_we,
|
||||
re => cmd_fifo_re,
|
||||
fifo_full => cmd_fifo_full,
|
||||
fifo_empty => cmd_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => cmd_fifo_din,
|
||||
data_r => cmd_fifo_dout
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.6 2013/08/03 19:31:19 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity busmaster_sync is
|
||||
Generic
|
||||
(
|
||||
DATA_WIDTH : natural := 32;
|
||||
FIFO_DEPTH : natural := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
cmd_cycle_finished : out std_logic;
|
||||
cmd_cycle_en : in std_logic;
|
||||
cmd_rdy : out std_logic;
|
||||
cmd_we : in std_logic;
|
||||
|
||||
cmd_in : in bm_cmd_t;
|
||||
|
||||
din : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
din_rdy : out std_logic;
|
||||
din_we : in std_logic;
|
||||
|
||||
dout : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
dout_vld : out std_logic;
|
||||
dout_re : in std_logic;
|
||||
|
||||
-- J-BUS signals
|
||||
ACK_I : in std_logic;
|
||||
SRDY_I : in std_logic;
|
||||
MDAT_I : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
MDAT_O : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0);
|
||||
WE_O : out std_logic;
|
||||
CYC_O : out std_logic;
|
||||
STB_O : out std_logic;
|
||||
MRDY_O : out std_logic
|
||||
);
|
||||
end busmaster_sync;
|
||||
|
||||
architecture Behavioral of busmaster_sync is
|
||||
|
||||
-- Bus Command FIFO
|
||||
signal cmd_fifo_din : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_dout : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_re : std_logic;
|
||||
signal cmd_fifo_we : std_logic;
|
||||
signal cmd_fifo_full : std_logic;
|
||||
signal cmd_fifo_empty : std_logic;
|
||||
|
||||
-- Bus Read FIFO
|
||||
signal read_fifo_re : std_logic;
|
||||
signal read_fifo_we : std_logic;
|
||||
signal read_fifo_full : std_logic;
|
||||
signal read_fifo_empty : std_logic;
|
||||
signal write_fifo_re : std_logic;
|
||||
signal write_fifo_we : std_logic;
|
||||
signal write_fifo_full : std_logic;
|
||||
signal write_fifo_empty : std_logic;
|
||||
signal cycle_busy : std_logic;
|
||||
signal cmd_en : std_logic;
|
||||
signal cmd_read_en : std_logic;
|
||||
signal read_cnt : integer range 0 to 65535;
|
||||
signal write : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full;
|
||||
cmd_read_en <= cmd_en and not cmd_in.rw;
|
||||
write <= cmd_fifo_dout(32+DATA_WIDTH/8);
|
||||
|
||||
dout_vld <= not read_fifo_empty;
|
||||
MRDY_O <= not read_fifo_full;
|
||||
read_fifo_we <= ACK_I and cycle_busy;
|
||||
read_fifo_re <= dout_re;
|
||||
ADDR_O <= cmd_fifo_dout(31 downto 0);
|
||||
SEL_O <= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32);
|
||||
WE_O <= write;
|
||||
|
||||
cmd_fifo_din <= cmd_in.rw & cmd_in.sel & cmd_in.addr;
|
||||
|
||||
cmd_rdy <= not cmd_fifo_full;
|
||||
|
||||
cmd_fifo_we <= cmd_en;
|
||||
cmd_fifo_re <= SRDY_I and cycle_busy;
|
||||
|
||||
din_rdy <= not write_fifo_full;
|
||||
write_fifo_we <= din_we;
|
||||
write_fifo_re <= SRDY_I and cycle_busy and write and not cmd_fifo_empty;
|
||||
|
||||
STB_O <= not cmd_fifo_empty;
|
||||
CYC_O <= cycle_busy;
|
||||
cmd_cycle_finished <= not cycle_busy;
|
||||
|
||||
-- proc_bus_read_counter:
|
||||
-- process(clk)
|
||||
-- begin
|
||||
-- if rising_edge(clk) then
|
||||
-- if rst = '1' then
|
||||
-- read_cnt <= 0;
|
||||
-- elsif cmd_read_en = '1' and read_fifo_we = '0' then
|
||||
-- read_cnt <= read_cnt + 1;
|
||||
-- elsif cmd_read_en = '0' and read_fifo_we = '1' then
|
||||
-- read_cnt <= read_cnt - 1;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
proc_bus_read_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
read_cnt <= 0;
|
||||
elsif cmd_read_en = '1' and read_fifo_empty = '1' then
|
||||
read_cnt <= read_cnt + 1;
|
||||
elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then
|
||||
read_cnt <= read_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_cycle_busy:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
cycle_busy <= '0';
|
||||
elsif cmd_cycle_en = '1' then
|
||||
if cmd_we = '1' then
|
||||
cycle_busy <= '1';
|
||||
end if;
|
||||
elsif read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
|
||||
cycle_busy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Bus READ FIFO
|
||||
inst_BM_READ_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => read_fifo_we,
|
||||
re => read_fifo_re,
|
||||
fifo_full => read_fifo_full,
|
||||
fifo_empty => read_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => MDAT_I,
|
||||
data_r => dout
|
||||
);
|
||||
|
||||
-- Bus WRITE FIFO
|
||||
inst_BM_WRITE_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => din,
|
||||
data_r => MDAT_O
|
||||
);
|
||||
|
||||
-- Bus command FIFO
|
||||
inst_BM_CMD_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => cmd_fifo_din'length,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => cmd_fifo_we,
|
||||
re => cmd_fifo_re,
|
||||
fifo_full => cmd_fifo_full,
|
||||
fifo_empty => cmd_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => cmd_fifo_din,
|
||||
data_r => cmd_fifo_dout
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,31 +1,31 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_types.vhd,v 1.2 2013-05-27 11:17:51 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
|
||||
package busmaster_types is
|
||||
|
||||
-- Constants
|
||||
|
||||
-- Types
|
||||
|
||||
type bm_cmd_t is
|
||||
record
|
||||
addr : unsigned(31 downto 0);
|
||||
sel : unsigned(3 downto 0);
|
||||
rw : std_logic;
|
||||
end record;
|
||||
|
||||
end busmaster_types;
|
||||
|
||||
|
||||
package body busmaster_types is
|
||||
|
||||
|
||||
end busmaster_types;
|
||||
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/busmaster_types.vhd,v 1.2 2013/05/27 11:17:51 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
|
||||
package busmaster_types is
|
||||
|
||||
-- Constants
|
||||
|
||||
-- Types
|
||||
|
||||
type bm_cmd_t is
|
||||
record
|
||||
addr : unsigned(31 downto 0);
|
||||
sel : unsigned(3 downto 0);
|
||||
rw : std_logic;
|
||||
end record;
|
||||
|
||||
end busmaster_types;
|
||||
|
||||
|
||||
package body busmaster_types is
|
||||
|
||||
|
||||
end busmaster_types;
|
||||
|
||||
|
||||
|
||||
+230
-229
@@ -1,229 +1,230 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/dmac.vhd,v 1.2 2013-05-28 11:23:15 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity dmac is
|
||||
Generic
|
||||
(
|
||||
DATA_WIDTH : natural := 32;
|
||||
XFER_CHUNK_SIZE : natural := 512
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
master_req : out std_logic;
|
||||
master_gnt : in std_logic;
|
||||
|
||||
dma_start : out std_logic;
|
||||
dma_active : out std_logic;
|
||||
dma_end : out std_logic;
|
||||
|
||||
req_rdy : out std_logic;
|
||||
req_en : in std_logic;
|
||||
req_rw : in std_logic;
|
||||
req_addr_start : in unsigned(31 downto 0);
|
||||
req_num_xfers : in unsigned(31 downto 0);
|
||||
req_addr_auto_inc : in std_logic;
|
||||
|
||||
req_complete : out std_logic;
|
||||
req_complete_ack : in std_logic;
|
||||
|
||||
-- busmaster control
|
||||
bus_cyc_complete : in std_logic;
|
||||
bus_cmd_rdy : in std_logic;
|
||||
bus_cmd_we : out std_logic;
|
||||
bus_cmd_cycle_en : out std_logic;
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_out : out bm_cmd_t
|
||||
);
|
||||
end dmac;
|
||||
|
||||
architecture Behavioral of dmac is
|
||||
|
||||
signal start_en : std_logic;
|
||||
signal finish_en : std_logic;
|
||||
signal complete : std_logic;
|
||||
signal addr_inc_en : std_logic;
|
||||
signal addr : unsigned(31 downto 0);
|
||||
signal rw : std_logic;
|
||||
|
||||
signal req_count_en : std_logic;
|
||||
signal req_count : unsigned(31 downto 0);
|
||||
signal req_count_next : unsigned(32 downto 0);
|
||||
signal req_count_rdy : std_logic;
|
||||
|
||||
signal chunk_count_rst : std_logic;
|
||||
signal chunk_count_en : std_logic;
|
||||
signal chunk_count : unsigned(31 downto 0);
|
||||
signal chunk_count_next : unsigned(32 downto 0);
|
||||
signal chunk_count_rdy : std_logic;
|
||||
|
||||
type state_t is (INIT, READY, START, SETUP, XFER, FINISH, DONE);
|
||||
signal s, sn : state_t;
|
||||
|
||||
begin
|
||||
|
||||
bus_cmd_out.addr <= addr;
|
||||
bus_cmd_out.sel <= (others => '1');
|
||||
bus_cmd_out.rw <= rw;
|
||||
req_complete <= complete;
|
||||
|
||||
state_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
s <= INIT;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
state:
|
||||
process(s, req_en, master_gnt, req_count_rdy, chunk_count_rdy, bus_cyc_complete, bus_cmd_rdy)
|
||||
begin
|
||||
|
||||
bus_cmd_cycle_en <= '0';
|
||||
bus_cmd_we <= '0';
|
||||
start_en <= '0';
|
||||
finish_en <= '0';
|
||||
req_count_en <= '0';
|
||||
req_rdy <= '0';
|
||||
chunk_count_rst <= '0';
|
||||
chunk_count_en <= '0';
|
||||
master_req <= '0';
|
||||
dma_start <= '0';
|
||||
dma_active <= '0';
|
||||
dma_end <= '0';
|
||||
|
||||
sn <= s;
|
||||
case s is
|
||||
when INIT =>
|
||||
sn <= READY;
|
||||
|
||||
when READY =>
|
||||
req_rdy <= '1';
|
||||
if req_en = '1' then
|
||||
start_en <= '1';
|
||||
sn <= SETUP;
|
||||
end if;
|
||||
|
||||
when SETUP =>
|
||||
dma_start <= '1';
|
||||
sn <= START;
|
||||
|
||||
when START =>
|
||||
master_req <= '1';
|
||||
chunk_count_rst <= '1';
|
||||
if req_count_rdy = '1' then
|
||||
sn <= READY;
|
||||
elsif master_gnt = '1' and bus_cyc_complete = '1' then
|
||||
sn <= XFER;
|
||||
end if;
|
||||
|
||||
when XFER =>
|
||||
dma_active <= '1';
|
||||
master_req <= '1';
|
||||
bus_cmd_we <= '1';
|
||||
bus_cmd_cycle_en <= '1';
|
||||
req_count_en <= bus_cmd_rdy;
|
||||
chunk_count_en <= bus_cmd_rdy;
|
||||
if req_count_rdy = '1' then
|
||||
sn <= FINISH;
|
||||
elsif chunk_count_rdy = '1' then
|
||||
sn <= START;
|
||||
end if;
|
||||
|
||||
when FINISH =>
|
||||
master_req <= '1';
|
||||
if bus_cyc_complete = '1' then
|
||||
sn <= DONE;
|
||||
finish_en <= '1';
|
||||
end if;
|
||||
|
||||
when DONE =>
|
||||
dma_end <= '1';
|
||||
sn <= READY;
|
||||
|
||||
when others =>
|
||||
sn <= READY;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
addr_gen:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' then
|
||||
rw <= req_rw;
|
||||
addr <= req_addr_start;
|
||||
addr_inc_en <= req_addr_auto_inc;
|
||||
elsif req_count_en = '1' and addr_inc_en = '1' then
|
||||
addr <= addr + DATA_WIDTH/8;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
req_count_next <= ('0' & req_num_xfers) - 1 when start_en = '1' else ('0' & req_count) - 1;
|
||||
req_count_rdy <= req_count_next(32);
|
||||
|
||||
req_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' then
|
||||
req_count <= req_count_next(31 downto 0);
|
||||
elsif req_count_en = '1' then
|
||||
if req_count_rdy = '0' then
|
||||
req_count <= req_count_next(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
chunk_count_next <= to_unsigned(XFER_CHUNK_SIZE, 33) - 1 when chunk_count_rst = '1' else ('0' & chunk_count) - 1;
|
||||
chunk_count_rdy <= chunk_count_next(32);
|
||||
|
||||
chunk_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if chunk_count_rst = '1' then
|
||||
chunk_count <= chunk_count_next(31 downto 0);
|
||||
elsif chunk_count_en = '1' then
|
||||
if chunk_count_rdy = '0' then
|
||||
chunk_count <= chunk_count_next(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
complete_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' or rst = '1' then
|
||||
complete <= '0';
|
||||
elsif complete = '0' then
|
||||
if finish_en = '1' then
|
||||
complete <= '1';
|
||||
elsif req_complete_ack = '1' then
|
||||
complete <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/dmac.vhd,v 1.2 2013/05/28 11:23:15 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity dmac is
|
||||
Generic
|
||||
(
|
||||
DATA_WIDTH : natural := 32;
|
||||
XFER_CHUNK_SIZE : natural := 512
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
master_req : out std_logic;
|
||||
master_gnt : in std_logic;
|
||||
|
||||
dma_start : out std_logic;
|
||||
dma_active : out std_logic;
|
||||
dma_end : out std_logic;
|
||||
|
||||
req_rdy : out std_logic;
|
||||
req_en : in std_logic;
|
||||
req_rw : in std_logic;
|
||||
req_addr_start : in unsigned(31 downto 0);
|
||||
req_num_xfers : in unsigned(31 downto 0);
|
||||
req_addr_auto_inc : in std_logic;
|
||||
|
||||
req_complete : out std_logic;
|
||||
req_complete_ack : in std_logic;
|
||||
|
||||
-- busmaster control
|
||||
bus_cyc_complete : in std_logic;
|
||||
bus_cmd_rdy : in std_logic;
|
||||
bus_cmd_we : out std_logic;
|
||||
bus_cmd_cycle_en : out std_logic;
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_out : out bm_cmd_t
|
||||
);
|
||||
end dmac;
|
||||
|
||||
architecture Behavioral of dmac is
|
||||
|
||||
signal start_en : std_logic;
|
||||
signal finish_en : std_logic;
|
||||
signal complete : std_logic;
|
||||
signal addr_inc_en : std_logic;
|
||||
signal addr : unsigned(31 downto 0);
|
||||
signal rw : std_logic;
|
||||
|
||||
signal req_count_en : std_logic;
|
||||
signal req_count : unsigned(31 downto 0);
|
||||
signal req_count_next : unsigned(32 downto 0);
|
||||
signal req_count_rdy : std_logic;
|
||||
|
||||
signal chunk_count_rst : std_logic;
|
||||
signal chunk_count_en : std_logic;
|
||||
signal chunk_count : unsigned(31 downto 0);
|
||||
signal chunk_count_next : unsigned(32 downto 0);
|
||||
signal chunk_count_rdy : std_logic;
|
||||
|
||||
type state_t is (INIT, READY, START, SETUP, XFER, FINISH, DONE);
|
||||
signal s, sn : state_t;
|
||||
|
||||
begin
|
||||
|
||||
bus_cmd_out.addr <= addr;
|
||||
bus_cmd_out.sel <= (others => '1');
|
||||
bus_cmd_out.rw <= rw;
|
||||
req_complete <= complete;
|
||||
|
||||
state_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
s <= INIT;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
state:
|
||||
process(s, req_en, master_gnt, req_count_rdy, chunk_count_rdy, bus_cyc_complete, bus_cmd_rdy)
|
||||
begin
|
||||
|
||||
bus_cmd_cycle_en <= '0';
|
||||
bus_cmd_we <= '0';
|
||||
start_en <= '0';
|
||||
finish_en <= '0';
|
||||
req_count_en <= '0';
|
||||
req_rdy <= '0';
|
||||
chunk_count_rst <= '0';
|
||||
chunk_count_en <= '0';
|
||||
master_req <= '0';
|
||||
dma_start <= '0';
|
||||
dma_active <= '0';
|
||||
dma_end <= '0';
|
||||
|
||||
sn <= s;
|
||||
case s is
|
||||
when INIT =>
|
||||
sn <= READY;
|
||||
|
||||
when READY =>
|
||||
req_rdy <= '1';
|
||||
if req_en = '1' then
|
||||
start_en <= '1';
|
||||
sn <= SETUP;
|
||||
end if;
|
||||
|
||||
when SETUP =>
|
||||
dma_start <= '1';
|
||||
sn <= START;
|
||||
|
||||
when START =>
|
||||
master_req <= '1';
|
||||
chunk_count_rst <= '1';
|
||||
if req_count_rdy = '1' then
|
||||
sn <= READY;
|
||||
elsif master_gnt = '1' and bus_cyc_complete = '1' then
|
||||
sn <= XFER;
|
||||
end if;
|
||||
|
||||
when XFER =>
|
||||
dma_active <= '1';
|
||||
master_req <= '1';
|
||||
bus_cmd_we <= '1';
|
||||
bus_cmd_cycle_en <= '1';
|
||||
req_count_en <= bus_cmd_rdy;
|
||||
chunk_count_en <= bus_cmd_rdy;
|
||||
if req_count_rdy = '1' then
|
||||
sn <= FINISH;
|
||||
elsif chunk_count_rdy = '1' then
|
||||
sn <= START;
|
||||
end if;
|
||||
|
||||
when FINISH =>
|
||||
master_req <= '1';
|
||||
dma_end <= '1';
|
||||
sn <= DONE;
|
||||
|
||||
when DONE =>
|
||||
master_req <= '1';
|
||||
if bus_cyc_complete = '1' then
|
||||
sn <= READY;
|
||||
finish_en <= '1';
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
sn <= READY;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
addr_gen:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' then
|
||||
rw <= req_rw;
|
||||
addr <= req_addr_start;
|
||||
addr_inc_en <= req_addr_auto_inc;
|
||||
elsif req_count_en = '1' and addr_inc_en = '1' then
|
||||
addr <= addr + DATA_WIDTH/8;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
req_count_next <= ('0' & req_num_xfers) - 1 when start_en = '1' else ('0' & req_count) - 1;
|
||||
req_count_rdy <= req_count_next(32);
|
||||
|
||||
req_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' then
|
||||
req_count <= req_count_next(31 downto 0);
|
||||
elsif req_count_en = '1' then
|
||||
if req_count_rdy = '0' then
|
||||
req_count <= req_count_next(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
chunk_count_next <= to_unsigned(XFER_CHUNK_SIZE, 33) - 1 when chunk_count_rst = '1' else ('0' & chunk_count) - 1;
|
||||
chunk_count_rdy <= chunk_count_next(32);
|
||||
|
||||
chunk_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if chunk_count_rst = '1' then
|
||||
chunk_count <= chunk_count_next(31 downto 0);
|
||||
elsif chunk_count_en = '1' then
|
||||
if chunk_count_rdy = '0' then
|
||||
chunk_count <= chunk_count_next(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
complete_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' or rst = '1' then
|
||||
complete <= '0';
|
||||
elsif complete = '0' then
|
||||
if finish_en = '1' then
|
||||
complete <= '1';
|
||||
elsif req_complete_ack = '1' then
|
||||
complete <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
+451
-451
@@ -1,451 +1,451 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_async.vhd,v 1.1 2013-07-21 09:21:30 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY tb_busmaster_async IS
|
||||
END tb_busmaster_async;
|
||||
|
||||
ARCHITECTURE behavior OF tb_busmaster_async IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant JBUS_CLK_PERIOD : time := 20 ns;
|
||||
signal clk : std_logic := '1';
|
||||
signal rst : std_logic := '1';
|
||||
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
|
||||
-- Master
|
||||
signal INT_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-');
|
||||
signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-');
|
||||
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
signal cmd_cycle_finished : std_logic;
|
||||
signal cmd_cycle_en : std_logic := '0';
|
||||
signal cmd_rdy : std_logic;
|
||||
signal cmd_we : std_logic := '0';
|
||||
|
||||
signal cmd_in : bm_cmd_t;
|
||||
|
||||
signal din : unsigned(31 downto 0) := (others => '-');
|
||||
signal din_rdy : std_logic;
|
||||
signal din_we : std_logic := '0';
|
||||
|
||||
signal dout : unsigned(31 downto 0);
|
||||
signal dout_vld : std_logic;
|
||||
signal dout_re : std_logic := '0';
|
||||
|
||||
signal read_reg : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
|
||||
signal state : state_t := IDLE;
|
||||
|
||||
type ram_t is array (0 to 127) of unsigned(63 downto 0);
|
||||
|
||||
signal ram64 : ram_t :=
|
||||
(
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000"
|
||||
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
MDAT_I <= MDAT_I_64(31 downto 0);
|
||||
MDAT_O_64 <= MDAT_O & MDAT_O;
|
||||
|
||||
inst_uut : entity work.busmaster_async
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
FIFO_DEPTH => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
|
||||
cmd_cycle_finished => cmd_cycle_finished,
|
||||
cmd_cycle_en => cmd_cycle_en,
|
||||
cmd_rdy => cmd_rdy,
|
||||
cmd_we => cmd_we,
|
||||
cmd_in => cmd_in,
|
||||
|
||||
din => din,
|
||||
din_rdy => din_rdy,
|
||||
din_we => din_we,
|
||||
|
||||
dout => dout,
|
||||
dout_vld => dout_vld,
|
||||
dout_re => dout_re,
|
||||
|
||||
-- JBUS Master signals
|
||||
RST_I => RST_O,
|
||||
CLK_I => CLK_O,
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
JBUS_CLK_GEN: process
|
||||
begin
|
||||
wait for JBUS_CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
-- Slave
|
||||
SRDY_I <= CYC_O;
|
||||
|
||||
process(CLK_O)
|
||||
variable res: unsigned(63 downto 0);
|
||||
variable ram_data : unsigned(63 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
else
|
||||
ACK_I <= '0';
|
||||
if (CYC_O and STB_O) = '1' then
|
||||
if WE_O = '0' then
|
||||
ACK_I <= '1';
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
if ADDR_O(2) = '0' then
|
||||
res := ram_data;
|
||||
else
|
||||
res := ram_data(31 downto 0) & ram_data(63 downto 32);
|
||||
end if;
|
||||
elsif MRDY_O = '1' then -- WE=1
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
ram_data := (others => '-');
|
||||
if ADDR_O(2) = '0' then
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
|
||||
end if;
|
||||
else
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if (CYC_O and MRDY_O) = '1' then
|
||||
MDAT_I_64 <= res;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
read_reg <= X"00000000";
|
||||
elsif dout_vld = '1' then
|
||||
read_reg <= dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dout_re <= dout_vld;
|
||||
|
||||
-- Master
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_write_single(addr, sel, data : unsigned) is
|
||||
begin
|
||||
|
||||
din <= data;
|
||||
din_we <= '1';
|
||||
wait until rising_edge(clk) and din_rdy = '1';
|
||||
din_we <= '0';
|
||||
|
||||
cmd_in.rw <= '1';
|
||||
cmd_in.sel <= sel;
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(clk) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_write_single;
|
||||
|
||||
procedure cmd_read_single(addr : unsigned) is
|
||||
begin
|
||||
|
||||
cmd_in.rw <= '0';
|
||||
cmd_in.sel <= (others => '0');
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(clk) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_read_single;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
RST_O <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
state <= IDLE;
|
||||
|
||||
for i in 0 to 9 loop
|
||||
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_ABCD");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_ABCD");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_ABCD");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_ABCD");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_ABCD");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_ABCD");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_ABCD");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_ABCD");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_BEEF");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_BEEF");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_BEEF");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_BEEF");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_BEEF");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_BEEF");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_BEEF");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_BEEF");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_cycle_en <= '0';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_ABCD");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_ABCD");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_ABCD");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_ABCD");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_ABCD");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_ABCD");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_ABCD");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_ABCD");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_BEEF");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_BEEF");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_BEEF");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_BEEF");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_BEEF");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_BEEF");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_BEEF");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_BEEF");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_cycle_en <= '0';
|
||||
|
||||
wait until rising_edge(clk) and cmd_cycle_finished = '1';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
end loop;
|
||||
|
||||
state <= IDLE;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/tb_busmaster_async.vhd,v 1.1 2013/07/21 09:21:30 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY tb_busmaster_async IS
|
||||
END tb_busmaster_async;
|
||||
|
||||
ARCHITECTURE behavior OF tb_busmaster_async IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant JBUS_CLK_PERIOD : time := 20 ns;
|
||||
signal clk : std_logic := '1';
|
||||
signal rst : std_logic := '1';
|
||||
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
|
||||
-- Master
|
||||
signal INT_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-');
|
||||
signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-');
|
||||
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
signal cmd_cycle_finished : std_logic;
|
||||
signal cmd_cycle_en : std_logic := '0';
|
||||
signal cmd_rdy : std_logic;
|
||||
signal cmd_we : std_logic := '0';
|
||||
|
||||
signal cmd_in : bm_cmd_t;
|
||||
|
||||
signal din : unsigned(31 downto 0) := (others => '-');
|
||||
signal din_rdy : std_logic;
|
||||
signal din_we : std_logic := '0';
|
||||
|
||||
signal dout : unsigned(31 downto 0);
|
||||
signal dout_vld : std_logic;
|
||||
signal dout_re : std_logic := '0';
|
||||
|
||||
signal read_reg : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
|
||||
signal state : state_t := IDLE;
|
||||
|
||||
type ram_t is array (0 to 127) of unsigned(63 downto 0);
|
||||
|
||||
signal ram64 : ram_t :=
|
||||
(
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000"
|
||||
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
MDAT_I <= MDAT_I_64(31 downto 0);
|
||||
MDAT_O_64 <= MDAT_O & MDAT_O;
|
||||
|
||||
inst_uut : entity work.busmaster_async
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
FIFO_DEPTH => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
|
||||
cmd_cycle_finished => cmd_cycle_finished,
|
||||
cmd_cycle_en => cmd_cycle_en,
|
||||
cmd_rdy => cmd_rdy,
|
||||
cmd_we => cmd_we,
|
||||
cmd_in => cmd_in,
|
||||
|
||||
din => din,
|
||||
din_rdy => din_rdy,
|
||||
din_we => din_we,
|
||||
|
||||
dout => dout,
|
||||
dout_vld => dout_vld,
|
||||
dout_re => dout_re,
|
||||
|
||||
-- JBUS Master signals
|
||||
RST_I => RST_O,
|
||||
CLK_I => CLK_O,
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
JBUS_CLK_GEN: process
|
||||
begin
|
||||
wait for JBUS_CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
-- Slave
|
||||
SRDY_I <= CYC_O;
|
||||
|
||||
process(CLK_O)
|
||||
variable res: unsigned(63 downto 0);
|
||||
variable ram_data : unsigned(63 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
else
|
||||
ACK_I <= '0';
|
||||
if (CYC_O and STB_O) = '1' then
|
||||
if WE_O = '0' then
|
||||
ACK_I <= '1';
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
if ADDR_O(2) = '0' then
|
||||
res := ram_data;
|
||||
else
|
||||
res := ram_data(31 downto 0) & ram_data(63 downto 32);
|
||||
end if;
|
||||
elsif MRDY_O = '1' then -- WE=1
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
ram_data := (others => '-');
|
||||
if ADDR_O(2) = '0' then
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
|
||||
end if;
|
||||
else
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if (CYC_O and MRDY_O) = '1' then
|
||||
MDAT_I_64 <= res;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
read_reg <= X"00000000";
|
||||
elsif dout_vld = '1' then
|
||||
read_reg <= dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dout_re <= dout_vld;
|
||||
|
||||
-- Master
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_write_single(addr, sel, data : unsigned) is
|
||||
begin
|
||||
|
||||
din <= data;
|
||||
din_we <= '1';
|
||||
wait until rising_edge(clk) and din_rdy = '1';
|
||||
din_we <= '0';
|
||||
|
||||
cmd_in.rw <= '1';
|
||||
cmd_in.sel <= sel;
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(clk) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_write_single;
|
||||
|
||||
procedure cmd_read_single(addr : unsigned) is
|
||||
begin
|
||||
|
||||
cmd_in.rw <= '0';
|
||||
cmd_in.sel <= (others => '0');
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(clk) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_read_single;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
RST_O <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
state <= IDLE;
|
||||
|
||||
for i in 0 to 9 loop
|
||||
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_ABCD");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_ABCD");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_ABCD");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_ABCD");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_ABCD");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_ABCD");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_ABCD");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_ABCD");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_BEEF");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_BEEF");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_BEEF");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_BEEF");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_BEEF");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_BEEF");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_BEEF");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_BEEF");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_cycle_en <= '0';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_ABCD");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_ABCD");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_ABCD");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_ABCD");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_ABCD");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_ABCD");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_ABCD");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_ABCD");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_BEEF");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_BEEF");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_BEEF");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_BEEF");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_BEEF");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_BEEF");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_BEEF");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_BEEF");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_cycle_en <= '0';
|
||||
|
||||
wait until rising_edge(clk) and cmd_cycle_finished = '1';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
end loop;
|
||||
|
||||
state <= IDLE;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
|
||||
+446
-446
@@ -1,446 +1,446 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.3 2013-07-21 09:10:13 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY tb_busmaster_sync IS
|
||||
END tb_busmaster_sync;
|
||||
|
||||
ARCHITECTURE behavior OF tb_busmaster_sync IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
|
||||
-- Master
|
||||
signal INT_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-');
|
||||
signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-');
|
||||
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
signal cmd_cycle_finished : std_logic;
|
||||
signal cmd_cycle_en : std_logic := '0';
|
||||
signal cmd_rdy : std_logic;
|
||||
signal cmd_we : std_logic := '0';
|
||||
|
||||
signal cmd_in : bm_cmd_t;
|
||||
|
||||
signal din : unsigned(31 downto 0) := (others => '-');
|
||||
signal din_rdy : std_logic;
|
||||
signal din_we : std_logic := '0';
|
||||
|
||||
signal dout : unsigned(31 downto 0);
|
||||
signal dout_vld : std_logic;
|
||||
signal dout_re : std_logic := '0';
|
||||
|
||||
signal rdy : std_logic := '0';
|
||||
signal read_reg : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
|
||||
signal state : state_t := IDLE;
|
||||
|
||||
type ram_t is array (0 to 127) of unsigned(63 downto 0);
|
||||
|
||||
signal ram64 : ram_t :=
|
||||
(
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000"
|
||||
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
MDAT_I <= MDAT_I_64(31 downto 0);
|
||||
MDAT_O_64 <= MDAT_O & MDAT_O;
|
||||
|
||||
inst_uut : entity work.busmaster_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
FIFO_DEPTH => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST_O,
|
||||
clk => CLK_O,
|
||||
|
||||
cmd_cycle_finished => cmd_cycle_finished,
|
||||
cmd_cycle_en => cmd_cycle_en,
|
||||
cmd_rdy => cmd_rdy,
|
||||
cmd_we => cmd_we,
|
||||
cmd_in => cmd_in,
|
||||
|
||||
din => din,
|
||||
din_rdy => din_rdy,
|
||||
din_we => din_we,
|
||||
|
||||
dout => dout,
|
||||
dout_vld => dout_vld,
|
||||
dout_re => dout_re,
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
rdy_GEN: process
|
||||
begin
|
||||
-- wait for 3*CLK_PERIOD/2;
|
||||
wait until rising_edge(CLK_O);
|
||||
rdy <= not rdy;
|
||||
end process;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
-- Slave
|
||||
SRDY_I <= CYC_O;
|
||||
|
||||
process(CLK_O)
|
||||
variable res: unsigned(63 downto 0);
|
||||
variable ram_data : unsigned(63 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
else
|
||||
ACK_I <= '0';
|
||||
if (CYC_O and STB_O) = '1' then
|
||||
if WE_O = '0' then
|
||||
ACK_I <= '1';
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
if ADDR_O(2) = '0' then
|
||||
res := ram_data;
|
||||
else
|
||||
res := ram_data(31 downto 0) & ram_data(63 downto 32);
|
||||
end if;
|
||||
elsif MRDY_O = '1' then -- WE=1
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
ram_data := (others => '-');
|
||||
if ADDR_O(2) = '0' then
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
|
||||
end if;
|
||||
else
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if (CYC_O and MRDY_O) = '1' then
|
||||
MDAT_I_64 <= res;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(CLK_O)
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
read_reg <= X"00000000";
|
||||
elsif dout_vld = '1' then
|
||||
read_reg <= dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dout_re <= dout_vld;
|
||||
|
||||
-- Master
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_write_single(addr, sel, data : unsigned) is
|
||||
begin
|
||||
|
||||
din <= data;
|
||||
din_we <= '1';
|
||||
wait until rising_edge(CLK_O) and din_rdy = '1';
|
||||
din_we <= '0';
|
||||
|
||||
cmd_in.rw <= '1';
|
||||
cmd_in.sel <= sel;
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(CLK_O) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_write_single;
|
||||
|
||||
procedure cmd_read_single(addr : unsigned) is
|
||||
begin
|
||||
|
||||
cmd_in.rw <= '0';
|
||||
cmd_in.sel <= (others => '0');
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(CLK_O) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_read_single;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
RST_O <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
state <= IDLE;
|
||||
|
||||
for i in 0 to 9 loop
|
||||
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_ABCD");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_ABCD");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_ABCD");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_ABCD");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_ABCD");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_ABCD");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_ABCD");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_ABCD");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_BEEF");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_BEEF");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_BEEF");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_BEEF");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_BEEF");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_BEEF");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_BEEF");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_BEEF");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_cycle_en <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
wait until rising_edge(CLK_O);
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_ABCD");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_ABCD");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_ABCD");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_ABCD");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_ABCD");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_ABCD");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_ABCD");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_ABCD");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_BEEF");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_BEEF");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_BEEF");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_BEEF");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_BEEF");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_BEEF");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_BEEF");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_BEEF");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_cycle_en <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O) and cmd_cycle_finished = '1';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
|
||||
end loop;
|
||||
|
||||
state <= IDLE;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.3 2013/07/21 09:10:13 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY tb_busmaster_sync IS
|
||||
END tb_busmaster_sync;
|
||||
|
||||
ARCHITECTURE behavior OF tb_busmaster_sync IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
|
||||
-- Master
|
||||
signal INT_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-');
|
||||
signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-');
|
||||
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
signal cmd_cycle_finished : std_logic;
|
||||
signal cmd_cycle_en : std_logic := '0';
|
||||
signal cmd_rdy : std_logic;
|
||||
signal cmd_we : std_logic := '0';
|
||||
|
||||
signal cmd_in : bm_cmd_t;
|
||||
|
||||
signal din : unsigned(31 downto 0) := (others => '-');
|
||||
signal din_rdy : std_logic;
|
||||
signal din_we : std_logic := '0';
|
||||
|
||||
signal dout : unsigned(31 downto 0);
|
||||
signal dout_vld : std_logic;
|
||||
signal dout_re : std_logic := '0';
|
||||
|
||||
signal rdy : std_logic := '0';
|
||||
signal read_reg : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
|
||||
signal state : state_t := IDLE;
|
||||
|
||||
type ram_t is array (0 to 127) of unsigned(63 downto 0);
|
||||
|
||||
signal ram64 : ram_t :=
|
||||
(
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000"
|
||||
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
MDAT_I <= MDAT_I_64(31 downto 0);
|
||||
MDAT_O_64 <= MDAT_O & MDAT_O;
|
||||
|
||||
inst_uut : entity work.busmaster_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
FIFO_DEPTH => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST_O,
|
||||
clk => CLK_O,
|
||||
|
||||
cmd_cycle_finished => cmd_cycle_finished,
|
||||
cmd_cycle_en => cmd_cycle_en,
|
||||
cmd_rdy => cmd_rdy,
|
||||
cmd_we => cmd_we,
|
||||
cmd_in => cmd_in,
|
||||
|
||||
din => din,
|
||||
din_rdy => din_rdy,
|
||||
din_we => din_we,
|
||||
|
||||
dout => dout,
|
||||
dout_vld => dout_vld,
|
||||
dout_re => dout_re,
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
rdy_GEN: process
|
||||
begin
|
||||
-- wait for 3*CLK_PERIOD/2;
|
||||
wait until rising_edge(CLK_O);
|
||||
rdy <= not rdy;
|
||||
end process;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
-- Slave
|
||||
SRDY_I <= CYC_O;
|
||||
|
||||
process(CLK_O)
|
||||
variable res: unsigned(63 downto 0);
|
||||
variable ram_data : unsigned(63 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
else
|
||||
ACK_I <= '0';
|
||||
if (CYC_O and STB_O) = '1' then
|
||||
if WE_O = '0' then
|
||||
ACK_I <= '1';
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
if ADDR_O(2) = '0' then
|
||||
res := ram_data;
|
||||
else
|
||||
res := ram_data(31 downto 0) & ram_data(63 downto 32);
|
||||
end if;
|
||||
elsif MRDY_O = '1' then -- WE=1
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
ram_data := (others => '-');
|
||||
if ADDR_O(2) = '0' then
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
|
||||
end if;
|
||||
else
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if (CYC_O and MRDY_O) = '1' then
|
||||
MDAT_I_64 <= res;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(CLK_O)
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
read_reg <= X"00000000";
|
||||
elsif dout_vld = '1' then
|
||||
read_reg <= dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dout_re <= dout_vld;
|
||||
|
||||
-- Master
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_write_single(addr, sel, data : unsigned) is
|
||||
begin
|
||||
|
||||
din <= data;
|
||||
din_we <= '1';
|
||||
wait until rising_edge(CLK_O) and din_rdy = '1';
|
||||
din_we <= '0';
|
||||
|
||||
cmd_in.rw <= '1';
|
||||
cmd_in.sel <= sel;
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(CLK_O) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_write_single;
|
||||
|
||||
procedure cmd_read_single(addr : unsigned) is
|
||||
begin
|
||||
|
||||
cmd_in.rw <= '0';
|
||||
cmd_in.sel <= (others => '0');
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(CLK_O) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_read_single;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
RST_O <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
state <= IDLE;
|
||||
|
||||
for i in 0 to 9 loop
|
||||
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_ABCD");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_ABCD");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_ABCD");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_ABCD");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_ABCD");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_ABCD");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_ABCD");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_ABCD");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_BEEF");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_BEEF");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_BEEF");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_BEEF");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_BEEF");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_BEEF");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_BEEF");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_BEEF");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_cycle_en <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
wait until rising_edge(CLK_O);
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_ABCD");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_ABCD");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_ABCD");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_ABCD");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_ABCD");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_ABCD");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_ABCD");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_ABCD");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_BEEF");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_BEEF");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_BEEF");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_BEEF");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_BEEF");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_BEEF");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_BEEF");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_BEEF");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_cycle_en <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O) and cmd_cycle_finished = '1';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
|
||||
end loop;
|
||||
|
||||
state <= IDLE;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
|
||||
+540
-540
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user