- commit local changes after CVS2SVN

git-svn-id: http://moon:8086/svn/vhdl/trunk@1036 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/syn/ise101/mips_top.prj

@@ -1,21 +1,22 @@
-vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vhdl work "../../../../FIFO/src/gray_counter.vhd"
-vhdl work "../../../../misc/dpram_2w2r.vhd"
-vhdl work "../../../../misc/dpram_1w1r.vhd"
-vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
-vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
-vhdl work "../../src/core/mips_types.vhd"
-vhdl work "../../../../FIFO/src/fifo_sync.vhd"
-vhdl work "../../../../FIFO/src/fifo_async.vhd"
-vhdl work "../../src/core/mips_shifter.vhd"
-vhdl work "../../src/core/mips_reg.vhd"
-vhdl work "../../src/core/mips_muldiv.vhd"
-vhdl work "../../src/core/mips_instr.vhd"
-vhdl work "../../src/core/mips_icache.vhd"
-vhdl work "../../src/core/mips_dcache.vhd"
-vhdl work "../../src/core/mips_bcu.vhd"
-vhdl work "../../src/core/mips_alu.vhd"
-vhdl work "../../src/core/mips_pipeline.vhd"
-vhdl work "../../src/core/mips_cop.vhd"
-vhdl work "../../src/core/mips_biu.vhd"
-vhdl work "../../src/core/mips_top.vhd"
+vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../../../FIFO/src/gray_counter.vhd"
+vhdl work "../../../../rams/dpram_2w2r2c_ra_xil.vhd"
+vhdl work "../../../../rams/dpram_1w1r2c_ro_xil.vhd"
+vhdl work "../../../../rams/dpram_1w1r2c_ra_xil.vhd"
+vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
+vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
+vhdl work "../../src/core/mips_types.vhd"
+vhdl work "../../../../FIFO/src/fifo_sync.vhd"
+vhdl work "../../../../FIFO/src/fifo_async.vhd"
+vhdl work "../../src/core/mips_shifter.vhd"
+vhdl work "../../src/core/mips_reg.vhd"
+vhdl work "../../src/core/mips_muldiv.vhd"
+vhdl work "../../src/core/mips_instr.vhd"
+vhdl work "../../src/core/mips_icache.vhd"
+vhdl work "../../src/core/mips_dcache.vhd"
+vhdl work "../../src/core/mips_bcu.vhd"
+vhdl work "../../src/core/mips_alu.vhd"
+vhdl work "../../src/core/mips_pipeline.vhd"
+vhdl work "../../src/core/mips_cop.vhd"
+vhdl work "../../src/core/mips_biu.vhd"
+vhdl work "../../src/core/mips_top.vhd"

lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj

@@ -1,21 +1,22 @@
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
+vhdl work "W:\vhdl\lib\rams\dpram_2w2r2c_ra_xil.vhd"
+vhdl work "W:\vhdl\lib\rams\dpram_1w1r2c_ro_xil.vhd"
+vhdl work "W:\vhdl\lib\rams\dpram_1w1r2c_ra_xil.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"

lib/CPUs/MIPS/todo.txt

@@ -1,35 +1,40 @@
-2008-10-26
-- Area-Optimierung: DIV und MUL verwenden gleiche Ressourcen
-- Area-Optimierung: MUL32x32 primitive für Virtex-4
-- shifter: log shifter besser als built-in sll, srl, sra? Nein (2008-10-27)
-- External COP 1..3 interface
-- FPU (COP1)
-- MMU
-
-2008-10-27
-- Area vs. speed : Pipeline-stall statt forwarding
-- Caches: - Lock-up free cache (refill critical word first then un-lock CPU) (geringer Effekt, zu kompliziert => geringere Zuverlässigkeit)
-          - 1,2,4-way assoziative
-          - 2nd-Level cache in System
-          - Write-back policy
-
-2008-11-15
-- Bus exceptions IBE DBE (BUI/Cache restart notwendig)
-
-2009-03-18
-- cache line sizes von 1 word (4 bytes) gibt NULL-vector. Fehler in Berechnung der inedx_widths
-
-2009-8-8
-- Soft-Reset. Ähnlich wie Exception (Reset/NMI). Speicherung von EPC (done)
-- CP_COND
-
-2009-10-17
-- Soft-reset implemetiert. Register werden wie bei normaler Exception verändert. 
-  TodO: Bei Soft-reset (laut Buch) KUc=0, IEc=0 und BEV=1 initialisieren
-
-- Uncached write: Geht wie bei cached-write in den Write-Buffer. Folge: Mögliche lange Latenz bis uncached memory-mapped I/O tatsächlich geschieben wird.
-  Könnte bei IRQ acknowledging Probleme bereiten (z.b. mehrfaches (unötiges) anspringen der ISR, obwohl IRQ schon acknowleded wurde).
-  Work-around: Nach schreiben von memory-mapped I/O, gleiche Adresse zurücklesen (lesen wartet bis write-buffer leer).
-
-2010-01-09
-- COP dependency einführen => Pipeline stall, wenn COP Daten nicht verfügbar
+2008-10-26
+- Area-Optimierung: DIV und MUL verwenden gleiche Ressourcen
+- Area-Optimierung: MUL32x32 primitive für Virtex-4
+- shifter: log shifter besser als built-in sll, srl, sra? Nein (2008-10-27)
+- External COP 1..3 interface
+- FPU (COP1)
+- MMU
+
+2008-10-27
+- Area vs. speed : Pipeline-stall statt forwarding
+- Caches: - Lock-up free cache (refill critical word first then un-lock CPU) (geringer Effekt, zu kompliziert => geringere Zuverlässigkeit)
+          - 1,2,4-way assoziative
+          - 2nd-Level cache in System
+          - Write-back policy
+
+2008-11-15
+- Bus exceptions IBE DBE (BUI/Cache restart notwendig)
+
+2009-03-18
+- cache line sizes von 1 word (4 bytes) gibt NULL-vector. Fehler in Berechnung der inedx_widths
+
+2009-8-8
+- Soft-Reset. Ähnlich wie Exception (Reset/NMI). Speicherung von EPC (done)
+- CP_COND
+
+2009-10-17
+- Soft-reset implemetiert. Register werden wie bei normaler Exception verändert. 
+  TodO: Bei Soft-reset (laut Buch) KUc=0, IEc=0 und BEV=1 initialisieren
+
+- Uncached write: Geht wie bei cached-write in den Write-Buffer. Folge: Mögliche lange Latenz bis uncached memory-mapped I/O tatsächlich geschieben wird.
+  Könnte bei IRQ acknowledging Probleme bereiten (z.b. mehrfaches (unötiges) anspringen der ISR, obwohl IRQ schon acknowleded wurde).
+  Work-around: Nach schreiben von memory-mapped I/O, gleiche Adresse zurücklesen (lesen wartet bis write-buffer leer).
+
+2010-01-09
+- COP dependency einführen => Pipeline stall, wenn COP Daten nicht verfügbar
+
+213-08-25
+- TLB exception in EX-stage einbauen
+- Cache dout und ready um logic-level reduzieren
+- cam_ram_addr_rd um logic-level reduzieren