- commit local changes after CVS2SVN
git-svn-id: http://moon:8086/svn/vhdl/trunk@1036 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
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@@ -1,21 +1,22 @@
|
||||
vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vhdl work "../../../../FIFO/src/gray_counter.vhd"
|
||||
vhdl work "../../../../misc/dpram_2w2r.vhd"
|
||||
vhdl work "../../../../misc/dpram_1w1r.vhd"
|
||||
vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
|
||||
vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
|
||||
vhdl work "../../src/core/mips_types.vhd"
|
||||
vhdl work "../../../../FIFO/src/fifo_sync.vhd"
|
||||
vhdl work "../../../../FIFO/src/fifo_async.vhd"
|
||||
vhdl work "../../src/core/mips_shifter.vhd"
|
||||
vhdl work "../../src/core/mips_reg.vhd"
|
||||
vhdl work "../../src/core/mips_muldiv.vhd"
|
||||
vhdl work "../../src/core/mips_instr.vhd"
|
||||
vhdl work "../../src/core/mips_icache.vhd"
|
||||
vhdl work "../../src/core/mips_dcache.vhd"
|
||||
vhdl work "../../src/core/mips_bcu.vhd"
|
||||
vhdl work "../../src/core/mips_alu.vhd"
|
||||
vhdl work "../../src/core/mips_pipeline.vhd"
|
||||
vhdl work "../../src/core/mips_cop.vhd"
|
||||
vhdl work "../../src/core/mips_biu.vhd"
|
||||
vhdl work "../../src/core/mips_top.vhd"
|
||||
vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vhdl work "../../../../FIFO/src/gray_counter.vhd"
|
||||
vhdl work "../../../../rams/dpram_2w2r2c_ra_xil.vhd"
|
||||
vhdl work "../../../../rams/dpram_1w1r2c_ro_xil.vhd"
|
||||
vhdl work "../../../../rams/dpram_1w1r2c_ra_xil.vhd"
|
||||
vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
|
||||
vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
|
||||
vhdl work "../../src/core/mips_types.vhd"
|
||||
vhdl work "../../../../FIFO/src/fifo_sync.vhd"
|
||||
vhdl work "../../../../FIFO/src/fifo_async.vhd"
|
||||
vhdl work "../../src/core/mips_shifter.vhd"
|
||||
vhdl work "../../src/core/mips_reg.vhd"
|
||||
vhdl work "../../src/core/mips_muldiv.vhd"
|
||||
vhdl work "../../src/core/mips_instr.vhd"
|
||||
vhdl work "../../src/core/mips_icache.vhd"
|
||||
vhdl work "../../src/core/mips_dcache.vhd"
|
||||
vhdl work "../../src/core/mips_bcu.vhd"
|
||||
vhdl work "../../src/core/mips_alu.vhd"
|
||||
vhdl work "../../src/core/mips_pipeline.vhd"
|
||||
vhdl work "../../src/core/mips_cop.vhd"
|
||||
vhdl work "../../src/core/mips_biu.vhd"
|
||||
vhdl work "../../src/core/mips_top.vhd"
|
||||
|
||||
@@ -1,21 +1,22 @@
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
|
||||
vhdl work "W:\vhdl\lib\rams\dpram_2w2r2c_ra_xil.vhd"
|
||||
vhdl work "W:\vhdl\lib\rams\dpram_1w1r2c_ro_xil.vhd"
|
||||
vhdl work "W:\vhdl\lib\rams\dpram_1w1r2c_ra_xil.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
|
||||
|
||||
+40
-35
@@ -1,35 +1,40 @@
|
||||
2008-10-26
|
||||
- Area-Optimierung: DIV und MUL verwenden gleiche Ressourcen
|
||||
- Area-Optimierung: MUL32x32 primitive für Virtex-4
|
||||
- shifter: log shifter besser als built-in sll, srl, sra? Nein (2008-10-27)
|
||||
- External COP 1..3 interface
|
||||
- FPU (COP1)
|
||||
- MMU
|
||||
|
||||
2008-10-27
|
||||
- Area vs. speed : Pipeline-stall statt forwarding
|
||||
- Caches: - Lock-up free cache (refill critical word first then un-lock CPU) (geringer Effekt, zu kompliziert => geringere Zuverlässigkeit)
|
||||
- 1,2,4-way assoziative
|
||||
- 2nd-Level cache in System
|
||||
- Write-back policy
|
||||
|
||||
2008-11-15
|
||||
- Bus exceptions IBE DBE (BUI/Cache restart notwendig)
|
||||
|
||||
2009-03-18
|
||||
- cache line sizes von 1 word (4 bytes) gibt NULL-vector. Fehler in Berechnung der inedx_widths
|
||||
|
||||
2009-8-8
|
||||
- Soft-Reset. Ähnlich wie Exception (Reset/NMI). Speicherung von EPC (done)
|
||||
- CP_COND
|
||||
|
||||
2009-10-17
|
||||
- Soft-reset implemetiert. Register werden wie bei normaler Exception verändert.
|
||||
TodO: Bei Soft-reset (laut Buch) KUc=0, IEc=0 und BEV=1 initialisieren
|
||||
|
||||
- Uncached write: Geht wie bei cached-write in den Write-Buffer. Folge: Mögliche lange Latenz bis uncached memory-mapped I/O tatsächlich geschieben wird.
|
||||
Könnte bei IRQ acknowledging Probleme bereiten (z.b. mehrfaches (unötiges) anspringen der ISR, obwohl IRQ schon acknowleded wurde).
|
||||
Work-around: Nach schreiben von memory-mapped I/O, gleiche Adresse zurücklesen (lesen wartet bis write-buffer leer).
|
||||
|
||||
2010-01-09
|
||||
- COP dependency einführen => Pipeline stall, wenn COP Daten nicht verfügbar
|
||||
2008-10-26
|
||||
- Area-Optimierung: DIV und MUL verwenden gleiche Ressourcen
|
||||
- Area-Optimierung: MUL32x32 primitive für Virtex-4
|
||||
- shifter: log shifter besser als built-in sll, srl, sra? Nein (2008-10-27)
|
||||
- External COP 1..3 interface
|
||||
- FPU (COP1)
|
||||
- MMU
|
||||
|
||||
2008-10-27
|
||||
- Area vs. speed : Pipeline-stall statt forwarding
|
||||
- Caches: - Lock-up free cache (refill critical word first then un-lock CPU) (geringer Effekt, zu kompliziert => geringere Zuverlässigkeit)
|
||||
- 1,2,4-way assoziative
|
||||
- 2nd-Level cache in System
|
||||
- Write-back policy
|
||||
|
||||
2008-11-15
|
||||
- Bus exceptions IBE DBE (BUI/Cache restart notwendig)
|
||||
|
||||
2009-03-18
|
||||
- cache line sizes von 1 word (4 bytes) gibt NULL-vector. Fehler in Berechnung der inedx_widths
|
||||
|
||||
2009-8-8
|
||||
- Soft-Reset. Ähnlich wie Exception (Reset/NMI). Speicherung von EPC (done)
|
||||
- CP_COND
|
||||
|
||||
2009-10-17
|
||||
- Soft-reset implemetiert. Register werden wie bei normaler Exception verändert.
|
||||
TodO: Bei Soft-reset (laut Buch) KUc=0, IEc=0 und BEV=1 initialisieren
|
||||
|
||||
- Uncached write: Geht wie bei cached-write in den Write-Buffer. Folge: Mögliche lange Latenz bis uncached memory-mapped I/O tatsächlich geschieben wird.
|
||||
Könnte bei IRQ acknowledging Probleme bereiten (z.b. mehrfaches (unötiges) anspringen der ISR, obwohl IRQ schon acknowleded wurde).
|
||||
Work-around: Nach schreiben von memory-mapped I/O, gleiche Adresse zurücklesen (lesen wartet bis write-buffer leer).
|
||||
|
||||
2010-01-09
|
||||
- COP dependency einführen => Pipeline stall, wenn COP Daten nicht verfügbar
|
||||
|
||||
213-08-25
|
||||
- TLB exception in EX-stage einbauen
|
||||
- Cache dout und ready um logic-level reduzieren
|
||||
- cam_ram_addr_rd um logic-level reduzieren
|
||||
|
||||
@@ -1,59 +1,74 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
|
||||
add wave -noupdate -divider J-BUS
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/ack_i
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/srdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/mdat_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/addr_o
|
||||
add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/sel_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/we_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/stb_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/mrdy_o
|
||||
add wave -noupdate -divider Busmaster
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/clk_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_finished
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_en
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/inst_uut/cmd_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/din
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/din_rdy
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/din_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/dout
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_vld
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_re
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cycle_busy
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_en
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_read_en
|
||||
add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/read_cnt
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o
|
||||
add wave -noupdate -divider RAM
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
|
||||
add wave -noupdate -format Literal /tb_busmaster_async/state
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/read_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/ram64
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {31500000 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {42 us}
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
|
||||
add wave -noupdate -divider J-BUS
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/ack_i
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/srdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/mdat_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/addr_o
|
||||
add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/sel_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/we_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/stb_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/mrdy_o
|
||||
add wave -noupdate -divider Busmaster
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/clk_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
|
||||
add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/read_cnt
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write
|
||||
add wave -noupdate -format Literal -expand /tb_busmaster_async/inst_uut/debug
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_finished
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_en
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/inst_uut/cmd_in
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_fifo_re
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/read_fifo_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/din
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/din_rdy
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/din_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/dout
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_vld
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_re
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cycle_busy
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cycle_active
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_en
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_read_en
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_fifo_we
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_fifo_full
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/read_fifo_re
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/read_fifo_full
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/read_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write_fifo_re
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write_fifo_we
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write_fifo_full
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/write_fifo_empty
|
||||
add wave -noupdate -divider RAM
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
|
||||
add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
|
||||
add wave -noupdate -format Literal /tb_busmaster_async/state
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/read_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/ram64
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {8639241 ps}
|
||||
|
||||
+277
-277
@@ -1,277 +1,277 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.2 2013-08-04 17:58:37 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity busmaster_async is
|
||||
Generic
|
||||
(
|
||||
DATA_WIDTH : natural := 32;
|
||||
FIFO_DEPTH : natural := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
cmd_cycle_finished : out std_logic;
|
||||
cmd_cycle_en : in std_logic;
|
||||
cmd_rdy : out std_logic;
|
||||
cmd_we : in std_logic;
|
||||
|
||||
cmd_in : in bm_cmd_t;
|
||||
|
||||
din : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
din_rdy : out std_logic;
|
||||
din_we : in std_logic;
|
||||
|
||||
dout : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
dout_vld : out std_logic;
|
||||
dout_re : in std_logic;
|
||||
|
||||
-- J-BUS signals
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in std_logic;
|
||||
SRDY_I : in std_logic;
|
||||
MDAT_I : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
MDAT_O : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0);
|
||||
WE_O : out std_logic;
|
||||
CYC_O : out std_logic;
|
||||
STB_O : out std_logic;
|
||||
MRDY_O : out std_logic
|
||||
);
|
||||
end busmaster_async;
|
||||
|
||||
architecture Behavioral of busmaster_async is
|
||||
|
||||
-- Bus Command FIFO
|
||||
signal cmd_fifo_din : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_dout : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_re : std_logic;
|
||||
signal cmd_fifo_we : std_logic;
|
||||
signal cmd_fifo_full : std_logic;
|
||||
signal cmd_fifo_empty : std_logic;
|
||||
|
||||
-- Bus Read FIFO
|
||||
signal read_fifo_re : std_logic;
|
||||
signal read_fifo_we : std_logic;
|
||||
signal read_fifo_full : std_logic;
|
||||
signal read_fifo_empty : std_logic;
|
||||
signal write_fifo_re : std_logic;
|
||||
signal write_fifo_we : std_logic;
|
||||
signal write_fifo_full : std_logic;
|
||||
signal write_fifo_empty : std_logic;
|
||||
signal cycle_busy : std_logic;
|
||||
signal cmd_en : std_logic;
|
||||
signal cmd_read_en : std_logic;
|
||||
signal read_cnt : integer range 0 to 65535;
|
||||
signal write : std_logic;
|
||||
|
||||
signal jbus_cycle_busy : std_logic;
|
||||
|
||||
type jbus_state_t is (init, ready, start, wait_finish, finish1, finish2, finish3);
|
||||
signal jbus_state : jbus_state_t;
|
||||
signal jbus_state_next : jbus_state_t;
|
||||
|
||||
begin
|
||||
|
||||
cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full;
|
||||
cmd_read_en <= cmd_en and not cmd_in.rw;
|
||||
write <= cmd_fifo_dout(32+DATA_WIDTH/8);
|
||||
|
||||
dout_vld <= not read_fifo_empty;
|
||||
MRDY_O <= not read_fifo_full;
|
||||
read_fifo_we <= ACK_I and jbus_cycle_busy;
|
||||
read_fifo_re <= dout_re;
|
||||
ADDR_O <= cmd_fifo_dout(31 downto 0);
|
||||
SEL_O <= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32);
|
||||
WE_O <= write;
|
||||
|
||||
cmd_fifo_din <= cmd_in.rw & cmd_in.sel & cmd_in.addr;
|
||||
|
||||
cmd_rdy <= not cmd_fifo_full;
|
||||
|
||||
cmd_fifo_we <= cmd_en;
|
||||
cmd_fifo_re <= SRDY_I and jbus_cycle_busy;
|
||||
|
||||
din_rdy <= not write_fifo_full;
|
||||
write_fifo_we <= din_we;
|
||||
write_fifo_re <= SRDY_I and jbus_cycle_busy and write and not cmd_fifo_empty;
|
||||
|
||||
CYC_O <= jbus_cycle_busy;
|
||||
STB_O <= not cmd_fifo_empty;
|
||||
|
||||
|
||||
-- J-Bus domain
|
||||
proc_JBUS_to_local_cmd_cycle_finished:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
cmd_cycle_finished <= not jbus_cycle_busy;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_JBUS_cycle:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
jbus_cycle_busy <= cycle_busy;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_bus_read_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
read_cnt <= 0;
|
||||
elsif cmd_read_en = '1' and read_fifo_empty = '1' then
|
||||
read_cnt <= read_cnt + 1;
|
||||
elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then
|
||||
read_cnt <= read_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
jbus_state_fsm_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
jbus_state <= init;
|
||||
else
|
||||
jbus_state <= jbus_state_next;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
jbus_state_fsm:
|
||||
process(jbus_state, cmd_we, cmd_fifo_empty, write_fifo_empty, read_cnt)
|
||||
begin
|
||||
|
||||
cycle_busy <= '0';
|
||||
jbus_state_next <= jbus_state;
|
||||
|
||||
case jbus_state is
|
||||
|
||||
when init =>
|
||||
jbus_state_next <= ready;
|
||||
|
||||
when ready =>
|
||||
if cmd_we = '1' or cmd_fifo_empty = '0' then
|
||||
jbus_state_next <= start;
|
||||
end if;
|
||||
|
||||
when start =>
|
||||
cycle_busy <= '1';
|
||||
if cmd_fifo_empty = '0' then
|
||||
jbus_state_next <= wait_finish;
|
||||
end if;
|
||||
|
||||
when wait_finish =>
|
||||
cycle_busy <= '1';
|
||||
if read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
|
||||
jbus_state_next <= finish1;
|
||||
end if;
|
||||
|
||||
-- Quick and dirty hack
|
||||
-- avoid buscycle to finish even if data available,
|
||||
-- caused by latency of async-FIFO empty flag
|
||||
when finish1 =>
|
||||
jbus_state_next <= finish2;
|
||||
|
||||
when finish2 =>
|
||||
jbus_state_next <= finish3;
|
||||
|
||||
when finish3 =>
|
||||
jbus_state_next <= ready;
|
||||
if cmd_fifo_empty = '0' then
|
||||
jbus_state_next <= wait_finish;
|
||||
end if;
|
||||
-- Quick and dirty hack
|
||||
|
||||
when others =>
|
||||
jbus_state_next <= ready;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Bus READ FIFO
|
||||
inst_BM_READ_FIFO: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_r => clk,
|
||||
clk_w => CLK_I,
|
||||
we => read_fifo_we,
|
||||
re => read_fifo_re,
|
||||
fifo_full => read_fifo_full,
|
||||
fifo_empty => read_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_r => dout,
|
||||
data_w => MDAT_I
|
||||
);
|
||||
|
||||
-- Bus WRITE FIFO
|
||||
inst_BM_WRITE_FIFO: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_r => CLK_I,
|
||||
clk_w => clk,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_r => MDAT_O,
|
||||
data_w => din
|
||||
);
|
||||
|
||||
-- Bus command FIFO
|
||||
inst_BM_CMD_FIFO: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => cmd_fifo_din'length,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_r => CLK_I,
|
||||
clk_w => clk,
|
||||
we => cmd_fifo_we,
|
||||
re => cmd_fifo_re,
|
||||
fifo_full => cmd_fifo_full,
|
||||
fifo_empty => cmd_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_r => cmd_fifo_dout,
|
||||
data_w => cmd_fifo_din
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.2 2013/08/04 17:58:37 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity busmaster_async is
|
||||
Generic
|
||||
(
|
||||
DATA_WIDTH : natural := 32;
|
||||
FIFO_DEPTH : natural := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
cmd_cycle_finished : out std_logic;
|
||||
cmd_cycle_en : in std_logic;
|
||||
cmd_rdy : out std_logic;
|
||||
cmd_we : in std_logic;
|
||||
|
||||
cmd_in : in bm_cmd_t;
|
||||
|
||||
din : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
din_rdy : out std_logic;
|
||||
din_we : in std_logic;
|
||||
|
||||
dout : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
dout_vld : out std_logic;
|
||||
dout_re : in std_logic;
|
||||
|
||||
-- J-BUS signals
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in std_logic;
|
||||
SRDY_I : in std_logic;
|
||||
MDAT_I : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
MDAT_O : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0);
|
||||
WE_O : out std_logic;
|
||||
CYC_O : out std_logic;
|
||||
STB_O : out std_logic;
|
||||
MRDY_O : out std_logic
|
||||
);
|
||||
end busmaster_async;
|
||||
|
||||
architecture Behavioral of busmaster_async is
|
||||
|
||||
-- Bus Command FIFO
|
||||
signal cmd_fifo_din : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_dout : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_re : std_logic;
|
||||
signal cmd_fifo_we : std_logic;
|
||||
signal cmd_fifo_full : std_logic;
|
||||
signal cmd_fifo_empty : std_logic;
|
||||
|
||||
-- Bus Read FIFO
|
||||
signal read_fifo_re : std_logic;
|
||||
signal read_fifo_we : std_logic;
|
||||
signal read_fifo_full : std_logic;
|
||||
signal read_fifo_empty : std_logic;
|
||||
signal write_fifo_re : std_logic;
|
||||
signal write_fifo_we : std_logic;
|
||||
signal write_fifo_full : std_logic;
|
||||
signal write_fifo_empty : std_logic;
|
||||
signal cycle_busy : std_logic;
|
||||
signal cmd_en : std_logic;
|
||||
signal cmd_read_en : std_logic;
|
||||
signal read_cnt : integer range 0 to 65535;
|
||||
signal write : std_logic;
|
||||
|
||||
signal jbus_cycle_busy : std_logic;
|
||||
|
||||
type jbus_state_t is (init, ready, start, wait_finish, finish1, finish2, finish3);
|
||||
signal jbus_state : jbus_state_t;
|
||||
signal jbus_state_next : jbus_state_t;
|
||||
|
||||
begin
|
||||
|
||||
cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full;
|
||||
cmd_read_en <= cmd_en and not cmd_in.rw;
|
||||
write <= cmd_fifo_dout(32+DATA_WIDTH/8);
|
||||
|
||||
dout_vld <= not read_fifo_empty;
|
||||
MRDY_O <= not read_fifo_full;
|
||||
read_fifo_we <= ACK_I and jbus_cycle_busy;
|
||||
read_fifo_re <= dout_re;
|
||||
ADDR_O <= cmd_fifo_dout(31 downto 0);
|
||||
SEL_O <= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32);
|
||||
WE_O <= write;
|
||||
|
||||
cmd_fifo_din <= cmd_in.rw & cmd_in.sel & cmd_in.addr;
|
||||
|
||||
cmd_rdy <= not cmd_fifo_full;
|
||||
|
||||
cmd_fifo_we <= cmd_en;
|
||||
cmd_fifo_re <= SRDY_I and jbus_cycle_busy;
|
||||
|
||||
din_rdy <= not write_fifo_full;
|
||||
write_fifo_we <= din_we;
|
||||
write_fifo_re <= SRDY_I and jbus_cycle_busy and write and not cmd_fifo_empty;
|
||||
|
||||
CYC_O <= jbus_cycle_busy;
|
||||
STB_O <= not cmd_fifo_empty;
|
||||
|
||||
|
||||
-- J-Bus domain
|
||||
proc_JBUS_to_local_cmd_cycle_finished:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
cmd_cycle_finished <= not jbus_cycle_busy;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_JBUS_cycle:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
jbus_cycle_busy <= cycle_busy;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_bus_read_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
read_cnt <= 0;
|
||||
elsif cmd_read_en = '1' and read_fifo_empty = '1' then
|
||||
read_cnt <= read_cnt + 1;
|
||||
elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then
|
||||
read_cnt <= read_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
jbus_state_fsm_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
jbus_state <= init;
|
||||
else
|
||||
jbus_state <= jbus_state_next;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
jbus_state_fsm:
|
||||
process(jbus_state, cmd_we, cmd_fifo_empty, write_fifo_empty, read_cnt)
|
||||
begin
|
||||
|
||||
cycle_busy <= '0';
|
||||
jbus_state_next <= jbus_state;
|
||||
|
||||
case jbus_state is
|
||||
|
||||
when init =>
|
||||
jbus_state_next <= ready;
|
||||
|
||||
when ready =>
|
||||
if cmd_we = '1' or cmd_fifo_empty = '0' then
|
||||
jbus_state_next <= start;
|
||||
end if;
|
||||
|
||||
when start =>
|
||||
cycle_busy <= '1';
|
||||
if cmd_fifo_empty = '0' then
|
||||
jbus_state_next <= wait_finish;
|
||||
end if;
|
||||
|
||||
when wait_finish =>
|
||||
cycle_busy <= '1';
|
||||
if read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
|
||||
jbus_state_next <= finish1;
|
||||
end if;
|
||||
|
||||
-- Quick and dirty hack
|
||||
-- avoid buscycle to finish even if data available,
|
||||
-- caused by latency of async-FIFO empty flag
|
||||
when finish1 =>
|
||||
jbus_state_next <= finish2;
|
||||
|
||||
when finish2 =>
|
||||
jbus_state_next <= finish3;
|
||||
|
||||
when finish3 =>
|
||||
jbus_state_next <= ready;
|
||||
if cmd_fifo_empty = '0' then
|
||||
jbus_state_next <= wait_finish;
|
||||
end if;
|
||||
-- Quick and dirty hack
|
||||
|
||||
when others =>
|
||||
jbus_state_next <= ready;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Bus READ FIFO
|
||||
inst_BM_READ_FIFO: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_r => clk,
|
||||
clk_w => CLK_I,
|
||||
we => read_fifo_we,
|
||||
re => read_fifo_re,
|
||||
fifo_full => read_fifo_full,
|
||||
fifo_empty => read_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_r => dout,
|
||||
data_w => MDAT_I
|
||||
);
|
||||
|
||||
-- Bus WRITE FIFO
|
||||
inst_BM_WRITE_FIFO: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_r => CLK_I,
|
||||
clk_w => clk,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_r => MDAT_O,
|
||||
data_w => din
|
||||
);
|
||||
|
||||
-- Bus command FIFO
|
||||
inst_BM_CMD_FIFO: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => cmd_fifo_din'length,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_r => CLK_I,
|
||||
clk_w => clk,
|
||||
we => cmd_fifo_we,
|
||||
re => cmd_fifo_re,
|
||||
fifo_full => cmd_fifo_full,
|
||||
fifo_empty => cmd_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_r => cmd_fifo_dout,
|
||||
data_w => cmd_fifo_din
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
+216
-216
@@ -1,216 +1,216 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.6 2013-08-03 19:31:19 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity busmaster_sync is
|
||||
Generic
|
||||
(
|
||||
DATA_WIDTH : natural := 32;
|
||||
FIFO_DEPTH : natural := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
cmd_cycle_finished : out std_logic;
|
||||
cmd_cycle_en : in std_logic;
|
||||
cmd_rdy : out std_logic;
|
||||
cmd_we : in std_logic;
|
||||
|
||||
cmd_in : in bm_cmd_t;
|
||||
|
||||
din : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
din_rdy : out std_logic;
|
||||
din_we : in std_logic;
|
||||
|
||||
dout : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
dout_vld : out std_logic;
|
||||
dout_re : in std_logic;
|
||||
|
||||
-- J-BUS signals
|
||||
ACK_I : in std_logic;
|
||||
SRDY_I : in std_logic;
|
||||
MDAT_I : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
MDAT_O : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0);
|
||||
WE_O : out std_logic;
|
||||
CYC_O : out std_logic;
|
||||
STB_O : out std_logic;
|
||||
MRDY_O : out std_logic
|
||||
);
|
||||
end busmaster_sync;
|
||||
|
||||
architecture Behavioral of busmaster_sync is
|
||||
|
||||
-- Bus Command FIFO
|
||||
signal cmd_fifo_din : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_dout : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_re : std_logic;
|
||||
signal cmd_fifo_we : std_logic;
|
||||
signal cmd_fifo_full : std_logic;
|
||||
signal cmd_fifo_empty : std_logic;
|
||||
|
||||
-- Bus Read FIFO
|
||||
signal read_fifo_re : std_logic;
|
||||
signal read_fifo_we : std_logic;
|
||||
signal read_fifo_full : std_logic;
|
||||
signal read_fifo_empty : std_logic;
|
||||
signal write_fifo_re : std_logic;
|
||||
signal write_fifo_we : std_logic;
|
||||
signal write_fifo_full : std_logic;
|
||||
signal write_fifo_empty : std_logic;
|
||||
signal cycle_busy : std_logic;
|
||||
signal cmd_en : std_logic;
|
||||
signal cmd_read_en : std_logic;
|
||||
signal read_cnt : integer range 0 to 65535;
|
||||
signal write : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full;
|
||||
cmd_read_en <= cmd_en and not cmd_in.rw;
|
||||
write <= cmd_fifo_dout(32+DATA_WIDTH/8);
|
||||
|
||||
dout_vld <= not read_fifo_empty;
|
||||
MRDY_O <= not read_fifo_full;
|
||||
read_fifo_we <= ACK_I and cycle_busy;
|
||||
read_fifo_re <= dout_re;
|
||||
ADDR_O <= cmd_fifo_dout(31 downto 0);
|
||||
SEL_O <= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32);
|
||||
WE_O <= write;
|
||||
|
||||
cmd_fifo_din <= cmd_in.rw & cmd_in.sel & cmd_in.addr;
|
||||
|
||||
cmd_rdy <= not cmd_fifo_full;
|
||||
|
||||
cmd_fifo_we <= cmd_en;
|
||||
cmd_fifo_re <= SRDY_I and cycle_busy;
|
||||
|
||||
din_rdy <= not write_fifo_full;
|
||||
write_fifo_we <= din_we;
|
||||
write_fifo_re <= SRDY_I and cycle_busy and write and not cmd_fifo_empty;
|
||||
|
||||
STB_O <= not cmd_fifo_empty;
|
||||
CYC_O <= cycle_busy;
|
||||
cmd_cycle_finished <= not cycle_busy;
|
||||
|
||||
-- proc_bus_read_counter:
|
||||
-- process(clk)
|
||||
-- begin
|
||||
-- if rising_edge(clk) then
|
||||
-- if rst = '1' then
|
||||
-- read_cnt <= 0;
|
||||
-- elsif cmd_read_en = '1' and read_fifo_we = '0' then
|
||||
-- read_cnt <= read_cnt + 1;
|
||||
-- elsif cmd_read_en = '0' and read_fifo_we = '1' then
|
||||
-- read_cnt <= read_cnt - 1;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
proc_bus_read_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
read_cnt <= 0;
|
||||
elsif cmd_read_en = '1' and read_fifo_empty = '1' then
|
||||
read_cnt <= read_cnt + 1;
|
||||
elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then
|
||||
read_cnt <= read_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_cycle_busy:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
cycle_busy <= '0';
|
||||
elsif cmd_cycle_en = '1' then
|
||||
if cmd_we = '1' then
|
||||
cycle_busy <= '1';
|
||||
end if;
|
||||
elsif read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
|
||||
cycle_busy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Bus READ FIFO
|
||||
inst_BM_READ_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => read_fifo_we,
|
||||
re => read_fifo_re,
|
||||
fifo_full => read_fifo_full,
|
||||
fifo_empty => read_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => MDAT_I,
|
||||
data_r => dout
|
||||
);
|
||||
|
||||
-- Bus WRITE FIFO
|
||||
inst_BM_WRITE_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => din,
|
||||
data_r => MDAT_O
|
||||
);
|
||||
|
||||
-- Bus command FIFO
|
||||
inst_BM_CMD_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => cmd_fifo_din'length,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => cmd_fifo_we,
|
||||
re => cmd_fifo_re,
|
||||
fifo_full => cmd_fifo_full,
|
||||
fifo_empty => cmd_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => cmd_fifo_din,
|
||||
data_r => cmd_fifo_dout
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.6 2013/08/03 19:31:19 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity busmaster_sync is
|
||||
Generic
|
||||
(
|
||||
DATA_WIDTH : natural := 32;
|
||||
FIFO_DEPTH : natural := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
cmd_cycle_finished : out std_logic;
|
||||
cmd_cycle_en : in std_logic;
|
||||
cmd_rdy : out std_logic;
|
||||
cmd_we : in std_logic;
|
||||
|
||||
cmd_in : in bm_cmd_t;
|
||||
|
||||
din : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
din_rdy : out std_logic;
|
||||
din_we : in std_logic;
|
||||
|
||||
dout : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
dout_vld : out std_logic;
|
||||
dout_re : in std_logic;
|
||||
|
||||
-- J-BUS signals
|
||||
ACK_I : in std_logic;
|
||||
SRDY_I : in std_logic;
|
||||
MDAT_I : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
MDAT_O : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0);
|
||||
WE_O : out std_logic;
|
||||
CYC_O : out std_logic;
|
||||
STB_O : out std_logic;
|
||||
MRDY_O : out std_logic
|
||||
);
|
||||
end busmaster_sync;
|
||||
|
||||
architecture Behavioral of busmaster_sync is
|
||||
|
||||
-- Bus Command FIFO
|
||||
signal cmd_fifo_din : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_dout : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal cmd_fifo_re : std_logic;
|
||||
signal cmd_fifo_we : std_logic;
|
||||
signal cmd_fifo_full : std_logic;
|
||||
signal cmd_fifo_empty : std_logic;
|
||||
|
||||
-- Bus Read FIFO
|
||||
signal read_fifo_re : std_logic;
|
||||
signal read_fifo_we : std_logic;
|
||||
signal read_fifo_full : std_logic;
|
||||
signal read_fifo_empty : std_logic;
|
||||
signal write_fifo_re : std_logic;
|
||||
signal write_fifo_we : std_logic;
|
||||
signal write_fifo_full : std_logic;
|
||||
signal write_fifo_empty : std_logic;
|
||||
signal cycle_busy : std_logic;
|
||||
signal cmd_en : std_logic;
|
||||
signal cmd_read_en : std_logic;
|
||||
signal read_cnt : integer range 0 to 65535;
|
||||
signal write : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full;
|
||||
cmd_read_en <= cmd_en and not cmd_in.rw;
|
||||
write <= cmd_fifo_dout(32+DATA_WIDTH/8);
|
||||
|
||||
dout_vld <= not read_fifo_empty;
|
||||
MRDY_O <= not read_fifo_full;
|
||||
read_fifo_we <= ACK_I and cycle_busy;
|
||||
read_fifo_re <= dout_re;
|
||||
ADDR_O <= cmd_fifo_dout(31 downto 0);
|
||||
SEL_O <= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32);
|
||||
WE_O <= write;
|
||||
|
||||
cmd_fifo_din <= cmd_in.rw & cmd_in.sel & cmd_in.addr;
|
||||
|
||||
cmd_rdy <= not cmd_fifo_full;
|
||||
|
||||
cmd_fifo_we <= cmd_en;
|
||||
cmd_fifo_re <= SRDY_I and cycle_busy;
|
||||
|
||||
din_rdy <= not write_fifo_full;
|
||||
write_fifo_we <= din_we;
|
||||
write_fifo_re <= SRDY_I and cycle_busy and write and not cmd_fifo_empty;
|
||||
|
||||
STB_O <= not cmd_fifo_empty;
|
||||
CYC_O <= cycle_busy;
|
||||
cmd_cycle_finished <= not cycle_busy;
|
||||
|
||||
-- proc_bus_read_counter:
|
||||
-- process(clk)
|
||||
-- begin
|
||||
-- if rising_edge(clk) then
|
||||
-- if rst = '1' then
|
||||
-- read_cnt <= 0;
|
||||
-- elsif cmd_read_en = '1' and read_fifo_we = '0' then
|
||||
-- read_cnt <= read_cnt + 1;
|
||||
-- elsif cmd_read_en = '0' and read_fifo_we = '1' then
|
||||
-- read_cnt <= read_cnt - 1;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
proc_bus_read_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
read_cnt <= 0;
|
||||
elsif cmd_read_en = '1' and read_fifo_empty = '1' then
|
||||
read_cnt <= read_cnt + 1;
|
||||
elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then
|
||||
read_cnt <= read_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_cycle_busy:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
cycle_busy <= '0';
|
||||
elsif cmd_cycle_en = '1' then
|
||||
if cmd_we = '1' then
|
||||
cycle_busy <= '1';
|
||||
end if;
|
||||
elsif read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
|
||||
cycle_busy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Bus READ FIFO
|
||||
inst_BM_READ_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => read_fifo_we,
|
||||
re => read_fifo_re,
|
||||
fifo_full => read_fifo_full,
|
||||
fifo_empty => read_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => MDAT_I,
|
||||
data_r => dout
|
||||
);
|
||||
|
||||
-- Bus WRITE FIFO
|
||||
inst_BM_WRITE_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => din,
|
||||
data_r => MDAT_O
|
||||
);
|
||||
|
||||
-- Bus command FIFO
|
||||
inst_BM_CMD_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => cmd_fifo_din'length,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => cmd_fifo_we,
|
||||
re => cmd_fifo_re,
|
||||
fifo_full => cmd_fifo_full,
|
||||
fifo_empty => cmd_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => cmd_fifo_din,
|
||||
data_r => cmd_fifo_dout
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,31 +1,31 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_types.vhd,v 1.2 2013-05-27 11:17:51 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
|
||||
package busmaster_types is
|
||||
|
||||
-- Constants
|
||||
|
||||
-- Types
|
||||
|
||||
type bm_cmd_t is
|
||||
record
|
||||
addr : unsigned(31 downto 0);
|
||||
sel : unsigned(3 downto 0);
|
||||
rw : std_logic;
|
||||
end record;
|
||||
|
||||
end busmaster_types;
|
||||
|
||||
|
||||
package body busmaster_types is
|
||||
|
||||
|
||||
end busmaster_types;
|
||||
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/busmaster_types.vhd,v 1.2 2013/05/27 11:17:51 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
|
||||
package busmaster_types is
|
||||
|
||||
-- Constants
|
||||
|
||||
-- Types
|
||||
|
||||
type bm_cmd_t is
|
||||
record
|
||||
addr : unsigned(31 downto 0);
|
||||
sel : unsigned(3 downto 0);
|
||||
rw : std_logic;
|
||||
end record;
|
||||
|
||||
end busmaster_types;
|
||||
|
||||
|
||||
package body busmaster_types is
|
||||
|
||||
|
||||
end busmaster_types;
|
||||
|
||||
|
||||
|
||||
+230
-229
@@ -1,229 +1,230 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/dmac.vhd,v 1.2 2013-05-28 11:23:15 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity dmac is
|
||||
Generic
|
||||
(
|
||||
DATA_WIDTH : natural := 32;
|
||||
XFER_CHUNK_SIZE : natural := 512
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
master_req : out std_logic;
|
||||
master_gnt : in std_logic;
|
||||
|
||||
dma_start : out std_logic;
|
||||
dma_active : out std_logic;
|
||||
dma_end : out std_logic;
|
||||
|
||||
req_rdy : out std_logic;
|
||||
req_en : in std_logic;
|
||||
req_rw : in std_logic;
|
||||
req_addr_start : in unsigned(31 downto 0);
|
||||
req_num_xfers : in unsigned(31 downto 0);
|
||||
req_addr_auto_inc : in std_logic;
|
||||
|
||||
req_complete : out std_logic;
|
||||
req_complete_ack : in std_logic;
|
||||
|
||||
-- busmaster control
|
||||
bus_cyc_complete : in std_logic;
|
||||
bus_cmd_rdy : in std_logic;
|
||||
bus_cmd_we : out std_logic;
|
||||
bus_cmd_cycle_en : out std_logic;
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_out : out bm_cmd_t
|
||||
);
|
||||
end dmac;
|
||||
|
||||
architecture Behavioral of dmac is
|
||||
|
||||
signal start_en : std_logic;
|
||||
signal finish_en : std_logic;
|
||||
signal complete : std_logic;
|
||||
signal addr_inc_en : std_logic;
|
||||
signal addr : unsigned(31 downto 0);
|
||||
signal rw : std_logic;
|
||||
|
||||
signal req_count_en : std_logic;
|
||||
signal req_count : unsigned(31 downto 0);
|
||||
signal req_count_next : unsigned(32 downto 0);
|
||||
signal req_count_rdy : std_logic;
|
||||
|
||||
signal chunk_count_rst : std_logic;
|
||||
signal chunk_count_en : std_logic;
|
||||
signal chunk_count : unsigned(31 downto 0);
|
||||
signal chunk_count_next : unsigned(32 downto 0);
|
||||
signal chunk_count_rdy : std_logic;
|
||||
|
||||
type state_t is (INIT, READY, START, SETUP, XFER, FINISH, DONE);
|
||||
signal s, sn : state_t;
|
||||
|
||||
begin
|
||||
|
||||
bus_cmd_out.addr <= addr;
|
||||
bus_cmd_out.sel <= (others => '1');
|
||||
bus_cmd_out.rw <= rw;
|
||||
req_complete <= complete;
|
||||
|
||||
state_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
s <= INIT;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
state:
|
||||
process(s, req_en, master_gnt, req_count_rdy, chunk_count_rdy, bus_cyc_complete, bus_cmd_rdy)
|
||||
begin
|
||||
|
||||
bus_cmd_cycle_en <= '0';
|
||||
bus_cmd_we <= '0';
|
||||
start_en <= '0';
|
||||
finish_en <= '0';
|
||||
req_count_en <= '0';
|
||||
req_rdy <= '0';
|
||||
chunk_count_rst <= '0';
|
||||
chunk_count_en <= '0';
|
||||
master_req <= '0';
|
||||
dma_start <= '0';
|
||||
dma_active <= '0';
|
||||
dma_end <= '0';
|
||||
|
||||
sn <= s;
|
||||
case s is
|
||||
when INIT =>
|
||||
sn <= READY;
|
||||
|
||||
when READY =>
|
||||
req_rdy <= '1';
|
||||
if req_en = '1' then
|
||||
start_en <= '1';
|
||||
sn <= SETUP;
|
||||
end if;
|
||||
|
||||
when SETUP =>
|
||||
dma_start <= '1';
|
||||
sn <= START;
|
||||
|
||||
when START =>
|
||||
master_req <= '1';
|
||||
chunk_count_rst <= '1';
|
||||
if req_count_rdy = '1' then
|
||||
sn <= READY;
|
||||
elsif master_gnt = '1' and bus_cyc_complete = '1' then
|
||||
sn <= XFER;
|
||||
end if;
|
||||
|
||||
when XFER =>
|
||||
dma_active <= '1';
|
||||
master_req <= '1';
|
||||
bus_cmd_we <= '1';
|
||||
bus_cmd_cycle_en <= '1';
|
||||
req_count_en <= bus_cmd_rdy;
|
||||
chunk_count_en <= bus_cmd_rdy;
|
||||
if req_count_rdy = '1' then
|
||||
sn <= FINISH;
|
||||
elsif chunk_count_rdy = '1' then
|
||||
sn <= START;
|
||||
end if;
|
||||
|
||||
when FINISH =>
|
||||
master_req <= '1';
|
||||
if bus_cyc_complete = '1' then
|
||||
sn <= DONE;
|
||||
finish_en <= '1';
|
||||
end if;
|
||||
|
||||
when DONE =>
|
||||
dma_end <= '1';
|
||||
sn <= READY;
|
||||
|
||||
when others =>
|
||||
sn <= READY;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
addr_gen:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' then
|
||||
rw <= req_rw;
|
||||
addr <= req_addr_start;
|
||||
addr_inc_en <= req_addr_auto_inc;
|
||||
elsif req_count_en = '1' and addr_inc_en = '1' then
|
||||
addr <= addr + DATA_WIDTH/8;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
req_count_next <= ('0' & req_num_xfers) - 1 when start_en = '1' else ('0' & req_count) - 1;
|
||||
req_count_rdy <= req_count_next(32);
|
||||
|
||||
req_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' then
|
||||
req_count <= req_count_next(31 downto 0);
|
||||
elsif req_count_en = '1' then
|
||||
if req_count_rdy = '0' then
|
||||
req_count <= req_count_next(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
chunk_count_next <= to_unsigned(XFER_CHUNK_SIZE, 33) - 1 when chunk_count_rst = '1' else ('0' & chunk_count) - 1;
|
||||
chunk_count_rdy <= chunk_count_next(32);
|
||||
|
||||
chunk_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if chunk_count_rst = '1' then
|
||||
chunk_count <= chunk_count_next(31 downto 0);
|
||||
elsif chunk_count_en = '1' then
|
||||
if chunk_count_rdy = '0' then
|
||||
chunk_count <= chunk_count_next(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
complete_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' or rst = '1' then
|
||||
complete <= '0';
|
||||
elsif complete = '0' then
|
||||
if finish_en = '1' then
|
||||
complete <= '1';
|
||||
elsif req_complete_ack = '1' then
|
||||
complete <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/dmac.vhd,v 1.2 2013/05/28 11:23:15 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity dmac is
|
||||
Generic
|
||||
(
|
||||
DATA_WIDTH : natural := 32;
|
||||
XFER_CHUNK_SIZE : natural := 512
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
master_req : out std_logic;
|
||||
master_gnt : in std_logic;
|
||||
|
||||
dma_start : out std_logic;
|
||||
dma_active : out std_logic;
|
||||
dma_end : out std_logic;
|
||||
|
||||
req_rdy : out std_logic;
|
||||
req_en : in std_logic;
|
||||
req_rw : in std_logic;
|
||||
req_addr_start : in unsigned(31 downto 0);
|
||||
req_num_xfers : in unsigned(31 downto 0);
|
||||
req_addr_auto_inc : in std_logic;
|
||||
|
||||
req_complete : out std_logic;
|
||||
req_complete_ack : in std_logic;
|
||||
|
||||
-- busmaster control
|
||||
bus_cyc_complete : in std_logic;
|
||||
bus_cmd_rdy : in std_logic;
|
||||
bus_cmd_we : out std_logic;
|
||||
bus_cmd_cycle_en : out std_logic;
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_out : out bm_cmd_t
|
||||
);
|
||||
end dmac;
|
||||
|
||||
architecture Behavioral of dmac is
|
||||
|
||||
signal start_en : std_logic;
|
||||
signal finish_en : std_logic;
|
||||
signal complete : std_logic;
|
||||
signal addr_inc_en : std_logic;
|
||||
signal addr : unsigned(31 downto 0);
|
||||
signal rw : std_logic;
|
||||
|
||||
signal req_count_en : std_logic;
|
||||
signal req_count : unsigned(31 downto 0);
|
||||
signal req_count_next : unsigned(32 downto 0);
|
||||
signal req_count_rdy : std_logic;
|
||||
|
||||
signal chunk_count_rst : std_logic;
|
||||
signal chunk_count_en : std_logic;
|
||||
signal chunk_count : unsigned(31 downto 0);
|
||||
signal chunk_count_next : unsigned(32 downto 0);
|
||||
signal chunk_count_rdy : std_logic;
|
||||
|
||||
type state_t is (INIT, READY, START, SETUP, XFER, FINISH, DONE);
|
||||
signal s, sn : state_t;
|
||||
|
||||
begin
|
||||
|
||||
bus_cmd_out.addr <= addr;
|
||||
bus_cmd_out.sel <= (others => '1');
|
||||
bus_cmd_out.rw <= rw;
|
||||
req_complete <= complete;
|
||||
|
||||
state_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
s <= INIT;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
state:
|
||||
process(s, req_en, master_gnt, req_count_rdy, chunk_count_rdy, bus_cyc_complete, bus_cmd_rdy)
|
||||
begin
|
||||
|
||||
bus_cmd_cycle_en <= '0';
|
||||
bus_cmd_we <= '0';
|
||||
start_en <= '0';
|
||||
finish_en <= '0';
|
||||
req_count_en <= '0';
|
||||
req_rdy <= '0';
|
||||
chunk_count_rst <= '0';
|
||||
chunk_count_en <= '0';
|
||||
master_req <= '0';
|
||||
dma_start <= '0';
|
||||
dma_active <= '0';
|
||||
dma_end <= '0';
|
||||
|
||||
sn <= s;
|
||||
case s is
|
||||
when INIT =>
|
||||
sn <= READY;
|
||||
|
||||
when READY =>
|
||||
req_rdy <= '1';
|
||||
if req_en = '1' then
|
||||
start_en <= '1';
|
||||
sn <= SETUP;
|
||||
end if;
|
||||
|
||||
when SETUP =>
|
||||
dma_start <= '1';
|
||||
sn <= START;
|
||||
|
||||
when START =>
|
||||
master_req <= '1';
|
||||
chunk_count_rst <= '1';
|
||||
if req_count_rdy = '1' then
|
||||
sn <= READY;
|
||||
elsif master_gnt = '1' and bus_cyc_complete = '1' then
|
||||
sn <= XFER;
|
||||
end if;
|
||||
|
||||
when XFER =>
|
||||
dma_active <= '1';
|
||||
master_req <= '1';
|
||||
bus_cmd_we <= '1';
|
||||
bus_cmd_cycle_en <= '1';
|
||||
req_count_en <= bus_cmd_rdy;
|
||||
chunk_count_en <= bus_cmd_rdy;
|
||||
if req_count_rdy = '1' then
|
||||
sn <= FINISH;
|
||||
elsif chunk_count_rdy = '1' then
|
||||
sn <= START;
|
||||
end if;
|
||||
|
||||
when FINISH =>
|
||||
master_req <= '1';
|
||||
dma_end <= '1';
|
||||
sn <= DONE;
|
||||
|
||||
when DONE =>
|
||||
master_req <= '1';
|
||||
if bus_cyc_complete = '1' then
|
||||
sn <= READY;
|
||||
finish_en <= '1';
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
sn <= READY;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
addr_gen:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' then
|
||||
rw <= req_rw;
|
||||
addr <= req_addr_start;
|
||||
addr_inc_en <= req_addr_auto_inc;
|
||||
elsif req_count_en = '1' and addr_inc_en = '1' then
|
||||
addr <= addr + DATA_WIDTH/8;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
req_count_next <= ('0' & req_num_xfers) - 1 when start_en = '1' else ('0' & req_count) - 1;
|
||||
req_count_rdy <= req_count_next(32);
|
||||
|
||||
req_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' then
|
||||
req_count <= req_count_next(31 downto 0);
|
||||
elsif req_count_en = '1' then
|
||||
if req_count_rdy = '0' then
|
||||
req_count <= req_count_next(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
chunk_count_next <= to_unsigned(XFER_CHUNK_SIZE, 33) - 1 when chunk_count_rst = '1' else ('0' & chunk_count) - 1;
|
||||
chunk_count_rdy <= chunk_count_next(32);
|
||||
|
||||
chunk_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if chunk_count_rst = '1' then
|
||||
chunk_count <= chunk_count_next(31 downto 0);
|
||||
elsif chunk_count_en = '1' then
|
||||
if chunk_count_rdy = '0' then
|
||||
chunk_count <= chunk_count_next(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
complete_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' or rst = '1' then
|
||||
complete <= '0';
|
||||
elsif complete = '0' then
|
||||
if finish_en = '1' then
|
||||
complete <= '1';
|
||||
elsif req_complete_ack = '1' then
|
||||
complete <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
+451
-451
@@ -1,451 +1,451 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_async.vhd,v 1.1 2013-07-21 09:21:30 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY tb_busmaster_async IS
|
||||
END tb_busmaster_async;
|
||||
|
||||
ARCHITECTURE behavior OF tb_busmaster_async IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant JBUS_CLK_PERIOD : time := 20 ns;
|
||||
signal clk : std_logic := '1';
|
||||
signal rst : std_logic := '1';
|
||||
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
|
||||
-- Master
|
||||
signal INT_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-');
|
||||
signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-');
|
||||
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
signal cmd_cycle_finished : std_logic;
|
||||
signal cmd_cycle_en : std_logic := '0';
|
||||
signal cmd_rdy : std_logic;
|
||||
signal cmd_we : std_logic := '0';
|
||||
|
||||
signal cmd_in : bm_cmd_t;
|
||||
|
||||
signal din : unsigned(31 downto 0) := (others => '-');
|
||||
signal din_rdy : std_logic;
|
||||
signal din_we : std_logic := '0';
|
||||
|
||||
signal dout : unsigned(31 downto 0);
|
||||
signal dout_vld : std_logic;
|
||||
signal dout_re : std_logic := '0';
|
||||
|
||||
signal read_reg : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
|
||||
signal state : state_t := IDLE;
|
||||
|
||||
type ram_t is array (0 to 127) of unsigned(63 downto 0);
|
||||
|
||||
signal ram64 : ram_t :=
|
||||
(
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000"
|
||||
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
MDAT_I <= MDAT_I_64(31 downto 0);
|
||||
MDAT_O_64 <= MDAT_O & MDAT_O;
|
||||
|
||||
inst_uut : entity work.busmaster_async
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
FIFO_DEPTH => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
|
||||
cmd_cycle_finished => cmd_cycle_finished,
|
||||
cmd_cycle_en => cmd_cycle_en,
|
||||
cmd_rdy => cmd_rdy,
|
||||
cmd_we => cmd_we,
|
||||
cmd_in => cmd_in,
|
||||
|
||||
din => din,
|
||||
din_rdy => din_rdy,
|
||||
din_we => din_we,
|
||||
|
||||
dout => dout,
|
||||
dout_vld => dout_vld,
|
||||
dout_re => dout_re,
|
||||
|
||||
-- JBUS Master signals
|
||||
RST_I => RST_O,
|
||||
CLK_I => CLK_O,
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
JBUS_CLK_GEN: process
|
||||
begin
|
||||
wait for JBUS_CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
-- Slave
|
||||
SRDY_I <= CYC_O;
|
||||
|
||||
process(CLK_O)
|
||||
variable res: unsigned(63 downto 0);
|
||||
variable ram_data : unsigned(63 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
else
|
||||
ACK_I <= '0';
|
||||
if (CYC_O and STB_O) = '1' then
|
||||
if WE_O = '0' then
|
||||
ACK_I <= '1';
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
if ADDR_O(2) = '0' then
|
||||
res := ram_data;
|
||||
else
|
||||
res := ram_data(31 downto 0) & ram_data(63 downto 32);
|
||||
end if;
|
||||
elsif MRDY_O = '1' then -- WE=1
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
ram_data := (others => '-');
|
||||
if ADDR_O(2) = '0' then
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
|
||||
end if;
|
||||
else
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if (CYC_O and MRDY_O) = '1' then
|
||||
MDAT_I_64 <= res;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
read_reg <= X"00000000";
|
||||
elsif dout_vld = '1' then
|
||||
read_reg <= dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dout_re <= dout_vld;
|
||||
|
||||
-- Master
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_write_single(addr, sel, data : unsigned) is
|
||||
begin
|
||||
|
||||
din <= data;
|
||||
din_we <= '1';
|
||||
wait until rising_edge(clk) and din_rdy = '1';
|
||||
din_we <= '0';
|
||||
|
||||
cmd_in.rw <= '1';
|
||||
cmd_in.sel <= sel;
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(clk) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_write_single;
|
||||
|
||||
procedure cmd_read_single(addr : unsigned) is
|
||||
begin
|
||||
|
||||
cmd_in.rw <= '0';
|
||||
cmd_in.sel <= (others => '0');
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(clk) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_read_single;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
RST_O <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
state <= IDLE;
|
||||
|
||||
for i in 0 to 9 loop
|
||||
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_ABCD");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_ABCD");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_ABCD");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_ABCD");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_ABCD");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_ABCD");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_ABCD");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_ABCD");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_BEEF");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_BEEF");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_BEEF");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_BEEF");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_BEEF");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_BEEF");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_BEEF");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_BEEF");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_cycle_en <= '0';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_ABCD");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_ABCD");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_ABCD");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_ABCD");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_ABCD");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_ABCD");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_ABCD");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_ABCD");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_BEEF");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_BEEF");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_BEEF");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_BEEF");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_BEEF");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_BEEF");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_BEEF");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_BEEF");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_cycle_en <= '0';
|
||||
|
||||
wait until rising_edge(clk) and cmd_cycle_finished = '1';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
end loop;
|
||||
|
||||
state <= IDLE;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/tb_busmaster_async.vhd,v 1.1 2013/07/21 09:21:30 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY tb_busmaster_async IS
|
||||
END tb_busmaster_async;
|
||||
|
||||
ARCHITECTURE behavior OF tb_busmaster_async IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant JBUS_CLK_PERIOD : time := 20 ns;
|
||||
signal clk : std_logic := '1';
|
||||
signal rst : std_logic := '1';
|
||||
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
|
||||
-- Master
|
||||
signal INT_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-');
|
||||
signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-');
|
||||
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
signal cmd_cycle_finished : std_logic;
|
||||
signal cmd_cycle_en : std_logic := '0';
|
||||
signal cmd_rdy : std_logic;
|
||||
signal cmd_we : std_logic := '0';
|
||||
|
||||
signal cmd_in : bm_cmd_t;
|
||||
|
||||
signal din : unsigned(31 downto 0) := (others => '-');
|
||||
signal din_rdy : std_logic;
|
||||
signal din_we : std_logic := '0';
|
||||
|
||||
signal dout : unsigned(31 downto 0);
|
||||
signal dout_vld : std_logic;
|
||||
signal dout_re : std_logic := '0';
|
||||
|
||||
signal read_reg : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
|
||||
signal state : state_t := IDLE;
|
||||
|
||||
type ram_t is array (0 to 127) of unsigned(63 downto 0);
|
||||
|
||||
signal ram64 : ram_t :=
|
||||
(
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000"
|
||||
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
MDAT_I <= MDAT_I_64(31 downto 0);
|
||||
MDAT_O_64 <= MDAT_O & MDAT_O;
|
||||
|
||||
inst_uut : entity work.busmaster_async
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
FIFO_DEPTH => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
|
||||
cmd_cycle_finished => cmd_cycle_finished,
|
||||
cmd_cycle_en => cmd_cycle_en,
|
||||
cmd_rdy => cmd_rdy,
|
||||
cmd_we => cmd_we,
|
||||
cmd_in => cmd_in,
|
||||
|
||||
din => din,
|
||||
din_rdy => din_rdy,
|
||||
din_we => din_we,
|
||||
|
||||
dout => dout,
|
||||
dout_vld => dout_vld,
|
||||
dout_re => dout_re,
|
||||
|
||||
-- JBUS Master signals
|
||||
RST_I => RST_O,
|
||||
CLK_I => CLK_O,
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
JBUS_CLK_GEN: process
|
||||
begin
|
||||
wait for JBUS_CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
-- Slave
|
||||
SRDY_I <= CYC_O;
|
||||
|
||||
process(CLK_O)
|
||||
variable res: unsigned(63 downto 0);
|
||||
variable ram_data : unsigned(63 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
else
|
||||
ACK_I <= '0';
|
||||
if (CYC_O and STB_O) = '1' then
|
||||
if WE_O = '0' then
|
||||
ACK_I <= '1';
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
if ADDR_O(2) = '0' then
|
||||
res := ram_data;
|
||||
else
|
||||
res := ram_data(31 downto 0) & ram_data(63 downto 32);
|
||||
end if;
|
||||
elsif MRDY_O = '1' then -- WE=1
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
ram_data := (others => '-');
|
||||
if ADDR_O(2) = '0' then
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
|
||||
end if;
|
||||
else
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if (CYC_O and MRDY_O) = '1' then
|
||||
MDAT_I_64 <= res;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
read_reg <= X"00000000";
|
||||
elsif dout_vld = '1' then
|
||||
read_reg <= dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dout_re <= dout_vld;
|
||||
|
||||
-- Master
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_write_single(addr, sel, data : unsigned) is
|
||||
begin
|
||||
|
||||
din <= data;
|
||||
din_we <= '1';
|
||||
wait until rising_edge(clk) and din_rdy = '1';
|
||||
din_we <= '0';
|
||||
|
||||
cmd_in.rw <= '1';
|
||||
cmd_in.sel <= sel;
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(clk) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_write_single;
|
||||
|
||||
procedure cmd_read_single(addr : unsigned) is
|
||||
begin
|
||||
|
||||
cmd_in.rw <= '0';
|
||||
cmd_in.sel <= (others => '0');
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(clk) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_read_single;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
RST_O <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
state <= IDLE;
|
||||
|
||||
for i in 0 to 9 loop
|
||||
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_ABCD");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_ABCD");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_ABCD");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_ABCD");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_ABCD");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_ABCD");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_ABCD");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_ABCD");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_BEEF");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_BEEF");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_BEEF");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_BEEF");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_BEEF");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_BEEF");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_BEEF");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_BEEF");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_cycle_en <= '0';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_ABCD");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_ABCD");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_ABCD");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_ABCD");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_ABCD");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_ABCD");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_ABCD");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_ABCD");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_BEEF");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_BEEF");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_BEEF");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_BEEF");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_BEEF");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_BEEF");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_BEEF");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_BEEF");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_cycle_en <= '0';
|
||||
|
||||
wait until rising_edge(clk) and cmd_cycle_finished = '1';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
end loop;
|
||||
|
||||
state <= IDLE;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
|
||||
+446
-446
@@ -1,446 +1,446 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.3 2013-07-21 09:10:13 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY tb_busmaster_sync IS
|
||||
END tb_busmaster_sync;
|
||||
|
||||
ARCHITECTURE behavior OF tb_busmaster_sync IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
|
||||
-- Master
|
||||
signal INT_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-');
|
||||
signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-');
|
||||
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
signal cmd_cycle_finished : std_logic;
|
||||
signal cmd_cycle_en : std_logic := '0';
|
||||
signal cmd_rdy : std_logic;
|
||||
signal cmd_we : std_logic := '0';
|
||||
|
||||
signal cmd_in : bm_cmd_t;
|
||||
|
||||
signal din : unsigned(31 downto 0) := (others => '-');
|
||||
signal din_rdy : std_logic;
|
||||
signal din_we : std_logic := '0';
|
||||
|
||||
signal dout : unsigned(31 downto 0);
|
||||
signal dout_vld : std_logic;
|
||||
signal dout_re : std_logic := '0';
|
||||
|
||||
signal rdy : std_logic := '0';
|
||||
signal read_reg : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
|
||||
signal state : state_t := IDLE;
|
||||
|
||||
type ram_t is array (0 to 127) of unsigned(63 downto 0);
|
||||
|
||||
signal ram64 : ram_t :=
|
||||
(
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000"
|
||||
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
MDAT_I <= MDAT_I_64(31 downto 0);
|
||||
MDAT_O_64 <= MDAT_O & MDAT_O;
|
||||
|
||||
inst_uut : entity work.busmaster_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
FIFO_DEPTH => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST_O,
|
||||
clk => CLK_O,
|
||||
|
||||
cmd_cycle_finished => cmd_cycle_finished,
|
||||
cmd_cycle_en => cmd_cycle_en,
|
||||
cmd_rdy => cmd_rdy,
|
||||
cmd_we => cmd_we,
|
||||
cmd_in => cmd_in,
|
||||
|
||||
din => din,
|
||||
din_rdy => din_rdy,
|
||||
din_we => din_we,
|
||||
|
||||
dout => dout,
|
||||
dout_vld => dout_vld,
|
||||
dout_re => dout_re,
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
rdy_GEN: process
|
||||
begin
|
||||
-- wait for 3*CLK_PERIOD/2;
|
||||
wait until rising_edge(CLK_O);
|
||||
rdy <= not rdy;
|
||||
end process;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
-- Slave
|
||||
SRDY_I <= CYC_O;
|
||||
|
||||
process(CLK_O)
|
||||
variable res: unsigned(63 downto 0);
|
||||
variable ram_data : unsigned(63 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
else
|
||||
ACK_I <= '0';
|
||||
if (CYC_O and STB_O) = '1' then
|
||||
if WE_O = '0' then
|
||||
ACK_I <= '1';
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
if ADDR_O(2) = '0' then
|
||||
res := ram_data;
|
||||
else
|
||||
res := ram_data(31 downto 0) & ram_data(63 downto 32);
|
||||
end if;
|
||||
elsif MRDY_O = '1' then -- WE=1
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
ram_data := (others => '-');
|
||||
if ADDR_O(2) = '0' then
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
|
||||
end if;
|
||||
else
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if (CYC_O and MRDY_O) = '1' then
|
||||
MDAT_I_64 <= res;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(CLK_O)
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
read_reg <= X"00000000";
|
||||
elsif dout_vld = '1' then
|
||||
read_reg <= dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dout_re <= dout_vld;
|
||||
|
||||
-- Master
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_write_single(addr, sel, data : unsigned) is
|
||||
begin
|
||||
|
||||
din <= data;
|
||||
din_we <= '1';
|
||||
wait until rising_edge(CLK_O) and din_rdy = '1';
|
||||
din_we <= '0';
|
||||
|
||||
cmd_in.rw <= '1';
|
||||
cmd_in.sel <= sel;
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(CLK_O) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_write_single;
|
||||
|
||||
procedure cmd_read_single(addr : unsigned) is
|
||||
begin
|
||||
|
||||
cmd_in.rw <= '0';
|
||||
cmd_in.sel <= (others => '0');
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(CLK_O) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_read_single;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
RST_O <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
state <= IDLE;
|
||||
|
||||
for i in 0 to 9 loop
|
||||
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_ABCD");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_ABCD");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_ABCD");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_ABCD");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_ABCD");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_ABCD");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_ABCD");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_ABCD");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_BEEF");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_BEEF");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_BEEF");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_BEEF");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_BEEF");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_BEEF");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_BEEF");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_BEEF");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_cycle_en <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
wait until rising_edge(CLK_O);
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_ABCD");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_ABCD");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_ABCD");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_ABCD");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_ABCD");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_ABCD");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_ABCD");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_ABCD");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_BEEF");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_BEEF");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_BEEF");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_BEEF");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_BEEF");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_BEEF");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_BEEF");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_BEEF");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_cycle_en <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O) and cmd_cycle_finished = '1';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
|
||||
end loop;
|
||||
|
||||
state <= IDLE;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.3 2013/07/21 09:10:13 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY tb_busmaster_sync IS
|
||||
END tb_busmaster_sync;
|
||||
|
||||
ARCHITECTURE behavior OF tb_busmaster_sync IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
|
||||
-- Master
|
||||
signal INT_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-');
|
||||
signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-');
|
||||
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
signal cmd_cycle_finished : std_logic;
|
||||
signal cmd_cycle_en : std_logic := '0';
|
||||
signal cmd_rdy : std_logic;
|
||||
signal cmd_we : std_logic := '0';
|
||||
|
||||
signal cmd_in : bm_cmd_t;
|
||||
|
||||
signal din : unsigned(31 downto 0) := (others => '-');
|
||||
signal din_rdy : std_logic;
|
||||
signal din_we : std_logic := '0';
|
||||
|
||||
signal dout : unsigned(31 downto 0);
|
||||
signal dout_vld : std_logic;
|
||||
signal dout_re : std_logic := '0';
|
||||
|
||||
signal rdy : std_logic := '0';
|
||||
signal read_reg : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
|
||||
signal state : state_t := IDLE;
|
||||
|
||||
type ram_t is array (0 to 127) of unsigned(63 downto 0);
|
||||
|
||||
signal ram64 : ram_t :=
|
||||
(
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000"
|
||||
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
MDAT_I <= MDAT_I_64(31 downto 0);
|
||||
MDAT_O_64 <= MDAT_O & MDAT_O;
|
||||
|
||||
inst_uut : entity work.busmaster_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
FIFO_DEPTH => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST_O,
|
||||
clk => CLK_O,
|
||||
|
||||
cmd_cycle_finished => cmd_cycle_finished,
|
||||
cmd_cycle_en => cmd_cycle_en,
|
||||
cmd_rdy => cmd_rdy,
|
||||
cmd_we => cmd_we,
|
||||
cmd_in => cmd_in,
|
||||
|
||||
din => din,
|
||||
din_rdy => din_rdy,
|
||||
din_we => din_we,
|
||||
|
||||
dout => dout,
|
||||
dout_vld => dout_vld,
|
||||
dout_re => dout_re,
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
rdy_GEN: process
|
||||
begin
|
||||
-- wait for 3*CLK_PERIOD/2;
|
||||
wait until rising_edge(CLK_O);
|
||||
rdy <= not rdy;
|
||||
end process;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
-- Slave
|
||||
SRDY_I <= CYC_O;
|
||||
|
||||
process(CLK_O)
|
||||
variable res: unsigned(63 downto 0);
|
||||
variable ram_data : unsigned(63 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
else
|
||||
ACK_I <= '0';
|
||||
if (CYC_O and STB_O) = '1' then
|
||||
if WE_O = '0' then
|
||||
ACK_I <= '1';
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
if ADDR_O(2) = '0' then
|
||||
res := ram_data;
|
||||
else
|
||||
res := ram_data(31 downto 0) & ram_data(63 downto 32);
|
||||
end if;
|
||||
elsif MRDY_O = '1' then -- WE=1
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
ram_data := (others => '-');
|
||||
if ADDR_O(2) = '0' then
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
|
||||
end if;
|
||||
else
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if (CYC_O and MRDY_O) = '1' then
|
||||
MDAT_I_64 <= res;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(CLK_O)
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
read_reg <= X"00000000";
|
||||
elsif dout_vld = '1' then
|
||||
read_reg <= dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dout_re <= dout_vld;
|
||||
|
||||
-- Master
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_write_single(addr, sel, data : unsigned) is
|
||||
begin
|
||||
|
||||
din <= data;
|
||||
din_we <= '1';
|
||||
wait until rising_edge(CLK_O) and din_rdy = '1';
|
||||
din_we <= '0';
|
||||
|
||||
cmd_in.rw <= '1';
|
||||
cmd_in.sel <= sel;
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(CLK_O) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_write_single;
|
||||
|
||||
procedure cmd_read_single(addr : unsigned) is
|
||||
begin
|
||||
|
||||
cmd_in.rw <= '0';
|
||||
cmd_in.sel <= (others => '0');
|
||||
cmd_in.addr <= addr;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(CLK_O) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_read_single;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
RST_O <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
state <= IDLE;
|
||||
|
||||
for i in 0 to 9 loop
|
||||
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_ABCD");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_ABCD");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_ABCD");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_ABCD");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_ABCD");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_ABCD");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_ABCD");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_ABCD");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_BEEF");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_BEEF");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_BEEF");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_BEEF");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_BEEF");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_BEEF");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_BEEF");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_BEEF");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_cycle_en <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
wait until rising_edge(CLK_O);
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_ABCD");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_ABCD");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_ABCD");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_ABCD");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_ABCD");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_ABCD");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_ABCD");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_ABCD");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_BEEF");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_BEEF");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_BEEF");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_BEEF");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_BEEF");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_BEEF");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_BEEF");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_BEEF");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_cycle_en <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O) and cmd_cycle_finished = '1';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
|
||||
end loop;
|
||||
|
||||
state <= IDLE;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
|
||||
+540
-540
File diff suppressed because it is too large
Load Diff
+86
-86
@@ -1,86 +1,86 @@
|
||||
---- $Id: CHANGES,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
Changes from version 1.16 to version 2002.07
|
||||
============================================
|
||||
|
||||
PCK_FIO is now distributed under the GNU Lesser General Public Licencse
|
||||
instead of the ordinary GPL, to better reflect intended usage.
|
||||
|
||||
Cosmetic changes in source code to correct some typos in the testbench output.
|
||||
A new testbench is also supplied.
|
||||
|
||||
The package now uses IEEE.numeric_std as default.
|
||||
|
||||
URL http://www.easics.com has been made part of address.
|
||||
|
||||
Changed syntax in the PCK_FIO package and its testbench to support VHDL-1993.
|
||||
Because of backwards-incompatibility, it has been necessary to supply
|
||||
different sets of files for 1987 and 1993.
|
||||
|
||||
Split the packages into a separate file for the header and a
|
||||
separate file for the body (in compliance with Easics' guidelines).
|
||||
|
||||
These changes resulted in the files:
|
||||
|
||||
Files for VHDL-1993:
|
||||
--------------------
|
||||
PCK_FIO_1993.vhd : the source code of the header file for the package
|
||||
PCK_FIO_1993_BODY.vhd: the source code of the body of the package
|
||||
TB_PCK_FIO_1993.vhd: the testbench for the package
|
||||
|
||||
Files for VHDL-1987:
|
||||
--------------------
|
||||
PCK_FIO_1987.vhd: the source code of the header file for the package
|
||||
PCK_FIO_1987_BODY.vhd: the source code of the body of the package
|
||||
TB_PCK_FIO_1987.vhd: the testbench for the package
|
||||
|
||||
Updated README and PCK_FIO.html to support these changes.
|
||||
|
||||
Adapted package files to support NUL termination of strings.
|
||||
fo(Arg: string) now prints the string until the first NUL.
|
||||
Several examples of its use are demonstrated in the supplied testbenches.
|
||||
|
||||
Made cosmetic changes to code to improve readability.
|
||||
|
||||
Acknowledgment
|
||||
--------------
|
||||
These changes have been implemented by Peter Geens.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
---- $Id: CHANGES,v 1.1 2008/08/23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
Changes from version 1.16 to version 2002.07
|
||||
============================================
|
||||
|
||||
PCK_FIO is now distributed under the GNU Lesser General Public Licencse
|
||||
instead of the ordinary GPL, to better reflect intended usage.
|
||||
|
||||
Cosmetic changes in source code to correct some typos in the testbench output.
|
||||
A new testbench is also supplied.
|
||||
|
||||
The package now uses IEEE.numeric_std as default.
|
||||
|
||||
URL http://www.easics.com has been made part of address.
|
||||
|
||||
Changed syntax in the PCK_FIO package and its testbench to support VHDL-1993.
|
||||
Because of backwards-incompatibility, it has been necessary to supply
|
||||
different sets of files for 1987 and 1993.
|
||||
|
||||
Split the packages into a separate file for the header and a
|
||||
separate file for the body (in compliance with Easics' guidelines).
|
||||
|
||||
These changes resulted in the files:
|
||||
|
||||
Files for VHDL-1993:
|
||||
--------------------
|
||||
PCK_FIO_1993.vhd : the source code of the header file for the package
|
||||
PCK_FIO_1993_BODY.vhd: the source code of the body of the package
|
||||
TB_PCK_FIO_1993.vhd: the testbench for the package
|
||||
|
||||
Files for VHDL-1987:
|
||||
--------------------
|
||||
PCK_FIO_1987.vhd: the source code of the header file for the package
|
||||
PCK_FIO_1987_BODY.vhd: the source code of the body of the package
|
||||
TB_PCK_FIO_1987.vhd: the testbench for the package
|
||||
|
||||
Updated README and PCK_FIO.html to support these changes.
|
||||
|
||||
Adapted package files to support NUL termination of strings.
|
||||
fo(Arg: string) now prints the string until the first NUL.
|
||||
Several examples of its use are demonstrated in the supplied testbenches.
|
||||
|
||||
Made cosmetic changes to code to improve readability.
|
||||
|
||||
Acknowledgment
|
||||
--------------
|
||||
These changes have been implemented by Peter Geens.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
+339
-339
@@ -1,339 +1,339 @@
|
||||
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
|
||||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<meta name="GENERATOR" content="Mozilla/4.76 [en] (X11; U; Linux 2.4.13 i686) [Netscape]">
|
||||
<title>VHDL package for formatted file output</title>
|
||||
<!-- $Id: PCK_FIO.html,v 1.1 2008-08-23 08:20:28 Jens Exp $ -->
|
||||
</head>
|
||||
<body text="#000000" bgcolor="#FFFFFF" link="#0000EE" vlink="#551A8B" alink="#FF0000">
|
||||
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_name_0"></a>Name</h1>
|
||||
<b>PCK_FIO</b> - VHDL package for formatted file output
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
Contents</h1>
|
||||
<a href="#PCK_FIO_usage_0">Usage</a>
|
||||
<br><a href="#PCK_FIO_file_0">The file output function 'fo'</a>
|
||||
<br><a href="#PCK_FIO_format_0">Format specifiers</a>
|
||||
<br><a href="#PCK_FIO_special_0">Special characters</a>
|
||||
<br><a href="#PCK_FIO_things_0">Things to watch out for</a>
|
||||
<br><a href="#PCK_FIO_methodology_0">Methodology notes</a>
|
||||
<br><a href="#PCK_FIO_parametrization_0">Parametrization</a>
|
||||
<br><a href="#PCK_FIO_test_0">Test bench</a>
|
||||
<br><a href="#PCK_FIO_limitations_0">Known limitations and problems</a>
|
||||
<br><a href="#PCK_FIO_author_0">Author</a>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_usage_0"></a>Usage</h1>
|
||||
PCK_FIO is a VHDL package that defines <tt>fprint, </tt>a function
|
||||
for formatted file output.
|
||||
<p>After installing the package you can call <tt>fprint</tt> as follows:
|
||||
<pre> fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));</pre>
|
||||
where F is the filehandle and L is the line variable.
|
||||
<p>The argument Format is the format string, which consists of ``normal''
|
||||
substrings which are copied verbatim, and format specifiers, starting with
|
||||
<tt>'%'</tt>.
|
||||
A typical format string looks as follows:
|
||||
<pre> "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"</pre>
|
||||
The remaining arguments are the expressions whose results you want to write
|
||||
to the file, embedded in <tt>fo</tt> function calls. There can be 0 to
|
||||
32 of such arguments. The expressions can be of any type for which an <tt>fo</tt>
|
||||
function exists. String expressions can also be called directly.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_file_0"></a>The file output function <tt>'fo'</tt></h1>
|
||||
The <tt>fo</tt> (<u>f</u>ile <u>o</u>utput) functions do the trick. They
|
||||
return a tagged string representation that is meaningful to format specifiers.
|
||||
Here are some examples:
|
||||
<pre> fo (signed'("1100")) returns "S:1100"
|
||||
fo (unsigned'("1100")) returns "U:1100"
|
||||
fo (TRUE) returns "L:T"
|
||||
fo (127) returns "I:127"</pre>
|
||||
The internal behavior of <tt>fo</tt> is irrelevant to the typical user.
|
||||
<br>
|
||||
<pre>The <tt>fo</tt> function is currently overloaded as follows:</pre>
|
||||
|
||||
<pre> function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;</pre>
|
||||
|
||||
<p><br>To support null-terminated strings, the function <tt>fo</tt>(Arg:
|
||||
string) processes <tt>Arg</tt> up to the first <tt>NUL</tt> character,
|
||||
if any. If you want the whole string to be outputted you can just enter
|
||||
the string as a direct argument in <tt>fprint</tt>. See also the
|
||||
examples in the testbench.
|
||||
<pre>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%"></pre>
|
||||
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_format_0"></a>Format specifiers</h1>
|
||||
The general format of a format specifier is:
|
||||
<pre> %[-][n]c</pre>
|
||||
The optional <b>-</b> sign specifies left justified output; default is
|
||||
right justified.
|
||||
<p>The optional number <b>n</b> specifies a field-width. If it is not specified,
|
||||
<tt>fprint</tt>
|
||||
does something reasonable.
|
||||
<p><b>c</b> is the conversion specifier. Currently the following conversion
|
||||
specifiers are supported:
|
||||
<dl COMPACT>
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_r_0"></a><b>r</b></dt>
|
||||
|
||||
<dd>
|
||||
reasonable output format (inspired by Synopsys VSS)</dd>
|
||||
|
||||
<dl COMPACT>Prints the ``most reasonable'' representation e.g. hex for
|
||||
unsigned, signed and other bit-like vectors (not preferred for integers)</dl>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_b_0"></a><b>b</b></dt>
|
||||
|
||||
<dd>
|
||||
bit-oriented output</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_d_0"></a><b>d</b></dt>
|
||||
|
||||
<dd>
|
||||
decimal output</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_s_0"></a><b>s</b></dt>
|
||||
|
||||
<dd>
|
||||
string output (e.g. in combination with 'IMAGE for enum types)</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_q_0"></a><b>q</b></dt>
|
||||
|
||||
<dd>
|
||||
``qualified'' string output (shows internal representation from <tt>fo</tt>)</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO__0"></a><b>{}</b></dt>
|
||||
|
||||
<dd>
|
||||
Iteration operator, used as follows:</dd>
|
||||
|
||||
<dd>
|
||||
<tt>%n{<format-string>}</tt></dd>
|
||||
|
||||
<br>In this case, <b>n</b> is the iteration count and is mandatory. Iteration
|
||||
can be nested.</dl>
|
||||
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_special_0"></a>Special characters</h1>
|
||||
To print a double quote, use <tt>'""'</tt> in the format string (VHDL
|
||||
convention). To print the special characters, <tt>'\'</tt>, and <tt>'%'</tt>,
|
||||
escape them with <tt>'\'</tt>. To prevent <tt>'{'</tt> and <tt>'}'</tt>
|
||||
from being interpreted as opening and closing brackets in iteration strings,
|
||||
escape them with <tt>'\'</tt>.
|
||||
<p>A newline is specified in the format string by <tt>'\n'</tt>.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_things_0"></a>Things to notice</h1>
|
||||
The fprint function expands into VHDL <tt>write</tt> and <tt>writeline</tt>
|
||||
commands. As in plain VHDL, nothing will be written to the output file
|
||||
until a <tt>writeline</tt> is given. Therefore, don't forget to include
|
||||
<tt>'\n'</tt>
|
||||
commands in the format string, or it ``will not work''.
|
||||
<p>The preferred format specifier for integers is, naturally, <b>%d</b>.
|
||||
This calls the VHDL <tt>write</tt> for integers. If you specify a field
|
||||
width that is too small, the field will automatically be expanded. If you
|
||||
use <b>%r</b> for integers, the field is not expanded automatically, which
|
||||
means that some digits are simply thrown away. This may sometimes be useful
|
||||
but it is also dangerous. Look at the test bench output for differences
|
||||
between <b>%d</b> and <b>%r</b> output.
|
||||
<p>When using the <b>%d</b> format specifier, the VHDL constraints for
|
||||
the allowed integer range apply.
|
||||
<p>In VHDL, signed/unsigned types have been standardized only relatively
|
||||
recently, in the package <tt>IEEE.numeric_std</tt>. The lack of a standard
|
||||
has caused (and is causing) portability issues. The most popular non-standard
|
||||
package that defines signed/unsigned is <tt>IEEE.std_logic_arith</tt> from
|
||||
Synopsys. PCK_FIO works with both packages, but refers to the standard
|
||||
package <tt>IEEE.numeric_std</tt> by default. To use <tt>IEEE.std_logic_arith</tt>
|
||||
instead, replace the reference to <tt>IEEE.numeric_std</tt> in the source
|
||||
code. This needs to be done consistently in a design database (e.g.
|
||||
in the PCK_FIO test bench as well).
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_methodology_0"></a>Methodology notes</h1>
|
||||
The obvious application for <tt>fprint</tt> is in test benches, to produce
|
||||
output files that trace the simulation behavior.
|
||||
<p>Another interesting application for <tt>fprint</tt> is to produce info,
|
||||
warning and error messages in your models. As it can take arguments, <tt>fprint</tt>
|
||||
is much better suited for this task than VHDL's <tt>assert</tt> or <tt>report</tt>
|
||||
statements. Actually <tt>fprint</tt> produces its own (few) warning messages.
|
||||
<p>An advanced usage is the generation of test vectors in a specific format.
|
||||
Instead of using the <tt>fo </tt>functions, you can write your own set
|
||||
of functions that return the symbols of a specific test format in a way
|
||||
that is understandable to the <tt>fprint</tt> format specifiers. As an
|
||||
example, when a high output value should be represented using the symbol
|
||||
'H' it suffices to write a conversion function that returns "B:H" and call
|
||||
it in combination with the <b>%b</b> format specifier.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_parametrization_0"></a>Parametrization</h1>
|
||||
Prefix and postfix strings for bit-oriented and hex-oriented output are
|
||||
parameterizable in the packages to accommodate different output styles.
|
||||
The settings in the distribution are such that hex output is indicated
|
||||
by the prefix '0x', while bit output prefix and postfix are empty
|
||||
strings.
|
||||
<p>You can adapt the output style by modifying the following constants
|
||||
in the package header:
|
||||
<p> <tt> -- prefix string for hex output</tt>
|
||||
<br><tt> -- VHDL style: "X"""</tt>
|
||||
<br><tt> -- Verilog style: "h'"</tt>
|
||||
<br><tt> -- C style: "0x"</tt>
|
||||
<br><tt> constant FIO_h_PRE: string := "0x";</tt>
|
||||
<p><tt> -- postfix string for hex output</tt>
|
||||
<br><tt> -- VHDL style: """"</tt>
|
||||
<br><tt> constant FIO_h_POST: string := "";</tt>
|
||||
<p><tt> -- prefix string for bit vector output</tt>
|
||||
<br><tt> -- VHDL style: "B"""</tt>
|
||||
<br><tt> -- Verilog style: "b'"</tt>
|
||||
<br><tt> constant FIO_bv_PRE: string := "";</tt>
|
||||
<p><tt> -- postfix string for bit vector output</tt>
|
||||
<br><tt> -- VHDL style: """"</tt>
|
||||
<br><tt> constant FIO_bv_POST: string := "";</tt>
|
||||
<p><tt> -- prefix string for bit output</tt>
|
||||
<br><tt> -- VHDL style: "'"</tt>
|
||||
<br><tt> -- Verilog style: "b'"</tt>
|
||||
<br><tt> constant FIO_b_PRE: string := "";</tt>
|
||||
<p><tt> -- postfix string for bit output</tt>
|
||||
<br><tt> -- VHDL style: "'"</tt>
|
||||
<br><tt> constant FIO_b_POST: string := "";</tt>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_test_0"></a>Test bench</h1>
|
||||
Included in the distribution are the files <tt>TB_PCK_FIO_1987.vhd and
|
||||
TB_PCK_FIO_1993</tt> with a test bench,depending on the standard you're
|
||||
running, for the PCK_FIO package. The file <tt>PCK_FIO.out.gold </tt>contains
|
||||
the expected output. If you run the test bench it should produce the file
|
||||
<tt>PCK_FIO.out</tt>
|
||||
that should be identical to <tt>PCK_FIO.out.gold</tt>. The source files
|
||||
should be analyzed in a VHDL library <tt>EASICS_PACKAGES</tt>.
|
||||
<p>A good way to understand <tt>fprint</tt> is to inspect the test bench
|
||||
and what it produces.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_limitations_0"></a>Known limitations and problems</h1>
|
||||
This VHDL package is an implementation of a flexible concept. It is likely
|
||||
to be extended and modified in the future. Backward compatibility is not
|
||||
guaranteed. Therefore, it is not recommended to give this package the status
|
||||
of a company wide standard package (or even worse, a VHDL standard package).
|
||||
Rather, it should be linked with a particular project (and it can be regarded
|
||||
as a standard package within that project).
|
||||
<p>PCK_FIO is available in either standard VHDL Std1076-1987 or standard
|
||||
VHDL Std1076-1993. Nevertheless, some simulators/versions have problems
|
||||
with the package. The following is an overview of currently known issues:
|
||||
<br>
|
||||
<center><table BORDER COLS=2 WIDTH="80%" NOSAVE >
|
||||
<caption>PCK_FIO_1987 and various simulators/versions</caption>
|
||||
|
||||
<tr>
|
||||
<th>Simulator</th>
|
||||
|
||||
<th>PCK_FIO_1987</th>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS 3.5 and earlier</td>
|
||||
|
||||
<td>Incorrect (all zero) output in compiled mode</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS 97.01</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS/Scirocco 2000.02</td>
|
||||
|
||||
<td>Incorrect output in compiled mode, interpreted mode works</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Mentor quickhdl</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr NOSAVE>
|
||||
<td NOSAVE>Modeltech modelsim</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Cadence Leapfrog</td>
|
||||
|
||||
<td>Should work with 4.4.1
|
||||
<br>Mysterious problems have been reported - please run the test bench
|
||||
and report problems</td>
|
||||
</tr>
|
||||
</table></center>
|
||||
|
||||
<br>
|
||||
<center><table BORDER COLS=2 WIDTH="80%" NOSAVE >
|
||||
<caption>PCK_FIO_1993 and various simulators/versions</caption>
|
||||
|
||||
<tr NOSAVE>
|
||||
<th NOSAVE>Simulator</th>
|
||||
|
||||
<th NOSAVE>PCK_FIO_1993</th>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS/Scirocco 2000.02</td>
|
||||
|
||||
<td>Compile errors due to improper handling of files by Synopsys</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS/Scirocco 2000.06</td>
|
||||
|
||||
<td>works fine</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Modeltech modelsim 5.4c and higher</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
</table></center>
|
||||
|
||||
<p>Although the package name suggests file IO, it only does file output.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_author_0"></a>Author</h1>
|
||||
<a href="mailto:jand@easics.be">Jan Decaluwe</a>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
</body>
|
||||
</html>
|
||||
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
|
||||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<meta name="GENERATOR" content="Mozilla/4.76 [en] (X11; U; Linux 2.4.13 i686) [Netscape]">
|
||||
<title>VHDL package for formatted file output</title>
|
||||
<!-- $Id: PCK_FIO.html,v 1.1 2008/08/23 08:20:28 Jens Exp $ -->
|
||||
</head>
|
||||
<body text="#000000" bgcolor="#FFFFFF" link="#0000EE" vlink="#551A8B" alink="#FF0000">
|
||||
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_name_0"></a>Name</h1>
|
||||
<b>PCK_FIO</b> - VHDL package for formatted file output
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
Contents</h1>
|
||||
<a href="#PCK_FIO_usage_0">Usage</a>
|
||||
<br><a href="#PCK_FIO_file_0">The file output function 'fo'</a>
|
||||
<br><a href="#PCK_FIO_format_0">Format specifiers</a>
|
||||
<br><a href="#PCK_FIO_special_0">Special characters</a>
|
||||
<br><a href="#PCK_FIO_things_0">Things to watch out for</a>
|
||||
<br><a href="#PCK_FIO_methodology_0">Methodology notes</a>
|
||||
<br><a href="#PCK_FIO_parametrization_0">Parametrization</a>
|
||||
<br><a href="#PCK_FIO_test_0">Test bench</a>
|
||||
<br><a href="#PCK_FIO_limitations_0">Known limitations and problems</a>
|
||||
<br><a href="#PCK_FIO_author_0">Author</a>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_usage_0"></a>Usage</h1>
|
||||
PCK_FIO is a VHDL package that defines <tt>fprint, </tt>a function
|
||||
for formatted file output.
|
||||
<p>After installing the package you can call <tt>fprint</tt> as follows:
|
||||
<pre> fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));</pre>
|
||||
where F is the filehandle and L is the line variable.
|
||||
<p>The argument Format is the format string, which consists of ``normal''
|
||||
substrings which are copied verbatim, and format specifiers, starting with
|
||||
<tt>'%'</tt>.
|
||||
A typical format string looks as follows:
|
||||
<pre> "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"</pre>
|
||||
The remaining arguments are the expressions whose results you want to write
|
||||
to the file, embedded in <tt>fo</tt> function calls. There can be 0 to
|
||||
32 of such arguments. The expressions can be of any type for which an <tt>fo</tt>
|
||||
function exists. String expressions can also be called directly.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_file_0"></a>The file output function <tt>'fo'</tt></h1>
|
||||
The <tt>fo</tt> (<u>f</u>ile <u>o</u>utput) functions do the trick. They
|
||||
return a tagged string representation that is meaningful to format specifiers.
|
||||
Here are some examples:
|
||||
<pre> fo (signed'("1100")) returns "S:1100"
|
||||
fo (unsigned'("1100")) returns "U:1100"
|
||||
fo (TRUE) returns "L:T"
|
||||
fo (127) returns "I:127"</pre>
|
||||
The internal behavior of <tt>fo</tt> is irrelevant to the typical user.
|
||||
<br>
|
||||
<pre>The <tt>fo</tt> function is currently overloaded as follows:</pre>
|
||||
|
||||
<pre> function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;</pre>
|
||||
|
||||
<p><br>To support null-terminated strings, the function <tt>fo</tt>(Arg:
|
||||
string) processes <tt>Arg</tt> up to the first <tt>NUL</tt> character,
|
||||
if any. If you want the whole string to be outputted you can just enter
|
||||
the string as a direct argument in <tt>fprint</tt>. See also the
|
||||
examples in the testbench.
|
||||
<pre>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%"></pre>
|
||||
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_format_0"></a>Format specifiers</h1>
|
||||
The general format of a format specifier is:
|
||||
<pre> %[-][n]c</pre>
|
||||
The optional <b>-</b> sign specifies left justified output; default is
|
||||
right justified.
|
||||
<p>The optional number <b>n</b> specifies a field-width. If it is not specified,
|
||||
<tt>fprint</tt>
|
||||
does something reasonable.
|
||||
<p><b>c</b> is the conversion specifier. Currently the following conversion
|
||||
specifiers are supported:
|
||||
<dl COMPACT>
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_r_0"></a><b>r</b></dt>
|
||||
|
||||
<dd>
|
||||
reasonable output format (inspired by Synopsys VSS)</dd>
|
||||
|
||||
<dl COMPACT>Prints the ``most reasonable'' representation e.g. hex for
|
||||
unsigned, signed and other bit-like vectors (not preferred for integers)</dl>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_b_0"></a><b>b</b></dt>
|
||||
|
||||
<dd>
|
||||
bit-oriented output</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_d_0"></a><b>d</b></dt>
|
||||
|
||||
<dd>
|
||||
decimal output</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_s_0"></a><b>s</b></dt>
|
||||
|
||||
<dd>
|
||||
string output (e.g. in combination with 'IMAGE for enum types)</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_q_0"></a><b>q</b></dt>
|
||||
|
||||
<dd>
|
||||
``qualified'' string output (shows internal representation from <tt>fo</tt>)</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO__0"></a><b>{}</b></dt>
|
||||
|
||||
<dd>
|
||||
Iteration operator, used as follows:</dd>
|
||||
|
||||
<dd>
|
||||
<tt>%n{<format-string>}</tt></dd>
|
||||
|
||||
<br>In this case, <b>n</b> is the iteration count and is mandatory. Iteration
|
||||
can be nested.</dl>
|
||||
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_special_0"></a>Special characters</h1>
|
||||
To print a double quote, use <tt>'""'</tt> in the format string (VHDL
|
||||
convention). To print the special characters, <tt>'\'</tt>, and <tt>'%'</tt>,
|
||||
escape them with <tt>'\'</tt>. To prevent <tt>'{'</tt> and <tt>'}'</tt>
|
||||
from being interpreted as opening and closing brackets in iteration strings,
|
||||
escape them with <tt>'\'</tt>.
|
||||
<p>A newline is specified in the format string by <tt>'\n'</tt>.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_things_0"></a>Things to notice</h1>
|
||||
The fprint function expands into VHDL <tt>write</tt> and <tt>writeline</tt>
|
||||
commands. As in plain VHDL, nothing will be written to the output file
|
||||
until a <tt>writeline</tt> is given. Therefore, don't forget to include
|
||||
<tt>'\n'</tt>
|
||||
commands in the format string, or it ``will not work''.
|
||||
<p>The preferred format specifier for integers is, naturally, <b>%d</b>.
|
||||
This calls the VHDL <tt>write</tt> for integers. If you specify a field
|
||||
width that is too small, the field will automatically be expanded. If you
|
||||
use <b>%r</b> for integers, the field is not expanded automatically, which
|
||||
means that some digits are simply thrown away. This may sometimes be useful
|
||||
but it is also dangerous. Look at the test bench output for differences
|
||||
between <b>%d</b> and <b>%r</b> output.
|
||||
<p>When using the <b>%d</b> format specifier, the VHDL constraints for
|
||||
the allowed integer range apply.
|
||||
<p>In VHDL, signed/unsigned types have been standardized only relatively
|
||||
recently, in the package <tt>IEEE.numeric_std</tt>. The lack of a standard
|
||||
has caused (and is causing) portability issues. The most popular non-standard
|
||||
package that defines signed/unsigned is <tt>IEEE.std_logic_arith</tt> from
|
||||
Synopsys. PCK_FIO works with both packages, but refers to the standard
|
||||
package <tt>IEEE.numeric_std</tt> by default. To use <tt>IEEE.std_logic_arith</tt>
|
||||
instead, replace the reference to <tt>IEEE.numeric_std</tt> in the source
|
||||
code. This needs to be done consistently in a design database (e.g.
|
||||
in the PCK_FIO test bench as well).
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_methodology_0"></a>Methodology notes</h1>
|
||||
The obvious application for <tt>fprint</tt> is in test benches, to produce
|
||||
output files that trace the simulation behavior.
|
||||
<p>Another interesting application for <tt>fprint</tt> is to produce info,
|
||||
warning and error messages in your models. As it can take arguments, <tt>fprint</tt>
|
||||
is much better suited for this task than VHDL's <tt>assert</tt> or <tt>report</tt>
|
||||
statements. Actually <tt>fprint</tt> produces its own (few) warning messages.
|
||||
<p>An advanced usage is the generation of test vectors in a specific format.
|
||||
Instead of using the <tt>fo </tt>functions, you can write your own set
|
||||
of functions that return the symbols of a specific test format in a way
|
||||
that is understandable to the <tt>fprint</tt> format specifiers. As an
|
||||
example, when a high output value should be represented using the symbol
|
||||
'H' it suffices to write a conversion function that returns "B:H" and call
|
||||
it in combination with the <b>%b</b> format specifier.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_parametrization_0"></a>Parametrization</h1>
|
||||
Prefix and postfix strings for bit-oriented and hex-oriented output are
|
||||
parameterizable in the packages to accommodate different output styles.
|
||||
The settings in the distribution are such that hex output is indicated
|
||||
by the prefix '0x', while bit output prefix and postfix are empty
|
||||
strings.
|
||||
<p>You can adapt the output style by modifying the following constants
|
||||
in the package header:
|
||||
<p> <tt> -- prefix string for hex output</tt>
|
||||
<br><tt> -- VHDL style: "X"""</tt>
|
||||
<br><tt> -- Verilog style: "h'"</tt>
|
||||
<br><tt> -- C style: "0x"</tt>
|
||||
<br><tt> constant FIO_h_PRE: string := "0x";</tt>
|
||||
<p><tt> -- postfix string for hex output</tt>
|
||||
<br><tt> -- VHDL style: """"</tt>
|
||||
<br><tt> constant FIO_h_POST: string := "";</tt>
|
||||
<p><tt> -- prefix string for bit vector output</tt>
|
||||
<br><tt> -- VHDL style: "B"""</tt>
|
||||
<br><tt> -- Verilog style: "b'"</tt>
|
||||
<br><tt> constant FIO_bv_PRE: string := "";</tt>
|
||||
<p><tt> -- postfix string for bit vector output</tt>
|
||||
<br><tt> -- VHDL style: """"</tt>
|
||||
<br><tt> constant FIO_bv_POST: string := "";</tt>
|
||||
<p><tt> -- prefix string for bit output</tt>
|
||||
<br><tt> -- VHDL style: "'"</tt>
|
||||
<br><tt> -- Verilog style: "b'"</tt>
|
||||
<br><tt> constant FIO_b_PRE: string := "";</tt>
|
||||
<p><tt> -- postfix string for bit output</tt>
|
||||
<br><tt> -- VHDL style: "'"</tt>
|
||||
<br><tt> constant FIO_b_POST: string := "";</tt>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_test_0"></a>Test bench</h1>
|
||||
Included in the distribution are the files <tt>TB_PCK_FIO_1987.vhd and
|
||||
TB_PCK_FIO_1993</tt> with a test bench,depending on the standard you're
|
||||
running, for the PCK_FIO package. The file <tt>PCK_FIO.out.gold </tt>contains
|
||||
the expected output. If you run the test bench it should produce the file
|
||||
<tt>PCK_FIO.out</tt>
|
||||
that should be identical to <tt>PCK_FIO.out.gold</tt>. The source files
|
||||
should be analyzed in a VHDL library <tt>EASICS_PACKAGES</tt>.
|
||||
<p>A good way to understand <tt>fprint</tt> is to inspect the test bench
|
||||
and what it produces.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_limitations_0"></a>Known limitations and problems</h1>
|
||||
This VHDL package is an implementation of a flexible concept. It is likely
|
||||
to be extended and modified in the future. Backward compatibility is not
|
||||
guaranteed. Therefore, it is not recommended to give this package the status
|
||||
of a company wide standard package (or even worse, a VHDL standard package).
|
||||
Rather, it should be linked with a particular project (and it can be regarded
|
||||
as a standard package within that project).
|
||||
<p>PCK_FIO is available in either standard VHDL Std1076-1987 or standard
|
||||
VHDL Std1076-1993. Nevertheless, some simulators/versions have problems
|
||||
with the package. The following is an overview of currently known issues:
|
||||
<br>
|
||||
<center><table BORDER COLS=2 WIDTH="80%" NOSAVE >
|
||||
<caption>PCK_FIO_1987 and various simulators/versions</caption>
|
||||
|
||||
<tr>
|
||||
<th>Simulator</th>
|
||||
|
||||
<th>PCK_FIO_1987</th>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS 3.5 and earlier</td>
|
||||
|
||||
<td>Incorrect (all zero) output in compiled mode</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS 97.01</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS/Scirocco 2000.02</td>
|
||||
|
||||
<td>Incorrect output in compiled mode, interpreted mode works</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Mentor quickhdl</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr NOSAVE>
|
||||
<td NOSAVE>Modeltech modelsim</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Cadence Leapfrog</td>
|
||||
|
||||
<td>Should work with 4.4.1
|
||||
<br>Mysterious problems have been reported - please run the test bench
|
||||
and report problems</td>
|
||||
</tr>
|
||||
</table></center>
|
||||
|
||||
<br>
|
||||
<center><table BORDER COLS=2 WIDTH="80%" NOSAVE >
|
||||
<caption>PCK_FIO_1993 and various simulators/versions</caption>
|
||||
|
||||
<tr NOSAVE>
|
||||
<th NOSAVE>Simulator</th>
|
||||
|
||||
<th NOSAVE>PCK_FIO_1993</th>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS/Scirocco 2000.02</td>
|
||||
|
||||
<td>Compile errors due to improper handling of files by Synopsys</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS/Scirocco 2000.06</td>
|
||||
|
||||
<td>works fine</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Modeltech modelsim 5.4c and higher</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
</table></center>
|
||||
|
||||
<p>Although the package name suggests file IO, it only does file output.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_author_0"></a>Author</h1>
|
||||
<a href="mailto:jand@easics.be">Jan Decaluwe</a>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
</body>
|
||||
</html>
|
||||
|
||||
+105
-105
@@ -1,105 +1,105 @@
|
||||
---- $Id: PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
-- use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
package PCK_FIO is
|
||||
|
||||
-- prefix string for hex output
|
||||
-- VHDL style: "X"""
|
||||
-- Verilog style: "h'"
|
||||
-- C style: "0x"
|
||||
constant FIO_h_PRE: string := "0x";
|
||||
|
||||
-- postfix string for hex output
|
||||
-- VHDL style: """"
|
||||
constant FIO_h_POST: string := "";
|
||||
|
||||
-- prefix string for bit vector output
|
||||
-- VHDL style: "B"""
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_bv_PRE: string := "";
|
||||
|
||||
-- postfix string for bit vector output
|
||||
-- VHDL style: """"
|
||||
constant FIO_bv_POST: string := "";
|
||||
|
||||
-- prefix string for bit output
|
||||
-- VHDL style: "'"
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_b_PRE: string := "";
|
||||
|
||||
-- postfix string for bit output
|
||||
-- VHDL style: "'"
|
||||
constant FIO_b_POST: string := "";
|
||||
|
||||
-- digit width for the string representation of integers
|
||||
constant FIO_d_WIDTH: integer := 10;
|
||||
|
||||
-- bit width for the string representation of integers
|
||||
constant FIO_b_WIDTH: integer := 32;
|
||||
|
||||
-- definition of the NIL string (default value for fprint arguments)
|
||||
-- fprint stops consuming arguments at the first NIL argument
|
||||
constant FIO_NIL: string := "\";
|
||||
|
||||
|
||||
procedure fprint
|
||||
(F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
);
|
||||
|
||||
function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive);
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
---- $Id: PCK_FIO_1987.vhd,v 1.1 2008/08/23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
-- use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
package PCK_FIO is
|
||||
|
||||
-- prefix string for hex output
|
||||
-- VHDL style: "X"""
|
||||
-- Verilog style: "h'"
|
||||
-- C style: "0x"
|
||||
constant FIO_h_PRE: string := "0x";
|
||||
|
||||
-- postfix string for hex output
|
||||
-- VHDL style: """"
|
||||
constant FIO_h_POST: string := "";
|
||||
|
||||
-- prefix string for bit vector output
|
||||
-- VHDL style: "B"""
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_bv_PRE: string := "";
|
||||
|
||||
-- postfix string for bit vector output
|
||||
-- VHDL style: """"
|
||||
constant FIO_bv_POST: string := "";
|
||||
|
||||
-- prefix string for bit output
|
||||
-- VHDL style: "'"
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_b_PRE: string := "";
|
||||
|
||||
-- postfix string for bit output
|
||||
-- VHDL style: "'"
|
||||
constant FIO_b_POST: string := "";
|
||||
|
||||
-- digit width for the string representation of integers
|
||||
constant FIO_d_WIDTH: integer := 10;
|
||||
|
||||
-- bit width for the string representation of integers
|
||||
constant FIO_b_WIDTH: integer := 32;
|
||||
|
||||
-- definition of the NIL string (default value for fprint arguments)
|
||||
-- fprint stops consuming arguments at the first NIL argument
|
||||
constant FIO_NIL: string := "\";
|
||||
|
||||
|
||||
procedure fprint
|
||||
(F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
);
|
||||
|
||||
function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive);
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
+108
-108
@@ -1,108 +1,108 @@
|
||||
---- $Id: PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
-- use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
package PCK_FIO is
|
||||
|
||||
|
||||
-- prefix string for hex output
|
||||
-- VHDL style: "X"""
|
||||
-- Verilog style: "h'"
|
||||
-- C style: "0x"
|
||||
constant FIO_h_PRE: string := "0x";
|
||||
|
||||
-- postfix string for hex output
|
||||
-- VHDL style: """"
|
||||
constant FIO_h_POST: string := "";
|
||||
|
||||
-- prefix string for bit vector output
|
||||
-- VHDL style: "B"""
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_bv_PRE: string := "";
|
||||
|
||||
-- postfix string for bit vector output
|
||||
-- VHDL style: """"
|
||||
constant FIO_bv_POST: string := "";
|
||||
|
||||
-- prefix string for bit output
|
||||
-- VHDL style: "'"
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_b_PRE: string := "";
|
||||
|
||||
-- postfix string for bit output
|
||||
-- VHDL style: "'"
|
||||
constant FIO_b_POST: string := "";
|
||||
|
||||
-- digit width for the string representation of integers
|
||||
constant FIO_d_WIDTH: integer := 10;
|
||||
|
||||
-- bit width for the string representation of integers
|
||||
constant FIO_b_WIDTH: integer := 32;
|
||||
|
||||
-- definition of the NIL string (default value for fprint arguments)
|
||||
-- fprint stops consuming arguments at the first NIL argument
|
||||
constant FIO_NIL: string := "\";
|
||||
|
||||
procedure fprint
|
||||
(file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
);
|
||||
|
||||
function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive);
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
|
||||
|
||||
---- $Id: PCK_FIO_1993.vhd,v 1.1 2008/08/23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
-- use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
package PCK_FIO is
|
||||
|
||||
|
||||
-- prefix string for hex output
|
||||
-- VHDL style: "X"""
|
||||
-- Verilog style: "h'"
|
||||
-- C style: "0x"
|
||||
constant FIO_h_PRE: string := "0x";
|
||||
|
||||
-- postfix string for hex output
|
||||
-- VHDL style: """"
|
||||
constant FIO_h_POST: string := "";
|
||||
|
||||
-- prefix string for bit vector output
|
||||
-- VHDL style: "B"""
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_bv_PRE: string := "";
|
||||
|
||||
-- postfix string for bit vector output
|
||||
-- VHDL style: """"
|
||||
constant FIO_bv_POST: string := "";
|
||||
|
||||
-- prefix string for bit output
|
||||
-- VHDL style: "'"
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_b_PRE: string := "";
|
||||
|
||||
-- postfix string for bit output
|
||||
-- VHDL style: "'"
|
||||
constant FIO_b_POST: string := "";
|
||||
|
||||
-- digit width for the string representation of integers
|
||||
constant FIO_d_WIDTH: integer := 10;
|
||||
|
||||
-- bit width for the string representation of integers
|
||||
constant FIO_b_WIDTH: integer := 32;
|
||||
|
||||
-- definition of the NIL string (default value for fprint arguments)
|
||||
-- fprint stops consuming arguments at the first NIL argument
|
||||
constant FIO_NIL: string := "\";
|
||||
|
||||
procedure fprint
|
||||
(file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
);
|
||||
|
||||
function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive);
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
+88
-88
@@ -1,88 +1,88 @@
|
||||
---- $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
Version 2002.07
|
||||
===============
|
||||
|
||||
Contents
|
||||
========
|
||||
|
||||
This distribution contains the following files:
|
||||
|
||||
PCK_FIO_1987.vhd: VHDL-87 source of the header of the PCK_FIO package
|
||||
PCK_FIO_1987_BODY.vhd: VHDL-87 source of the body of the PCK_FIO package
|
||||
PCK_FIO_1993.vhd: VHDL-93 source of the header of the PCK_FIO package
|
||||
PCK_FIO_1993_BODY.vhd: VHDL-93 source of the body of the PCK_FIO package
|
||||
TB_PCK_FIO_1987.vhd: VHDL-87 source of the testbench for package PCK_FIO
|
||||
TB_PCK_FIO_1993.vhd: VHDL-93 source of the testbench for package PCK_FIO
|
||||
PCK_FIO.out.gold: Certified test bench output
|
||||
PCK_FIO.html: Manual for PCK_FIO in html format
|
||||
README: This file
|
||||
|
||||
|
||||
Installation
|
||||
============
|
||||
|
||||
VHDL-1987
|
||||
---------
|
||||
To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
|
||||
analyze the VHDL file PCK_FIO_1987.vhd and PCK_FIO_1987_BODY.vhd into this library.
|
||||
|
||||
To install the test bench, analyze TB_PCK_FIO_1987.vhd into the same library.
|
||||
|
||||
VHDL-1993
|
||||
---------
|
||||
To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
|
||||
analyze the VHDL file PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd into this library.
|
||||
|
||||
To install the test bench, analyze TB_PCK_FIO_1993.vhd into the same library.
|
||||
|
||||
Numeric packages
|
||||
----------------
|
||||
If you want to use IEEE.std_logic_arith instead of IEEE.numeric_std, you need
|
||||
to edit the source code of the package, both header and body, and the test bench
|
||||
and replace the package use clause. PCK_FIO works with either of these packages.
|
||||
|
||||
Documentation
|
||||
-------------
|
||||
To install the documentation, put the file point PCK_FIO.html in a path of
|
||||
your choosing, point your web browser to it, and bookmark it.
|
||||
|
||||
|
||||
Installation check
|
||||
==================
|
||||
|
||||
After installing the test bench, you should run it. The corresponding VHDL
|
||||
design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB).
|
||||
|
||||
Simulating the test bench should create a file called PCK_FIO.out. This file
|
||||
should be identical to PCK_FIO.out.gold. Any difference indicates a portability
|
||||
issue or a simulator non-compliance or bug.
|
||||
|
||||
|
||||
|
||||
|
||||
---- $Id: README,v 1.1 2008/08/23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
Version 2002.07
|
||||
===============
|
||||
|
||||
Contents
|
||||
========
|
||||
|
||||
This distribution contains the following files:
|
||||
|
||||
PCK_FIO_1987.vhd: VHDL-87 source of the header of the PCK_FIO package
|
||||
PCK_FIO_1987_BODY.vhd: VHDL-87 source of the body of the PCK_FIO package
|
||||
PCK_FIO_1993.vhd: VHDL-93 source of the header of the PCK_FIO package
|
||||
PCK_FIO_1993_BODY.vhd: VHDL-93 source of the body of the PCK_FIO package
|
||||
TB_PCK_FIO_1987.vhd: VHDL-87 source of the testbench for package PCK_FIO
|
||||
TB_PCK_FIO_1993.vhd: VHDL-93 source of the testbench for package PCK_FIO
|
||||
PCK_FIO.out.gold: Certified test bench output
|
||||
PCK_FIO.html: Manual for PCK_FIO in html format
|
||||
README: This file
|
||||
|
||||
|
||||
Installation
|
||||
============
|
||||
|
||||
VHDL-1987
|
||||
---------
|
||||
To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
|
||||
analyze the VHDL file PCK_FIO_1987.vhd and PCK_FIO_1987_BODY.vhd into this library.
|
||||
|
||||
To install the test bench, analyze TB_PCK_FIO_1987.vhd into the same library.
|
||||
|
||||
VHDL-1993
|
||||
---------
|
||||
To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
|
||||
analyze the VHDL file PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd into this library.
|
||||
|
||||
To install the test bench, analyze TB_PCK_FIO_1993.vhd into the same library.
|
||||
|
||||
Numeric packages
|
||||
----------------
|
||||
If you want to use IEEE.std_logic_arith instead of IEEE.numeric_std, you need
|
||||
to edit the source code of the package, both header and body, and the test bench
|
||||
and replace the package use clause. PCK_FIO works with either of these packages.
|
||||
|
||||
Documentation
|
||||
-------------
|
||||
To install the documentation, put the file point PCK_FIO.html in a path of
|
||||
your choosing, point your web browser to it, and bookmark it.
|
||||
|
||||
|
||||
Installation check
|
||||
==================
|
||||
|
||||
After installing the test bench, you should run it. The corresponding VHDL
|
||||
design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB).
|
||||
|
||||
Simulating the test bench should create a file called PCK_FIO.out. This file
|
||||
should be identical to PCK_FIO.out.gold. Any difference indicates a portability
|
||||
issue or a simulator non-compliance or bug.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -4,8 +4,8 @@
|
||||
vlib work
|
||||
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
|
||||
vcom -explicit -93 "../../misc/dpram_1w1r_dist.vhd"
|
||||
vcom -explicit -93 "../../FIFO/src/fifo_sync_dist.vhd"
|
||||
vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
|
||||
vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../../misc/singleshot.vhd"
|
||||
vcom -explicit -93 "../src/core/ac_out.vhd"
|
||||
vcom -explicit -93 "../src/core/ac_in.vhd"
|
||||
|
||||
+317
-317
@@ -1,317 +1,317 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010-02-09 09:56:37 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use work.async_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity async_port_wb is
|
||||
Generic
|
||||
(
|
||||
f_sysclk : real := 100.0;
|
||||
addr_width : natural := 32;
|
||||
data_width : natural := 32;
|
||||
byte_sel_width : natural := 4;
|
||||
async_timespec : async_timespec_t
|
||||
);
|
||||
Port
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
page_mode_en : in STD_LOGIC;
|
||||
async_a : out unsigned(addr_width-1 downto 0);
|
||||
async_d : inout unsigned(data_width-1 downto 0);
|
||||
async_cs : out std_logic;
|
||||
async_wr : out std_logic;
|
||||
async_rd : out std_logic;
|
||||
async_be : out unsigned(byte_sel_width-1 downto 0);
|
||||
async_rst : out std_logic
|
||||
);
|
||||
end async_port_wb;
|
||||
|
||||
architecture Behavioral of async_port_wb is
|
||||
|
||||
type async_t is record
|
||||
cs : std_logic;
|
||||
wr : std_logic;
|
||||
rd : std_logic;
|
||||
rst : std_logic;
|
||||
drive_d : std_logic;
|
||||
end record;
|
||||
|
||||
type async_state_t is (start, reset, idle, leadin, pulse, leadout, release);
|
||||
|
||||
signal s, sn : async_state_t;
|
||||
signal as : async_t;
|
||||
signal ack : std_logic;
|
||||
signal cc_rst : std_logic;
|
||||
signal cycle_cnt : natural range 0 to 31;
|
||||
signal cycle_reload : natural range 0 to 31;
|
||||
signal rdy : std_logic;
|
||||
signal rdyo : std_logic;
|
||||
signal en : std_logic;
|
||||
signal is_idle : std_logic;
|
||||
signal DAT_I_r : unsigned(data_width-1 downto 0);
|
||||
signal SEL_I_r : unsigned(byte_sel_width-1 downto 0);
|
||||
signal WE_I_r : std_logic;
|
||||
signal ADDR_I_r : unsigned(addr_width-1 downto 0);
|
||||
signal page_mode_en_r : std_logic;
|
||||
signal do_page_read : std_logic;
|
||||
|
||||
------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk) > 0 report "Read pulse length must be greater than zero!" severity failure;
|
||||
ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk) > 0 report "Write pulse length must be greater than zero!" severity failure;
|
||||
ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) > 1)) report "Read page pulse length must be greater than one!" severity failure;
|
||||
|
||||
SRDY_O <= CYC_I and rdyo;
|
||||
en <= CYC_I and STB_I;
|
||||
|
||||
do_page_read <= '1' when (async_timespec.can_page_rd and (WE_I = '0') and (WE_I_r = '0') and (ADDR_I(addr_width-1 downto async_timespec.nbits_page_rd) = ADDR_I_r(addr_width-1 downto async_timespec.nbits_page_rd))) else '0';
|
||||
|
||||
proc_cycle_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if cc_rst = '1' then
|
||||
cycle_cnt <= cycle_reload;
|
||||
elsif cycle_cnt /= 0 then
|
||||
cycle_cnt <= cycle_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
proc_state_next:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
s <= start;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_state:
|
||||
process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
|
||||
begin
|
||||
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
|
||||
cc_rst <= '0';
|
||||
as.rst <= '0';
|
||||
as.cs <= '0';
|
||||
as.wr <= '0';
|
||||
as.rd <= '0';
|
||||
as.drive_d <= '0';
|
||||
ack <= '0';
|
||||
rdy <= '0';
|
||||
is_idle <= '0';
|
||||
|
||||
sn <= s;
|
||||
case s is
|
||||
|
||||
when start =>
|
||||
cc_rst <= '1';
|
||||
sn <= reset;
|
||||
when reset =>
|
||||
as.rst <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
sn <= idle;
|
||||
end if;
|
||||
when idle =>
|
||||
rdy <= '1';
|
||||
is_idle <= '1';
|
||||
if en = '1' then
|
||||
as.cs <= '1';
|
||||
cc_rst <= '1';
|
||||
if to_cycles(async_timespec.T_leadin, f_sysclk) = 0 then
|
||||
sn <= pulse;
|
||||
if WE_I = '1' then
|
||||
cycle_reload <= 0;
|
||||
sn <= leadin; -- always lead-in for writes
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
|
||||
as.rd <= '1';
|
||||
end if;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk) - 1;
|
||||
sn <= leadin;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when leadin =>
|
||||
as.cs <= '1';
|
||||
as.rd <= not WE_I_r;
|
||||
as.drive_d <= WE_I_r;
|
||||
as.wr <= WE_I_r;
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
sn <= pulse;
|
||||
if WE_I_r = '1' then
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk) - 1;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when pulse =>
|
||||
as.cs <= '1';
|
||||
as.rd <= not WE_I_r;
|
||||
as.drive_d <= WE_I_r;
|
||||
as.wr <= WE_I_r;
|
||||
if cycle_cnt = 0 then
|
||||
as.wr <= '0';
|
||||
cc_rst <= '1';
|
||||
ack <= not WE_I_r;
|
||||
rdy <= do_page_read;
|
||||
if en = '1' and do_page_read = '1' then
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) - 1;
|
||||
sn <= pulse;
|
||||
elsif to_cycles(async_timespec.T_leadout, f_sysclk) = 0 then
|
||||
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
|
||||
sn <= idle;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
|
||||
sn <= release;
|
||||
end if;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk) - 1;
|
||||
sn <= leadout;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when leadout =>
|
||||
as.cs <= '1';
|
||||
as.drive_d <= WE_I_r;
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
|
||||
sn <= idle;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
|
||||
sn <= release;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when release =>
|
||||
if cycle_cnt = 0 then
|
||||
sn <= idle;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
sn <= idle;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_ctrl:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
async_cs <= (not async_timespec.pol_cs) xor as.cs;
|
||||
async_wr <= (not async_timespec.pol_we) xor as.wr;
|
||||
async_rd <= (not async_timespec.pol_oe) xor as.rd;
|
||||
async_rst <= (not async_timespec.pol_rst) xor as.rst;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
din_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if as.rd = '1' then
|
||||
DAT_O(data_width-1 downto 0) <= async_d;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_addr:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
async_a <= (others => '0');
|
||||
SEL_I_r <= (others => '0');
|
||||
elsif en = '1' and rdy = '1' then
|
||||
async_a <= ADDR_I(addr_width-1 downto 0);
|
||||
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I(byte_sel_width-1 downto 0));
|
||||
SEL_I_r <= SEL_I(byte_sel_width-1 downto 0);
|
||||
if is_idle = '1' then
|
||||
ADDR_I_r <= ADDR_I(addr_width-1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
data_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
page_mode_en_r <= page_mode_en;
|
||||
if en = '1' and rdy = '1' then
|
||||
DAT_I_r <= DAT_I(data_width-1 downto 0);
|
||||
WE_I_r <= WE_I;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_SRDY:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
rdyo <= '1';
|
||||
elsif en = '1' then
|
||||
rdyo <= rdy and not rdyo;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_ACK:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
ACK_O <= '0';
|
||||
else
|
||||
ACK_O <= ack;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_data:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
async_d <= (others => 'Z');
|
||||
if as.drive_d = '1' then
|
||||
async_d <= DAT_I_r;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010/02/09 09:56:37 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use work.async_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity async_port_wb is
|
||||
Generic
|
||||
(
|
||||
f_sysclk : real := 100.0;
|
||||
addr_width : natural := 32;
|
||||
data_width : natural := 32;
|
||||
byte_sel_width : natural := 4;
|
||||
async_timespec : async_timespec_t
|
||||
);
|
||||
Port
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
page_mode_en : in STD_LOGIC;
|
||||
async_a : out unsigned(addr_width-1 downto 0);
|
||||
async_d : inout unsigned(data_width-1 downto 0);
|
||||
async_cs : out std_logic;
|
||||
async_wr : out std_logic;
|
||||
async_rd : out std_logic;
|
||||
async_be : out unsigned(byte_sel_width-1 downto 0);
|
||||
async_rst : out std_logic
|
||||
);
|
||||
end async_port_wb;
|
||||
|
||||
architecture Behavioral of async_port_wb is
|
||||
|
||||
type async_t is record
|
||||
cs : std_logic;
|
||||
wr : std_logic;
|
||||
rd : std_logic;
|
||||
rst : std_logic;
|
||||
drive_d : std_logic;
|
||||
end record;
|
||||
|
||||
type async_state_t is (start, reset, idle, leadin, pulse, leadout, release);
|
||||
|
||||
signal s, sn : async_state_t;
|
||||
signal as : async_t;
|
||||
signal ack : std_logic;
|
||||
signal cc_rst : std_logic;
|
||||
signal cycle_cnt : natural range 0 to 31;
|
||||
signal cycle_reload : natural range 0 to 31;
|
||||
signal rdy : std_logic;
|
||||
signal rdyo : std_logic;
|
||||
signal en : std_logic;
|
||||
signal is_idle : std_logic;
|
||||
signal DAT_I_r : unsigned(data_width-1 downto 0);
|
||||
signal SEL_I_r : unsigned(byte_sel_width-1 downto 0);
|
||||
signal WE_I_r : std_logic;
|
||||
signal ADDR_I_r : unsigned(addr_width-1 downto 0);
|
||||
signal page_mode_en_r : std_logic;
|
||||
signal do_page_read : std_logic;
|
||||
|
||||
------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk) > 0 report "Read pulse length must be greater than zero!" severity failure;
|
||||
ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk) > 0 report "Write pulse length must be greater than zero!" severity failure;
|
||||
ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) > 1)) report "Read page pulse length must be greater than one!" severity failure;
|
||||
|
||||
SRDY_O <= CYC_I and rdyo;
|
||||
en <= CYC_I and STB_I;
|
||||
|
||||
do_page_read <= '1' when (async_timespec.can_page_rd and (WE_I = '0') and (WE_I_r = '0') and (ADDR_I(addr_width-1 downto async_timespec.nbits_page_rd) = ADDR_I_r(addr_width-1 downto async_timespec.nbits_page_rd))) else '0';
|
||||
|
||||
proc_cycle_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if cc_rst = '1' then
|
||||
cycle_cnt <= cycle_reload;
|
||||
elsif cycle_cnt /= 0 then
|
||||
cycle_cnt <= cycle_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
proc_state_next:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
s <= start;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_state:
|
||||
process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
|
||||
begin
|
||||
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
|
||||
cc_rst <= '0';
|
||||
as.rst <= '0';
|
||||
as.cs <= '0';
|
||||
as.wr <= '0';
|
||||
as.rd <= '0';
|
||||
as.drive_d <= '0';
|
||||
ack <= '0';
|
||||
rdy <= '0';
|
||||
is_idle <= '0';
|
||||
|
||||
sn <= s;
|
||||
case s is
|
||||
|
||||
when start =>
|
||||
cc_rst <= '1';
|
||||
sn <= reset;
|
||||
when reset =>
|
||||
as.rst <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
sn <= idle;
|
||||
end if;
|
||||
when idle =>
|
||||
rdy <= '1';
|
||||
is_idle <= '1';
|
||||
if en = '1' then
|
||||
as.cs <= '1';
|
||||
cc_rst <= '1';
|
||||
if to_cycles(async_timespec.T_leadin, f_sysclk) = 0 then
|
||||
sn <= pulse;
|
||||
if WE_I = '1' then
|
||||
cycle_reload <= 0;
|
||||
sn <= leadin; -- always lead-in for writes
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
|
||||
as.rd <= '1';
|
||||
end if;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk) - 1;
|
||||
sn <= leadin;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when leadin =>
|
||||
as.cs <= '1';
|
||||
as.rd <= not WE_I_r;
|
||||
as.drive_d <= WE_I_r;
|
||||
as.wr <= WE_I_r;
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
sn <= pulse;
|
||||
if WE_I_r = '1' then
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk) - 1;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when pulse =>
|
||||
as.cs <= '1';
|
||||
as.rd <= not WE_I_r;
|
||||
as.drive_d <= WE_I_r;
|
||||
as.wr <= WE_I_r;
|
||||
if cycle_cnt = 0 then
|
||||
as.wr <= '0';
|
||||
cc_rst <= '1';
|
||||
ack <= not WE_I_r;
|
||||
rdy <= do_page_read;
|
||||
if en = '1' and do_page_read = '1' then
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) - 1;
|
||||
sn <= pulse;
|
||||
elsif to_cycles(async_timespec.T_leadout, f_sysclk) = 0 then
|
||||
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
|
||||
sn <= idle;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
|
||||
sn <= release;
|
||||
end if;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk) - 1;
|
||||
sn <= leadout;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when leadout =>
|
||||
as.cs <= '1';
|
||||
as.drive_d <= WE_I_r;
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
|
||||
sn <= idle;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
|
||||
sn <= release;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when release =>
|
||||
if cycle_cnt = 0 then
|
||||
sn <= idle;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
sn <= idle;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_ctrl:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
async_cs <= (not async_timespec.pol_cs) xor as.cs;
|
||||
async_wr <= (not async_timespec.pol_we) xor as.wr;
|
||||
async_rd <= (not async_timespec.pol_oe) xor as.rd;
|
||||
async_rst <= (not async_timespec.pol_rst) xor as.rst;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
din_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if as.rd = '1' then
|
||||
DAT_O(data_width-1 downto 0) <= async_d;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_addr:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
async_a <= (others => '0');
|
||||
SEL_I_r <= (others => '0');
|
||||
elsif en = '1' and rdy = '1' then
|
||||
async_a <= ADDR_I(addr_width-1 downto 0);
|
||||
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I(byte_sel_width-1 downto 0));
|
||||
SEL_I_r <= SEL_I(byte_sel_width-1 downto 0);
|
||||
if is_idle = '1' then
|
||||
ADDR_I_r <= ADDR_I(addr_width-1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
data_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
page_mode_en_r <= page_mode_en;
|
||||
if en = '1' and rdy = '1' then
|
||||
DAT_I_r <= DAT_I(data_width-1 downto 0);
|
||||
WE_I_r <= WE_I;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_SRDY:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
rdyo <= '1';
|
||||
elsif en = '1' then
|
||||
rdyo <= rdy and not rdyo;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_ACK:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
ACK_O <= '0';
|
||||
else
|
||||
ACK_O <= ack;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_data:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
async_d <= (others => 'Z');
|
||||
if as.drive_d = '1' then
|
||||
async_d <= DAT_I_r;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
|
||||
+123
-123
@@ -1,123 +1,123 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008-10-20 19:26:01 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity bbfifo is
|
||||
Generic
|
||||
(
|
||||
depth : integer := 2;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
re : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
ready : out STD_LOGIC;
|
||||
avail : out STD_LOGIC;
|
||||
din : in unsigned(data_width-1 downto 0);
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
|
||||
end bbfifo;
|
||||
|
||||
architecture Behavioral of bbfifo is
|
||||
|
||||
type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
|
||||
signal req : unsigned(0 to depth);
|
||||
signal rdy : unsigned(1 to depth+1);
|
||||
signal bucket_array : bucket_array_t;
|
||||
signal ce_in : unsigned(1 to depth);
|
||||
signal ce_out : unsigned(1 to depth);
|
||||
|
||||
begin
|
||||
|
||||
req(0) <= we;
|
||||
rdy(depth+1) <= re;
|
||||
ready <= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0';
|
||||
avail <= req(depth);
|
||||
bucket_array(0) <= din;
|
||||
dout <= bucket_array(depth);
|
||||
|
||||
gen_ce:
|
||||
for i in 1 to depth generate
|
||||
begin
|
||||
process (rdy, req)
|
||||
begin
|
||||
ce_in(i) <= not req(i) and req(i-1);
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
gen_rdy:
|
||||
for i in 1 to depth generate
|
||||
begin
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
rdy(i) <= '1';
|
||||
elsif req(i-1) = '1' then
|
||||
rdy(i) <= rdy(i+1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
gen_req:
|
||||
for i in 1 to depth generate
|
||||
begin
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
req(i) <= '0';
|
||||
elsif rdy(i+1) = '1' then
|
||||
req(i) <= req(i-1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
gen_data:
|
||||
for i in 1 to depth generate
|
||||
begin
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
bucket_array(i) <= (others => '0');
|
||||
elsif req(i-1) = '1' then
|
||||
bucket_array(i) <= bucket_array(i-1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008/10/20 19:26:01 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity bbfifo is
|
||||
Generic
|
||||
(
|
||||
depth : integer := 2;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
re : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
ready : out STD_LOGIC;
|
||||
avail : out STD_LOGIC;
|
||||
din : in unsigned(data_width-1 downto 0);
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
|
||||
end bbfifo;
|
||||
|
||||
architecture Behavioral of bbfifo is
|
||||
|
||||
type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
|
||||
signal req : unsigned(0 to depth);
|
||||
signal rdy : unsigned(1 to depth+1);
|
||||
signal bucket_array : bucket_array_t;
|
||||
signal ce_in : unsigned(1 to depth);
|
||||
signal ce_out : unsigned(1 to depth);
|
||||
|
||||
begin
|
||||
|
||||
req(0) <= we;
|
||||
rdy(depth+1) <= re;
|
||||
ready <= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0';
|
||||
avail <= req(depth);
|
||||
bucket_array(0) <= din;
|
||||
dout <= bucket_array(depth);
|
||||
|
||||
gen_ce:
|
||||
for i in 1 to depth generate
|
||||
begin
|
||||
process (rdy, req)
|
||||
begin
|
||||
ce_in(i) <= not req(i) and req(i-1);
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
gen_rdy:
|
||||
for i in 1 to depth generate
|
||||
begin
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
rdy(i) <= '1';
|
||||
elsif req(i-1) = '1' then
|
||||
rdy(i) <= rdy(i+1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
gen_req:
|
||||
for i in 1 to depth generate
|
||||
begin
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
req(i) <= '0';
|
||||
elsif rdy(i+1) = '1' then
|
||||
req(i) <= req(i-1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
gen_data:
|
||||
for i in 1 to depth generate
|
||||
begin
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
bucket_array(i) <= (others => '0');
|
||||
elsif req(i-1) = '1' then
|
||||
bucket_array(i) <= bucket_array(i-1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
+91
-91
@@ -1,91 +1,91 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 19:34:24 10/23/05
|
||||
-- Design Name:
|
||||
-- Module Name: debounce - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity debounce is
|
||||
Generic ( ncyc_latency : integer := 100);
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
input : in std_logic;
|
||||
output : out std_logic);
|
||||
end debounce;
|
||||
|
||||
architecture Behavioral of debounce is
|
||||
|
||||
type debounce_state_t is (init_st, wait_st, rel_st);
|
||||
signal debounce_cs : debounce_state_t;
|
||||
signal debounce_ns : debounce_state_t;
|
||||
signal count : integer range 0 to ncyc_latency;
|
||||
signal input_last : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
count <= 0;
|
||||
output <= input;
|
||||
input_last <= input;
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
debounce_cs <= debounce_ns;
|
||||
if (debounce_cs = wait_st) then
|
||||
if (count /= 0) then
|
||||
count <= count - 1;
|
||||
end if;
|
||||
else
|
||||
count <= ncyc_latency;
|
||||
if (debounce_cs = rel_st) then
|
||||
output <= input;
|
||||
input_last <= input;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
debounce_in: process(rst, clk, input, input_last, debounce_cs, count)
|
||||
begin
|
||||
debounce_ns <= debounce_cs;
|
||||
case debounce_cs is
|
||||
when init_st =>
|
||||
if (input /= input_last) then
|
||||
debounce_ns <= wait_st;
|
||||
end if;
|
||||
when wait_st =>
|
||||
if (count = 0) then
|
||||
debounce_ns <= rel_st;
|
||||
end if;
|
||||
when others =>
|
||||
debounce_ns <= init_st;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 19:34:24 10/23/05
|
||||
-- Design Name:
|
||||
-- Module Name: debounce - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity debounce is
|
||||
Generic ( ncyc_latency : integer := 100);
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
input : in std_logic;
|
||||
output : out std_logic);
|
||||
end debounce;
|
||||
|
||||
architecture Behavioral of debounce is
|
||||
|
||||
type debounce_state_t is (init_st, wait_st, rel_st);
|
||||
signal debounce_cs : debounce_state_t;
|
||||
signal debounce_ns : debounce_state_t;
|
||||
signal count : integer range 0 to ncyc_latency;
|
||||
signal input_last : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
count <= 0;
|
||||
output <= input;
|
||||
input_last <= input;
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
debounce_cs <= debounce_ns;
|
||||
if (debounce_cs = wait_st) then
|
||||
if (count /= 0) then
|
||||
count <= count - 1;
|
||||
end if;
|
||||
else
|
||||
count <= ncyc_latency;
|
||||
if (debounce_cs = rel_st) then
|
||||
output <= input;
|
||||
input_last <= input;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
debounce_in: process(rst, clk, input, input_last, debounce_cs, count)
|
||||
begin
|
||||
debounce_ns <= debounce_cs;
|
||||
case debounce_cs is
|
||||
when init_st =>
|
||||
if (input /= input_last) then
|
||||
debounce_ns <= wait_st;
|
||||
end if;
|
||||
when wait_st =>
|
||||
if (count = 0) then
|
||||
debounce_ns <= rel_st;
|
||||
end if;
|
||||
when others =>
|
||||
debounce_ns <= init_st;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
+142
-142
@@ -1,142 +1,142 @@
|
||||
-------------------------------------------------
|
||||
-- Signal Debouncer
|
||||
-- Jeff Bazinet
|
||||
-- February 14, 2002
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library lpm;
|
||||
use lpm.lpm_components.lpm_counter;
|
||||
|
||||
|
||||
entity debounce is
|
||||
generic(BUFFER_WIDTH: positive:= 30;
|
||||
CLOCK_DIV: positive:= 15
|
||||
);
|
||||
port( clock: in std_logic;
|
||||
reset: in std_logic;
|
||||
signal_in: in std_logic;
|
||||
signal_out: out std_logic
|
||||
);
|
||||
end entity debounce;
|
||||
|
||||
|
||||
architecture rtl of debounce is
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- SIGNAL DECLARATION
|
||||
---------------------------------------------------------------
|
||||
|
||||
-- General
|
||||
signal reset_n: std_logic;
|
||||
|
||||
-- SLOW CLOCK GENERATION
|
||||
signal clock_reg: std_logic_vector(CLOCK_DIV-1 downto 0);
|
||||
signal clock_reg_high: std_logic_vector(CLOCK_DIV-1 downto 1);
|
||||
signal clock_slow: std_logic;
|
||||
signal clock_slow_wire: std_logic;
|
||||
|
||||
-- DATA BUFFER FILL
|
||||
signal counter_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
|
||||
signal data_buffer_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
|
||||
|
||||
-- CHECK FOR DEBOUNCE STABILITY
|
||||
signal stable: std_logic;
|
||||
signal stable_old: std_logic;
|
||||
signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0);
|
||||
|
||||
-- PUSH BUTTON ENABLE
|
||||
signal button_pushed: std_logic;
|
||||
|
||||
begin
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- SLOW CLOCK GENERATION
|
||||
---------------------------------------------------------------
|
||||
|
||||
COUNTER_1: lpm_counter
|
||||
generic map (lpm_width => CLOCK_DIV)
|
||||
port map (
|
||||
clock => clock,
|
||||
sclr => reset_n,
|
||||
cout => clock_slow_wire
|
||||
);
|
||||
|
||||
process (clock) is
|
||||
begin
|
||||
|
||||
clock_slow <= clock_slow_wire;
|
||||
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- DATA BUFFER FILL
|
||||
---------------------------------------------------------------
|
||||
|
||||
process (clock) is
|
||||
begin
|
||||
|
||||
if (reset = '0') then
|
||||
-- Initialization
|
||||
data_buffer_reg <= (others => '1');
|
||||
elsif rising_edge(clock_slow) then
|
||||
data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- CHECK FOR DEBOUNCE STABILITY
|
||||
---------------------------------------------------------------
|
||||
|
||||
process (clock) is
|
||||
begin
|
||||
|
||||
if (reset = '0') then
|
||||
-- Initialization
|
||||
stable <= '0';
|
||||
stable_old <= '0';
|
||||
stable_state_reg <= (others => '0');
|
||||
elsif rising_edge(clock) then
|
||||
if (data_buffer_reg = stable_state_reg) then
|
||||
stable <= '1';
|
||||
stable_state_reg <= (others => '0');
|
||||
else
|
||||
stable <= '0';
|
||||
end if;
|
||||
stable_old <= stable;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- PUSH BUTTON ENABLE
|
||||
---------------------------------------------------------------
|
||||
|
||||
process (clock) is
|
||||
begin
|
||||
|
||||
if (reset = '0') then
|
||||
-- Initialization
|
||||
button_pushed <= '0';
|
||||
elsif rising_edge(clock) then
|
||||
if (stable_old = '0' and stable = '1') then
|
||||
button_pushed <= '1';
|
||||
else
|
||||
button_pushed <= '0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
signal_out <= button_pushed;
|
||||
reset_n <= not reset;
|
||||
|
||||
end rtl;
|
||||
-------------------------------------------------
|
||||
-- Signal Debouncer
|
||||
-- Jeff Bazinet
|
||||
-- February 14, 2002
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library lpm;
|
||||
use lpm.lpm_components.lpm_counter;
|
||||
|
||||
|
||||
entity debounce is
|
||||
generic(BUFFER_WIDTH: positive:= 30;
|
||||
CLOCK_DIV: positive:= 15
|
||||
);
|
||||
port( clock: in std_logic;
|
||||
reset: in std_logic;
|
||||
signal_in: in std_logic;
|
||||
signal_out: out std_logic
|
||||
);
|
||||
end entity debounce;
|
||||
|
||||
|
||||
architecture rtl of debounce is
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- SIGNAL DECLARATION
|
||||
---------------------------------------------------------------
|
||||
|
||||
-- General
|
||||
signal reset_n: std_logic;
|
||||
|
||||
-- SLOW CLOCK GENERATION
|
||||
signal clock_reg: std_logic_vector(CLOCK_DIV-1 downto 0);
|
||||
signal clock_reg_high: std_logic_vector(CLOCK_DIV-1 downto 1);
|
||||
signal clock_slow: std_logic;
|
||||
signal clock_slow_wire: std_logic;
|
||||
|
||||
-- DATA BUFFER FILL
|
||||
signal counter_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
|
||||
signal data_buffer_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
|
||||
|
||||
-- CHECK FOR DEBOUNCE STABILITY
|
||||
signal stable: std_logic;
|
||||
signal stable_old: std_logic;
|
||||
signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0);
|
||||
|
||||
-- PUSH BUTTON ENABLE
|
||||
signal button_pushed: std_logic;
|
||||
|
||||
begin
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- SLOW CLOCK GENERATION
|
||||
---------------------------------------------------------------
|
||||
|
||||
COUNTER_1: lpm_counter
|
||||
generic map (lpm_width => CLOCK_DIV)
|
||||
port map (
|
||||
clock => clock,
|
||||
sclr => reset_n,
|
||||
cout => clock_slow_wire
|
||||
);
|
||||
|
||||
process (clock) is
|
||||
begin
|
||||
|
||||
clock_slow <= clock_slow_wire;
|
||||
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- DATA BUFFER FILL
|
||||
---------------------------------------------------------------
|
||||
|
||||
process (clock) is
|
||||
begin
|
||||
|
||||
if (reset = '0') then
|
||||
-- Initialization
|
||||
data_buffer_reg <= (others => '1');
|
||||
elsif rising_edge(clock_slow) then
|
||||
data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- CHECK FOR DEBOUNCE STABILITY
|
||||
---------------------------------------------------------------
|
||||
|
||||
process (clock) is
|
||||
begin
|
||||
|
||||
if (reset = '0') then
|
||||
-- Initialization
|
||||
stable <= '0';
|
||||
stable_old <= '0';
|
||||
stable_state_reg <= (others => '0');
|
||||
elsif rising_edge(clock) then
|
||||
if (data_buffer_reg = stable_state_reg) then
|
||||
stable <= '1';
|
||||
stable_state_reg <= (others => '0');
|
||||
else
|
||||
stable <= '0';
|
||||
end if;
|
||||
stable_old <= stable;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- PUSH BUTTON ENABLE
|
||||
---------------------------------------------------------------
|
||||
|
||||
process (clock) is
|
||||
begin
|
||||
|
||||
if (reset = '0') then
|
||||
-- Initialization
|
||||
button_pushed <= '0';
|
||||
elsif rising_edge(clock) then
|
||||
if (stable_old = '0' and stable = '1') then
|
||||
button_pushed <= '1';
|
||||
else
|
||||
button_pushed <= '0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
signal_out <= button_pushed;
|
||||
reset_n <= not reset;
|
||||
|
||||
end rtl;
|
||||
|
||||
+79
-79
@@ -1,79 +1,79 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r;
|
||||
|
||||
architecture Behavioral of dpram_1w1r is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clka)
|
||||
begin
|
||||
if clka'event and clka = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clkb)
|
||||
begin
|
||||
if clkb'event and clkb = '1' then
|
||||
if en_b = '1' then
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r;
|
||||
|
||||
architecture Behavioral of dpram_1w1r is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clka)
|
||||
begin
|
||||
if clka'event and clka = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clkb)
|
||||
begin
|
||||
if clkb'event and clkb = '1' then
|
||||
if en_b = '1' then
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,77 +1,77 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r1c_sim.vhd,v 1.1 2013-02-07 14:15:37 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r1c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r1c;
|
||||
|
||||
architecture Behavioral of dpram_1w1r1c is
|
||||
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r1c_sim.vhd,v 1.1 2013/02/07 14:15:37 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r1c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r1c;
|
||||
|
||||
architecture Behavioral of dpram_1w1r1c is
|
||||
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,77 +1,77 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r1c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r1c;
|
||||
|
||||
architecture Behavioral of dpram_1w1r1c is
|
||||
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r1c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r1c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r1c;
|
||||
|
||||
architecture Behavioral of dpram_1w1r1c is
|
||||
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,82 +1,82 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r2c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r2c is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r2c;
|
||||
|
||||
architecture Behavioral of dpram_1w1r2c is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r2c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r2c is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r2c;
|
||||
|
||||
architecture Behavioral of dpram_1w1r2c is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,82 +1,82 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r2c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r2c is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r2c;
|
||||
|
||||
architecture Behavioral of dpram_1w1r2c is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r2c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r2c is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r2c;
|
||||
|
||||
architecture Behavioral of dpram_1w1r2c is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,84 +1,84 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r_dist is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r_dist;
|
||||
|
||||
architecture Behavioral of dpram_1w1r_dist is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
attribute ram_style : string;
|
||||
attribute ram_style of RAM: signal is "distributed";
|
||||
|
||||
begin
|
||||
|
||||
process (clka)
|
||||
begin
|
||||
if clka'event and clka = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clkb)
|
||||
begin
|
||||
if clkb'event and clkb = '1' then
|
||||
if en_b = '1' then
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r_dist is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r_dist;
|
||||
|
||||
architecture Behavioral of dpram_1w1r_dist is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
attribute ram_style : string;
|
||||
attribute ram_style of RAM: signal is "distributed";
|
||||
|
||||
begin
|
||||
|
||||
process (clka)
|
||||
begin
|
||||
if clka'event and clka = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clkb)
|
||||
begin
|
||||
if clkb'event and clkb = '1' then
|
||||
if en_b = '1' then
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,86 +1,86 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w2r1c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_1w2r1c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w2r1c;
|
||||
|
||||
architecture Behavioral of dpram_1w2r1c is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
signal addr_a_r : unsigned (addr_width-1 downto 0);
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
dout_a <= RAM(to_integer(addr_a_r));
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
addr_a_r <= addr_a;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w2r1c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_1w2r1c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w2r1c;
|
||||
|
||||
architecture Behavioral of dpram_1w2r1c is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
signal addr_a_r : unsigned (addr_width-1 downto 0);
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
dout_a <= RAM(to_integer(addr_a_r));
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
addr_a_r <= addr_a;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,80 +1,80 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w2r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_1w2r1c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w2r1c;
|
||||
|
||||
architecture Behavioral of dpram_1w2r1c is
|
||||
|
||||
|
||||
begin
|
||||
|
||||
inst_dpram: entity work.dpram_2w2r2c
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
data_width => data_width
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
clk_b => clk,
|
||||
en_a => en_a,
|
||||
en_b => en_b,
|
||||
we_a => we_a,
|
||||
we_b => '0',
|
||||
addr_a => addr_a,
|
||||
addr_b => addr_b,
|
||||
din_a => din_a,
|
||||
din_b => din_a,
|
||||
dout_a => dout_a,
|
||||
dout_b => dout_b
|
||||
);
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w2r1c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_1w2r1c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w2r1c;
|
||||
|
||||
architecture Behavioral of dpram_1w2r1c is
|
||||
|
||||
|
||||
begin
|
||||
|
||||
inst_dpram: entity work.dpram_2w2r2c
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
data_width => data_width
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
clk_b => clk,
|
||||
en_a => en_a,
|
||||
en_b => en_b,
|
||||
we_a => we_a,
|
||||
we_b => '0',
|
||||
addr_a => addr_a,
|
||||
addr_b => addr_b,
|
||||
din_a => din_a,
|
||||
din_b => din_a,
|
||||
dout_a => dout_a,
|
||||
dout_b => dout_b
|
||||
);
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
+88
-88
@@ -1,88 +1,88 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009-01-14 20:26:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r;
|
||||
|
||||
architecture Behavioral of dpram_2w2r is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
dout_a <= RAM(to_integer(addr_a));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009/01/14 20:26:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r;
|
||||
|
||||
architecture Behavioral of dpram_2w2r is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
dout_a <= RAM(to_integer(addr_a));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,88 +1,88 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r1c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r1c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r1c;
|
||||
|
||||
architecture Behavioral of dpram_2w2r1c is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
signal addr_a_r : unsigned (addr_width-1 downto 0);
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
signal contention : std_logic;
|
||||
begin
|
||||
|
||||
dout_a <= RAM(to_integer(addr_a_r));
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
contention <= en_a and we_a and en_b and we_b;
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
assert contention = '0' report "dpram_2w2r1c: Simultaneous write on Port A and Port B!" severity warning;
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
addr_a_r <= addr_a;
|
||||
end if;
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) <= din_b;
|
||||
end if;
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r1c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r1c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r1c;
|
||||
|
||||
architecture Behavioral of dpram_2w2r1c is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
signal addr_a_r : unsigned (addr_width-1 downto 0);
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
signal contention : std_logic;
|
||||
begin
|
||||
|
||||
dout_a <= RAM(to_integer(addr_a_r));
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
contention <= en_a and we_a and en_b and we_b;
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
assert contention = '0' report "dpram_2w2r1c: Simultaneous write on Port A and Port B!" severity warning;
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
addr_a_r <= addr_a;
|
||||
end if;
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) <= din_b;
|
||||
end if;
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,82 +1,82 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r1c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r1c;
|
||||
|
||||
architecture Behavioral of dpram_2w2r1c is
|
||||
|
||||
|
||||
begin
|
||||
|
||||
inst_dpram: entity work.dpram_2w2r2c
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
data_width => data_width
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
clk_b => clk,
|
||||
en_a => en_a,
|
||||
en_b => en_b,
|
||||
we_a => we_a,
|
||||
we_b => we_b,
|
||||
addr_a => addr_a,
|
||||
addr_b => addr_b,
|
||||
din_a => din_a,
|
||||
din_b => din_a,
|
||||
dout_a => dout_a,
|
||||
dout_b => dout_b
|
||||
);
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r1c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r1c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r1c;
|
||||
|
||||
architecture Behavioral of dpram_2w2r1c is
|
||||
|
||||
|
||||
begin
|
||||
|
||||
inst_dpram: entity work.dpram_2w2r2c
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
data_width => data_width
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
clk_b => clk,
|
||||
en_a => en_a,
|
||||
en_b => en_b,
|
||||
we_a => we_a,
|
||||
we_b => we_b,
|
||||
addr_a => addr_a,
|
||||
addr_b => addr_b,
|
||||
din_a => din_a,
|
||||
din_b => din_a,
|
||||
dout_a => dout_a,
|
||||
dout_b => dout_b
|
||||
);
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,95 +1,95 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r2c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r2c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r2c;
|
||||
|
||||
architecture Behavioral of dpram_2w2r2c is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
signal addr_a_r : unsigned (addr_width-1 downto 0);
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
dout_a <= RAM(to_integer(addr_a_r));
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a, clk_b)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' and en_a = '1' and we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
elsif clk_b'event and clk_b = '1' and en_b = '1' and we_b = '1' then
|
||||
RAM(to_integer(addr_b)) <= din_b;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
addr_a_r <= addr_a;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r2c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r2c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r2c;
|
||||
|
||||
architecture Behavioral of dpram_2w2r2c is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
signal addr_a_r : unsigned (addr_width-1 downto 0);
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
dout_a <= RAM(to_integer(addr_a_r));
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a, clk_b)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' and en_a = '1' and we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
elsif clk_b'event and clk_b = '1' and en_b = '1' and we_b = '1' then
|
||||
RAM(to_integer(addr_b)) <= din_b;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
addr_a_r <= addr_a;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,93 +1,93 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r2c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r2c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r2c;
|
||||
|
||||
architecture Behavioral of dpram_2w2r2c is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
signal addr_a_r : unsigned (addr_width-1 downto 0);
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
dout_a <= RAM(to_integer(addr_a_r));
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
addr_a_r <= addr_a;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_2w2r2c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r2c is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r2c;
|
||||
|
||||
architecture Behavioral of dpram_2w2r2c is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
signal addr_a_r : unsigned (addr_width-1 downto 0);
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
dout_a <= RAM(to_integer(addr_a_r));
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
addr_a_r <= addr_a;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
+293
-293
@@ -1,293 +1,293 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.2 2010-03-13 11:06:43 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use work.async_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity flash_port_wb is
|
||||
Generic
|
||||
(
|
||||
f_sysclk : real := 100.0;
|
||||
addr_width : natural := 32;
|
||||
data_width : natural := 32;
|
||||
async_timespec : async_timespec_t
|
||||
);
|
||||
Port
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
port_bsyi : in std_logic;
|
||||
port_bsyo : out std_logic;
|
||||
port_a : out unsigned(addr_width-1 downto 0);
|
||||
port_di : in unsigned(data_width-1 downto 0);
|
||||
port_do : out unsigned(data_width-1 downto 0);
|
||||
port_d_drv : out STD_LOGIC;
|
||||
port_wr : out STD_LOGIC;
|
||||
port_rd : out STD_LOGIC;
|
||||
flash_cs : out std_logic;
|
||||
flash_rst : out std_logic
|
||||
);
|
||||
end flash_port_wb;
|
||||
|
||||
architecture Behavioral of flash_port_wb is
|
||||
|
||||
type async_t is record
|
||||
cs : std_logic;
|
||||
wr : std_logic;
|
||||
rd : std_logic;
|
||||
rst : std_logic;
|
||||
drive_d : std_logic;
|
||||
end record;
|
||||
|
||||
type async_state_t is (start, reset, idle, go, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
|
||||
|
||||
signal s, sn : async_state_t;
|
||||
signal as : async_t;
|
||||
signal ack : std_logic;
|
||||
signal cc_rst : std_logic;
|
||||
signal cycle_cnt : natural range 0 to 31;
|
||||
signal cycle_reload : natural range 0 to 31;
|
||||
signal rdy : std_logic;
|
||||
signal rdyo : std_logic;
|
||||
signal en : std_logic;
|
||||
signal we_reg : std_logic;
|
||||
signal data_reg : unsigned(data_width-1 downto 0);
|
||||
signal addr_reg : unsigned(addr_width-1 downto 0);
|
||||
|
||||
------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
SRDY_O <= CYC_I and rdyo;
|
||||
en <= CYC_I and STB_I;
|
||||
port_a <= addr_reg;
|
||||
port_do <= data_reg;
|
||||
port_d_drv <= as.drive_d;
|
||||
port_wr <= (not async_timespec.pol_we) xor as.wr;
|
||||
port_rd <= (not async_timespec.pol_oe) xor as.rd;
|
||||
|
||||
proc_cycle_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if cc_rst = '1' then
|
||||
cycle_cnt <= cycle_reload;
|
||||
elsif cycle_cnt /= 0 then
|
||||
cycle_cnt <= cycle_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
proc_state_next:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
s <= start;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_state:
|
||||
process(s, cycle_cnt, en, we_reg, port_bsyi)
|
||||
begin
|
||||
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
|
||||
cc_rst <= '0';
|
||||
as.rst <= '0';
|
||||
as.cs <= '0';
|
||||
as.wr <= '0';
|
||||
as.rd <= '0';
|
||||
as.drive_d <= '0';
|
||||
ack <= '0';
|
||||
rdy <= '0';
|
||||
port_bsyo <= '1';
|
||||
|
||||
sn <= s;
|
||||
case s is
|
||||
|
||||
when start =>
|
||||
cc_rst <= '1';
|
||||
sn <= reset;
|
||||
when reset =>
|
||||
as.rst <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
sn <= idle;
|
||||
end if;
|
||||
when idle =>
|
||||
port_bsyo <= '0';
|
||||
rdy <= '1';
|
||||
if en = '1' then
|
||||
sn <= go;
|
||||
end if;
|
||||
when go =>
|
||||
port_bsyo <= '0';
|
||||
if port_bsyi = '0' then
|
||||
as.cs <= '1';
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk)-1;
|
||||
if we_reg = '0' then
|
||||
sn <= leadin_rd;
|
||||
else
|
||||
sn <= leadin_wr;
|
||||
end if;
|
||||
end if;
|
||||
when leadin_rd =>
|
||||
as.cs <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk)-1;
|
||||
as.rd <= '1';
|
||||
sn <= read;
|
||||
end if;
|
||||
|
||||
when leadin_wr =>
|
||||
as.cs <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk)-1;
|
||||
as.wr <= '1';
|
||||
as.drive_d <= '1';
|
||||
sn <= write;
|
||||
end if;
|
||||
|
||||
when read =>
|
||||
as.cs <= '1';
|
||||
as.rd <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
|
||||
-- as.rd <= '0';
|
||||
sn <= leadout_rd;
|
||||
ack <= '1';
|
||||
end if;
|
||||
|
||||
when write =>
|
||||
as.drive_d <= '1';
|
||||
as.cs <= '1';
|
||||
as.wr <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
as.wr <= '0';
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
|
||||
sn <= leadout_wr;
|
||||
-- ack <= '1';
|
||||
end if;
|
||||
|
||||
when leadout_rd =>
|
||||
as.cs <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
|
||||
sn <= release;
|
||||
as.cs <= '0';
|
||||
end if;
|
||||
|
||||
when leadout_wr =>
|
||||
as.cs <= '1';
|
||||
as.drive_d <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
|
||||
sn <= release;
|
||||
as.cs <= '0';
|
||||
end if;
|
||||
|
||||
when release =>
|
||||
if cycle_cnt = 0 then
|
||||
sn <= idle;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
sn <= idle;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_ctrl:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
flash_cs <= (not async_timespec.pol_cs) xor as.cs;
|
||||
flash_rst <= (not async_timespec.pol_rst) xor as.rst;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
din_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if as.rd = '1' then
|
||||
DAT_O(data_width-1 downto 0) <= port_di;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
data_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if en = '1' and rdy = '1' then
|
||||
we_reg <= WE_I;
|
||||
data_reg <= DAT_I(data_width-1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
addr_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if en = '1' and rdy = '1' then
|
||||
addr_reg <= ADDR_I(addr_width-1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_SRDY:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
rdyo <= '1';
|
||||
elsif en = '1' then
|
||||
rdyo <= rdy and not rdyo;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_ACK:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
ACK_O <= '0';
|
||||
else
|
||||
ACK_O <= ack;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.2 2010/03/13 11:06:43 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use work.async_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity flash_port_wb is
|
||||
Generic
|
||||
(
|
||||
f_sysclk : real := 100.0;
|
||||
addr_width : natural := 32;
|
||||
data_width : natural := 32;
|
||||
async_timespec : async_timespec_t
|
||||
);
|
||||
Port
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
port_bsyi : in std_logic;
|
||||
port_bsyo : out std_logic;
|
||||
port_a : out unsigned(addr_width-1 downto 0);
|
||||
port_di : in unsigned(data_width-1 downto 0);
|
||||
port_do : out unsigned(data_width-1 downto 0);
|
||||
port_d_drv : out STD_LOGIC;
|
||||
port_wr : out STD_LOGIC;
|
||||
port_rd : out STD_LOGIC;
|
||||
flash_cs : out std_logic;
|
||||
flash_rst : out std_logic
|
||||
);
|
||||
end flash_port_wb;
|
||||
|
||||
architecture Behavioral of flash_port_wb is
|
||||
|
||||
type async_t is record
|
||||
cs : std_logic;
|
||||
wr : std_logic;
|
||||
rd : std_logic;
|
||||
rst : std_logic;
|
||||
drive_d : std_logic;
|
||||
end record;
|
||||
|
||||
type async_state_t is (start, reset, idle, go, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
|
||||
|
||||
signal s, sn : async_state_t;
|
||||
signal as : async_t;
|
||||
signal ack : std_logic;
|
||||
signal cc_rst : std_logic;
|
||||
signal cycle_cnt : natural range 0 to 31;
|
||||
signal cycle_reload : natural range 0 to 31;
|
||||
signal rdy : std_logic;
|
||||
signal rdyo : std_logic;
|
||||
signal en : std_logic;
|
||||
signal we_reg : std_logic;
|
||||
signal data_reg : unsigned(data_width-1 downto 0);
|
||||
signal addr_reg : unsigned(addr_width-1 downto 0);
|
||||
|
||||
------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
SRDY_O <= CYC_I and rdyo;
|
||||
en <= CYC_I and STB_I;
|
||||
port_a <= addr_reg;
|
||||
port_do <= data_reg;
|
||||
port_d_drv <= as.drive_d;
|
||||
port_wr <= (not async_timespec.pol_we) xor as.wr;
|
||||
port_rd <= (not async_timespec.pol_oe) xor as.rd;
|
||||
|
||||
proc_cycle_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if cc_rst = '1' then
|
||||
cycle_cnt <= cycle_reload;
|
||||
elsif cycle_cnt /= 0 then
|
||||
cycle_cnt <= cycle_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
proc_state_next:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
s <= start;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_state:
|
||||
process(s, cycle_cnt, en, we_reg, port_bsyi)
|
||||
begin
|
||||
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
|
||||
cc_rst <= '0';
|
||||
as.rst <= '0';
|
||||
as.cs <= '0';
|
||||
as.wr <= '0';
|
||||
as.rd <= '0';
|
||||
as.drive_d <= '0';
|
||||
ack <= '0';
|
||||
rdy <= '0';
|
||||
port_bsyo <= '1';
|
||||
|
||||
sn <= s;
|
||||
case s is
|
||||
|
||||
when start =>
|
||||
cc_rst <= '1';
|
||||
sn <= reset;
|
||||
when reset =>
|
||||
as.rst <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
sn <= idle;
|
||||
end if;
|
||||
when idle =>
|
||||
port_bsyo <= '0';
|
||||
rdy <= '1';
|
||||
if en = '1' then
|
||||
sn <= go;
|
||||
end if;
|
||||
when go =>
|
||||
port_bsyo <= '0';
|
||||
if port_bsyi = '0' then
|
||||
as.cs <= '1';
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk)-1;
|
||||
if we_reg = '0' then
|
||||
sn <= leadin_rd;
|
||||
else
|
||||
sn <= leadin_wr;
|
||||
end if;
|
||||
end if;
|
||||
when leadin_rd =>
|
||||
as.cs <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk)-1;
|
||||
as.rd <= '1';
|
||||
sn <= read;
|
||||
end if;
|
||||
|
||||
when leadin_wr =>
|
||||
as.cs <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk)-1;
|
||||
as.wr <= '1';
|
||||
as.drive_d <= '1';
|
||||
sn <= write;
|
||||
end if;
|
||||
|
||||
when read =>
|
||||
as.cs <= '1';
|
||||
as.rd <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
|
||||
-- as.rd <= '0';
|
||||
sn <= leadout_rd;
|
||||
ack <= '1';
|
||||
end if;
|
||||
|
||||
when write =>
|
||||
as.drive_d <= '1';
|
||||
as.cs <= '1';
|
||||
as.wr <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
as.wr <= '0';
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
|
||||
sn <= leadout_wr;
|
||||
-- ack <= '1';
|
||||
end if;
|
||||
|
||||
when leadout_rd =>
|
||||
as.cs <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
|
||||
sn <= release;
|
||||
as.cs <= '0';
|
||||
end if;
|
||||
|
||||
when leadout_wr =>
|
||||
as.cs <= '1';
|
||||
as.drive_d <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
|
||||
sn <= release;
|
||||
as.cs <= '0';
|
||||
end if;
|
||||
|
||||
when release =>
|
||||
if cycle_cnt = 0 then
|
||||
sn <= idle;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
sn <= idle;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_ctrl:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
flash_cs <= (not async_timespec.pol_cs) xor as.cs;
|
||||
flash_rst <= (not async_timespec.pol_rst) xor as.rst;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
din_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if as.rd = '1' then
|
||||
DAT_O(data_width-1 downto 0) <= port_di;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
data_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if en = '1' and rdy = '1' then
|
||||
we_reg <= WE_I;
|
||||
data_reg <= DAT_I(data_width-1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
addr_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if en = '1' and rdy = '1' then
|
||||
addr_reg <= ADDR_I(addr_width-1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_SRDY:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
rdyo <= '1';
|
||||
elsif en = '1' then
|
||||
rdyo <= rdy and not rdyo;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_ACK:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
ACK_O <= '0';
|
||||
else
|
||||
ACK_O <= ack;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
|
||||
+69
-69
@@ -1,69 +1,69 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity lcd_port is
|
||||
Port (
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
din : in unsigned(7 downto 0);
|
||||
dout : out unsigned(7 downto 0);
|
||||
lcd_d : inout unsigned(3 downto 0);
|
||||
lcd_e : out std_logic;
|
||||
lcd_rs : out std_logic;
|
||||
lcd_rw : out std_logic
|
||||
);
|
||||
end lcd_port;
|
||||
|
||||
architecture Behavioral of lcd_port is
|
||||
|
||||
constant clcd_e : integer := 7;
|
||||
constant clcd_rs : integer := 6;
|
||||
constant clcd_rw : integer := 5;
|
||||
|
||||
type lcd_t is record
|
||||
d : unsigned(3 downto 0);
|
||||
e : std_logic;
|
||||
rs : std_logic;
|
||||
rw : std_logic;
|
||||
end record;
|
||||
|
||||
------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
proc_lcd_port:
|
||||
process(rst, clk)
|
||||
variable vlcd : lcd_t;
|
||||
begin
|
||||
if (rst = '1') then
|
||||
dout <= (others => '0');
|
||||
vlcd.d := (others => '0');
|
||||
vlcd.e := '0';
|
||||
vlcd.rw := '1';
|
||||
vlcd.rs := '0';
|
||||
elsif rising_edge(clk) then
|
||||
dout <= unsigned("0000" & lcd_d);
|
||||
if we = '1' then
|
||||
vlcd.d := din(3 downto 0);
|
||||
vlcd.e := din(clcd_e);
|
||||
vlcd.rs := din(clcd_rs);
|
||||
vlcd.rw := din(clcd_rw);
|
||||
end if;
|
||||
end if;
|
||||
if vlcd.rw = '0' then
|
||||
lcd_d <= unsigned(vlcd.d);
|
||||
else
|
||||
lcd_d <= (others => 'Z');
|
||||
end if;
|
||||
lcd_e <= vlcd.e;
|
||||
lcd_rs <= vlcd.rs;
|
||||
lcd_rw <= vlcd.rw;
|
||||
end process;
|
||||
------------------------------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity lcd_port is
|
||||
Port (
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
din : in unsigned(7 downto 0);
|
||||
dout : out unsigned(7 downto 0);
|
||||
lcd_d : inout unsigned(3 downto 0);
|
||||
lcd_e : out std_logic;
|
||||
lcd_rs : out std_logic;
|
||||
lcd_rw : out std_logic
|
||||
);
|
||||
end lcd_port;
|
||||
|
||||
architecture Behavioral of lcd_port is
|
||||
|
||||
constant clcd_e : integer := 7;
|
||||
constant clcd_rs : integer := 6;
|
||||
constant clcd_rw : integer := 5;
|
||||
|
||||
type lcd_t is record
|
||||
d : unsigned(3 downto 0);
|
||||
e : std_logic;
|
||||
rs : std_logic;
|
||||
rw : std_logic;
|
||||
end record;
|
||||
|
||||
------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
proc_lcd_port:
|
||||
process(rst, clk)
|
||||
variable vlcd : lcd_t;
|
||||
begin
|
||||
if (rst = '1') then
|
||||
dout <= (others => '0');
|
||||
vlcd.d := (others => '0');
|
||||
vlcd.e := '0';
|
||||
vlcd.rw := '1';
|
||||
vlcd.rs := '0';
|
||||
elsif rising_edge(clk) then
|
||||
dout <= unsigned("0000" & lcd_d);
|
||||
if we = '1' then
|
||||
vlcd.d := din(3 downto 0);
|
||||
vlcd.e := din(clcd_e);
|
||||
vlcd.rs := din(clcd_rs);
|
||||
vlcd.rw := din(clcd_rw);
|
||||
end if;
|
||||
end if;
|
||||
if vlcd.rw = '0' then
|
||||
lcd_d <= unsigned(vlcd.d);
|
||||
else
|
||||
lcd_d <= (others => 'Z');
|
||||
end if;
|
||||
lcd_e <= vlcd.e;
|
||||
lcd_rs <= vlcd.rs;
|
||||
lcd_rw <= vlcd.rw;
|
||||
end process;
|
||||
------------------------------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
|
||||
+223
-223
@@ -1,223 +1,223 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 21:52:19 10/22/05
|
||||
-- Design Name:
|
||||
-- Module Name: oneshot - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
-- Component Template
|
||||
--
|
||||
-- COMPONENT oneshot
|
||||
-- GENERIC (mode : integer);
|
||||
-- PORT(
|
||||
-- rst : IN std_logic;
|
||||
-- clk : IN std_logic;
|
||||
-- input : IN std_logic;
|
||||
-- output : OUT std_logic
|
||||
-- );
|
||||
-- END COMPONENT;
|
||||
--
|
||||
-- Instantation Template
|
||||
--
|
||||
-- oneshot_int: oneshot
|
||||
-- GENERIC MAP (
|
||||
-- mode => 1)
|
||||
-- PORT MAP(
|
||||
-- rst => ,
|
||||
-- clk => ,
|
||||
-- input => ,
|
||||
-- output =>
|
||||
-- );
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity oneshot is
|
||||
Generic ( mode : integer range 0 to 2 := 1);
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
input : in std_logic;
|
||||
output : out std_logic);
|
||||
end oneshot;
|
||||
|
||||
architecture Behavioral of oneshot is
|
||||
|
||||
type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st);
|
||||
|
||||
signal shot_cs : shot_state_t;
|
||||
signal shot_ns : shot_state_t;
|
||||
|
||||
begin
|
||||
|
||||
mode_0:
|
||||
if mode = 0 generate
|
||||
begin
|
||||
shot_clk: process(rst, clk, shot_ns, input)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
if (input = '1') then
|
||||
shot_cs <= release_pos_st;
|
||||
else
|
||||
shot_cs <= release_neg_st;
|
||||
end if;
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
shot_cs <= shot_ns;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
shot_in: process(rst, clk, input, shot_cs)
|
||||
begin
|
||||
shot_ns <= shot_cs;
|
||||
case shot_cs is
|
||||
when release_pos_st =>
|
||||
if (input = '0') then
|
||||
shot_ns <= shot_neg_st;
|
||||
end if;
|
||||
when shot_neg_st =>
|
||||
shot_ns <= release_neg_st;
|
||||
when release_neg_st =>
|
||||
if (input = '1') then
|
||||
shot_ns <= release_pos_st;
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
shot_out: process(shot_cs)
|
||||
begin
|
||||
output <= '0';
|
||||
case shot_cs is
|
||||
when shot_pos_st =>
|
||||
output <= '1';
|
||||
when shot_neg_st =>
|
||||
output <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
mode_1:
|
||||
if mode = 1 generate
|
||||
begin
|
||||
shot_clk: process(rst, clk, shot_ns, input)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
if (input = '1') then
|
||||
shot_cs <= release_pos_st;
|
||||
else
|
||||
shot_cs <= release_neg_st;
|
||||
end if;
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
shot_cs <= shot_ns;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
shot_in: process(rst, clk, input, shot_cs)
|
||||
begin
|
||||
shot_ns <= shot_cs;
|
||||
case shot_cs is
|
||||
when shot_pos_st =>
|
||||
shot_ns <= release_pos_st;
|
||||
when release_pos_st =>
|
||||
if (input = '0') then
|
||||
shot_ns <= release_neg_st;
|
||||
end if;
|
||||
when release_neg_st =>
|
||||
if (input = '1') then
|
||||
shot_ns <= shot_pos_st;
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
shot_out: process(shot_cs)
|
||||
begin
|
||||
output <= '0';
|
||||
case shot_cs is
|
||||
when shot_pos_st =>
|
||||
output <= '1';
|
||||
when shot_neg_st =>
|
||||
output <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
mode_2:
|
||||
if mode = 2 generate
|
||||
begin
|
||||
shot_clk: process(rst, clk, shot_ns, input)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
if (input = '1') then
|
||||
shot_cs <= release_pos_st;
|
||||
else
|
||||
shot_cs <= release_neg_st;
|
||||
end if;
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
shot_cs <= shot_ns;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
shot_in: process(rst, clk, input, shot_cs)
|
||||
begin
|
||||
shot_ns <= shot_cs;
|
||||
case shot_cs is
|
||||
when shot_pos_st =>
|
||||
shot_ns <= release_pos_st;
|
||||
when release_pos_st =>
|
||||
if (input = '0') then
|
||||
shot_ns <= shot_neg_st;
|
||||
end if;
|
||||
when shot_neg_st =>
|
||||
shot_ns <= release_neg_st;
|
||||
when release_neg_st =>
|
||||
if (input = '1') then
|
||||
shot_ns <= shot_pos_st;
|
||||
end if;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
shot_out: process(shot_cs)
|
||||
begin
|
||||
output <= '0';
|
||||
case shot_cs is
|
||||
when shot_pos_st =>
|
||||
output <= '1';
|
||||
when shot_neg_st =>
|
||||
output <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
end Behavioral;
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 21:52:19 10/22/05
|
||||
-- Design Name:
|
||||
-- Module Name: oneshot - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
-- Component Template
|
||||
--
|
||||
-- COMPONENT oneshot
|
||||
-- GENERIC (mode : integer);
|
||||
-- PORT(
|
||||
-- rst : IN std_logic;
|
||||
-- clk : IN std_logic;
|
||||
-- input : IN std_logic;
|
||||
-- output : OUT std_logic
|
||||
-- );
|
||||
-- END COMPONENT;
|
||||
--
|
||||
-- Instantation Template
|
||||
--
|
||||
-- oneshot_int: oneshot
|
||||
-- GENERIC MAP (
|
||||
-- mode => 1)
|
||||
-- PORT MAP(
|
||||
-- rst => ,
|
||||
-- clk => ,
|
||||
-- input => ,
|
||||
-- output =>
|
||||
-- );
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity oneshot is
|
||||
Generic ( mode : integer range 0 to 2 := 1);
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
input : in std_logic;
|
||||
output : out std_logic);
|
||||
end oneshot;
|
||||
|
||||
architecture Behavioral of oneshot is
|
||||
|
||||
type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st);
|
||||
|
||||
signal shot_cs : shot_state_t;
|
||||
signal shot_ns : shot_state_t;
|
||||
|
||||
begin
|
||||
|
||||
mode_0:
|
||||
if mode = 0 generate
|
||||
begin
|
||||
shot_clk: process(rst, clk, shot_ns, input)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
if (input = '1') then
|
||||
shot_cs <= release_pos_st;
|
||||
else
|
||||
shot_cs <= release_neg_st;
|
||||
end if;
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
shot_cs <= shot_ns;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
shot_in: process(rst, clk, input, shot_cs)
|
||||
begin
|
||||
shot_ns <= shot_cs;
|
||||
case shot_cs is
|
||||
when release_pos_st =>
|
||||
if (input = '0') then
|
||||
shot_ns <= shot_neg_st;
|
||||
end if;
|
||||
when shot_neg_st =>
|
||||
shot_ns <= release_neg_st;
|
||||
when release_neg_st =>
|
||||
if (input = '1') then
|
||||
shot_ns <= release_pos_st;
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
shot_out: process(shot_cs)
|
||||
begin
|
||||
output <= '0';
|
||||
case shot_cs is
|
||||
when shot_pos_st =>
|
||||
output <= '1';
|
||||
when shot_neg_st =>
|
||||
output <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
mode_1:
|
||||
if mode = 1 generate
|
||||
begin
|
||||
shot_clk: process(rst, clk, shot_ns, input)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
if (input = '1') then
|
||||
shot_cs <= release_pos_st;
|
||||
else
|
||||
shot_cs <= release_neg_st;
|
||||
end if;
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
shot_cs <= shot_ns;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
shot_in: process(rst, clk, input, shot_cs)
|
||||
begin
|
||||
shot_ns <= shot_cs;
|
||||
case shot_cs is
|
||||
when shot_pos_st =>
|
||||
shot_ns <= release_pos_st;
|
||||
when release_pos_st =>
|
||||
if (input = '0') then
|
||||
shot_ns <= release_neg_st;
|
||||
end if;
|
||||
when release_neg_st =>
|
||||
if (input = '1') then
|
||||
shot_ns <= shot_pos_st;
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
shot_out: process(shot_cs)
|
||||
begin
|
||||
output <= '0';
|
||||
case shot_cs is
|
||||
when shot_pos_st =>
|
||||
output <= '1';
|
||||
when shot_neg_st =>
|
||||
output <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
mode_2:
|
||||
if mode = 2 generate
|
||||
begin
|
||||
shot_clk: process(rst, clk, shot_ns, input)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
if (input = '1') then
|
||||
shot_cs <= release_pos_st;
|
||||
else
|
||||
shot_cs <= release_neg_st;
|
||||
end if;
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
shot_cs <= shot_ns;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
shot_in: process(rst, clk, input, shot_cs)
|
||||
begin
|
||||
shot_ns <= shot_cs;
|
||||
case shot_cs is
|
||||
when shot_pos_st =>
|
||||
shot_ns <= release_pos_st;
|
||||
when release_pos_st =>
|
||||
if (input = '0') then
|
||||
shot_ns <= shot_neg_st;
|
||||
end if;
|
||||
when shot_neg_st =>
|
||||
shot_ns <= release_neg_st;
|
||||
when release_neg_st =>
|
||||
if (input = '1') then
|
||||
shot_ns <= shot_pos_st;
|
||||
end if;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
shot_out: process(shot_cs)
|
||||
begin
|
||||
output <= '0';
|
||||
case shot_cs is
|
||||
when shot_pos_st =>
|
||||
output <= '1';
|
||||
when shot_neg_st =>
|
||||
output <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
+18
-18
@@ -1,18 +1,18 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package template_pkg is
|
||||
-- Constants
|
||||
-- Types
|
||||
-- Functions
|
||||
|
||||
end template_pkg;
|
||||
|
||||
package body template_pkg is
|
||||
|
||||
end template_pkg;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package template_pkg is
|
||||
-- Constants
|
||||
-- Types
|
||||
-- Functions
|
||||
|
||||
end template_pkg;
|
||||
|
||||
package body template_pkg is
|
||||
|
||||
end template_pkg;
|
||||
|
||||
|
||||
+155
-155
@@ -1,155 +1,155 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 21:52:19 10/22/05
|
||||
-- Design Name:
|
||||
-- Module Name: singleshot - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
-- Component Template
|
||||
--
|
||||
-- COMPONENT singleshot
|
||||
-- GENERIC (mode : integer);
|
||||
-- PORT(
|
||||
-- rst : IN std_logic;
|
||||
-- clk : IN std_logic;
|
||||
-- input : IN std_logic;
|
||||
-- output : OUT std_logic
|
||||
-- );
|
||||
-- END COMPONENT;
|
||||
--
|
||||
-- Instantation Template
|
||||
--
|
||||
-- singleshot_int: oneshot
|
||||
-- GENERIC MAP (
|
||||
-- mode => 1)
|
||||
-- PORT MAP(
|
||||
-- rst => ,
|
||||
-- clk => ,
|
||||
-- input => ,
|
||||
-- output =>
|
||||
-- );
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity singleshot is
|
||||
Generic ( mode : integer range 0 to 2 := 1);
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
input : in std_logic;
|
||||
output : out std_logic);
|
||||
end singleshot;
|
||||
|
||||
architecture Behavioral of singleshot is
|
||||
|
||||
type s_t is (idle, shot_in, active, shot_out);
|
||||
signal s, sn : s_t;
|
||||
|
||||
begin
|
||||
|
||||
process (rst, clk, sn)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
s <= idle;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
mode_1:
|
||||
if mode = 1 generate
|
||||
begin
|
||||
process (input, s)
|
||||
begin
|
||||
output <= '0';
|
||||
sn <= s;
|
||||
case s is
|
||||
when idle =>
|
||||
if input = '1' then
|
||||
sn <= shot_in;
|
||||
end if;
|
||||
when shot_in =>
|
||||
output <= '1';
|
||||
sn <= active;
|
||||
when active =>
|
||||
if input = '0' then
|
||||
sn <= shot_out;
|
||||
end if;
|
||||
when shot_out =>
|
||||
sn <= idle;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
mode_0:
|
||||
if mode = 0 generate
|
||||
begin
|
||||
process (input, s)
|
||||
begin
|
||||
output <= '0';
|
||||
sn <= s;
|
||||
case s is
|
||||
when idle =>
|
||||
if input = '1' then
|
||||
sn <= shot_in;
|
||||
end if;
|
||||
when shot_in =>
|
||||
sn <= active;
|
||||
when active =>
|
||||
if input = '0' then
|
||||
sn <= shot_out;
|
||||
end if;
|
||||
when shot_out =>
|
||||
output <= '1';
|
||||
sn <= idle;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
mode_2:
|
||||
if mode = 2 generate
|
||||
begin
|
||||
process (input, s)
|
||||
begin
|
||||
output <= '0';
|
||||
sn <= s;
|
||||
case s is
|
||||
when idle =>
|
||||
if input = '1' then
|
||||
sn <= shot_in;
|
||||
end if;
|
||||
when shot_in =>
|
||||
output <= '1';
|
||||
sn <= active;
|
||||
when active =>
|
||||
if input = '0' then
|
||||
sn <= shot_out;
|
||||
end if;
|
||||
when shot_out =>
|
||||
output <= '1';
|
||||
sn <= idle;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
end Behavioral;
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 21:52:19 10/22/05
|
||||
-- Design Name:
|
||||
-- Module Name: singleshot - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
-- Component Template
|
||||
--
|
||||
-- COMPONENT singleshot
|
||||
-- GENERIC (mode : integer);
|
||||
-- PORT(
|
||||
-- rst : IN std_logic;
|
||||
-- clk : IN std_logic;
|
||||
-- input : IN std_logic;
|
||||
-- output : OUT std_logic
|
||||
-- );
|
||||
-- END COMPONENT;
|
||||
--
|
||||
-- Instantation Template
|
||||
--
|
||||
-- singleshot_int: oneshot
|
||||
-- GENERIC MAP (
|
||||
-- mode => 1)
|
||||
-- PORT MAP(
|
||||
-- rst => ,
|
||||
-- clk => ,
|
||||
-- input => ,
|
||||
-- output =>
|
||||
-- );
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity singleshot is
|
||||
Generic ( mode : integer range 0 to 2 := 1);
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
input : in std_logic;
|
||||
output : out std_logic);
|
||||
end singleshot;
|
||||
|
||||
architecture Behavioral of singleshot is
|
||||
|
||||
type s_t is (idle, shot_in, active, shot_out);
|
||||
signal s, sn : s_t;
|
||||
|
||||
begin
|
||||
|
||||
process (rst, clk, sn)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
s <= idle;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
mode_1:
|
||||
if mode = 1 generate
|
||||
begin
|
||||
process (input, s)
|
||||
begin
|
||||
output <= '0';
|
||||
sn <= s;
|
||||
case s is
|
||||
when idle =>
|
||||
if input = '1' then
|
||||
sn <= shot_in;
|
||||
end if;
|
||||
when shot_in =>
|
||||
output <= '1';
|
||||
sn <= active;
|
||||
when active =>
|
||||
if input = '0' then
|
||||
sn <= shot_out;
|
||||
end if;
|
||||
when shot_out =>
|
||||
sn <= idle;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
mode_0:
|
||||
if mode = 0 generate
|
||||
begin
|
||||
process (input, s)
|
||||
begin
|
||||
output <= '0';
|
||||
sn <= s;
|
||||
case s is
|
||||
when idle =>
|
||||
if input = '1' then
|
||||
sn <= shot_in;
|
||||
end if;
|
||||
when shot_in =>
|
||||
sn <= active;
|
||||
when active =>
|
||||
if input = '0' then
|
||||
sn <= shot_out;
|
||||
end if;
|
||||
when shot_out =>
|
||||
output <= '1';
|
||||
sn <= idle;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
mode_2:
|
||||
if mode = 2 generate
|
||||
begin
|
||||
process (input, s)
|
||||
begin
|
||||
output <= '0';
|
||||
sn <= s;
|
||||
case s is
|
||||
when idle =>
|
||||
if input = '1' then
|
||||
sn <= shot_in;
|
||||
end if;
|
||||
when shot_in =>
|
||||
output <= '1';
|
||||
sn <= active;
|
||||
when active =>
|
||||
if input = '0' then
|
||||
sn <= shot_out;
|
||||
end if;
|
||||
when shot_out =>
|
||||
output <= '1';
|
||||
sn <= idle;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
+63
-63
@@ -1,63 +1,63 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
-- LIBRARY WORK;
|
||||
-- USE.YOURLIB.WHATELSE
|
||||
|
||||
ENTITY tb_template IS
|
||||
END tb_template;
|
||||
|
||||
ARCHITECTURE behavior OF tb_template IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT your_comp
|
||||
GENERIC
|
||||
(
|
||||
);
|
||||
PORT
|
||||
(
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
--Inputs
|
||||
signal clk : STD_LOGIC := '0';
|
||||
|
||||
--Outputs
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: your_comp
|
||||
GENERIC MAP
|
||||
(
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END tb_template;
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
-- LIBRARY WORK;
|
||||
-- USE.YOURLIB.WHATELSE
|
||||
|
||||
ENTITY tb_template IS
|
||||
END tb_template;
|
||||
|
||||
ARCHITECTURE behavior OF tb_template IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT your_comp
|
||||
GENERIC
|
||||
(
|
||||
);
|
||||
PORT
|
||||
(
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
--Inputs
|
||||
signal clk : STD_LOGIC := '0';
|
||||
|
||||
--Outputs
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: your_comp
|
||||
GENERIC MAP
|
||||
(
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END tb_template;
|
||||
|
||||
+196
-196
@@ -1,196 +1,196 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.6 2010-03-22 07:25:40 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
|
||||
package utils_pkg is
|
||||
|
||||
-- Constants
|
||||
|
||||
-- Functions
|
||||
function MIN (X, Y: INTEGER) return INTEGER;
|
||||
function MAX (X, Y: INTEGER) return INTEGER;
|
||||
|
||||
function NextPowerOfTwo(x : real) return real;
|
||||
function NextExpBaseTwo(x : real) return real;
|
||||
function NextPowerOfTwo(x : natural) return natural;
|
||||
function NextExpBaseTwo(x : natural) return natural;
|
||||
function GCD(a, b : natural) return natural;
|
||||
function LCM(a, b : natural) return natural;
|
||||
function UTILS_PERIOD_NS(f_in_MHz : real) return real;
|
||||
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural;
|
||||
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural;
|
||||
function f_correct(f : real) return natural;
|
||||
|
||||
end utils_pkg;
|
||||
|
||||
|
||||
package body utils_pkg is
|
||||
|
||||
-------------------------------------------------------------
|
||||
function MIN (X, Y: INTEGER) return INTEGER is
|
||||
variable res : integer := X;
|
||||
begin
|
||||
if Y < X then
|
||||
res := Y;
|
||||
end if;
|
||||
|
||||
return res;
|
||||
|
||||
end MIN;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function MAX (X, Y: INTEGER) return INTEGER is
|
||||
variable res : integer := X;
|
||||
begin
|
||||
if Y > X then
|
||||
res := Y;
|
||||
end if;
|
||||
|
||||
return res;
|
||||
|
||||
end MAX;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function NextExpBaseTwo(x : real) return real is
|
||||
begin
|
||||
return ceil(log2(x));
|
||||
end NextExpBaseTwo;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function NextPowerOfTwo(x : real) return real is
|
||||
begin
|
||||
|
||||
return 2.0**NextExpBaseTwo(x);
|
||||
end NextPowerOfTwo;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function NextExpBaseTwo(x : natural) return natural is
|
||||
begin
|
||||
return natural(NextExpBaseTwo(real(x)));
|
||||
end NextExpBaseTwo;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function NextPowerOfTwo(x : natural) return natural is
|
||||
begin
|
||||
|
||||
return 2**NextExpBaseTwo(x);
|
||||
end NextPowerOfTwo;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function GCD(a, b : natural) return natural is
|
||||
variable aa : natural;
|
||||
variable bb : natural;
|
||||
begin
|
||||
aa := a;
|
||||
bb := b;
|
||||
while bb /= 0 loop
|
||||
if aa > bb then
|
||||
aa := aa - bb;
|
||||
else
|
||||
bb := bb - aa;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
return aa;
|
||||
|
||||
end GCD;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function LCM(a, b : natural) return natural is
|
||||
begin
|
||||
|
||||
return (a * b)/GCD(a, b);
|
||||
|
||||
end LCM;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function UTILS_PERIOD_NS(f_in_MHz : real) return real is
|
||||
begin
|
||||
|
||||
return 1.0E3/f_in_MHz;
|
||||
|
||||
end UTILS_PERIOD_NS;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural is
|
||||
variable f_in : natural;
|
||||
variable f_out : natural;
|
||||
variable C : natural;
|
||||
variable M : natural;
|
||||
variable D : natural;
|
||||
begin
|
||||
C := f_correct(f_out_MHz);
|
||||
if C < 2 then
|
||||
C := f_correct(f_in_MHz);
|
||||
end if;
|
||||
|
||||
f_out := natural(ceil(real(C)*f_out_MHz));
|
||||
f_in := natural(ceil(real(C)*f_in_MHz));
|
||||
|
||||
M := LCM(f_in, f_out)/f_in;
|
||||
D := f_in/GCD(f_in, f_out);
|
||||
|
||||
assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
|
||||
|
||||
if M = 1 then
|
||||
M := 2;
|
||||
end if;
|
||||
|
||||
return M;
|
||||
|
||||
end UTILS_FREQ_M;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural is
|
||||
variable f_in : natural;
|
||||
variable f_out : natural;
|
||||
variable C : natural;
|
||||
variable M : natural;
|
||||
variable D : natural;
|
||||
begin
|
||||
C := f_correct(f_out_MHz);
|
||||
if C < 2 then
|
||||
C := f_correct(f_in_MHz);
|
||||
end if;
|
||||
|
||||
f_out := natural(ceil(real(C)*f_out_MHz));
|
||||
f_in := natural(ceil(real(C)*f_in_MHz));
|
||||
|
||||
M := LCM(f_in, f_out)/f_in;
|
||||
D := f_in/GCD(f_in, f_out);
|
||||
|
||||
assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
|
||||
|
||||
if M = 1 then
|
||||
D := 2*D;
|
||||
end if;
|
||||
|
||||
return D;
|
||||
|
||||
end UTILS_FREQ_D;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function f_correct(f : real) return natural is
|
||||
constant MAX_ITER : positive := 100;
|
||||
constant MAX_ERR : real := 0.01;
|
||||
variable fpart : real;
|
||||
variable err : real;
|
||||
begin
|
||||
for i in 1 to MAX_ITER loop
|
||||
fpart := real(i)*f - ceil(real(i)*f);
|
||||
err := abs(fpart);
|
||||
if err < max_err then
|
||||
return i;
|
||||
end if;
|
||||
end loop;
|
||||
end f_correct;
|
||||
|
||||
-------------------------------------------------------------
|
||||
end utils_pkg;
|
||||
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.6 2010/03/22 07:25:40 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
|
||||
package utils_pkg is
|
||||
|
||||
-- Constants
|
||||
|
||||
-- Functions
|
||||
function MIN (X, Y: INTEGER) return INTEGER;
|
||||
function MAX (X, Y: INTEGER) return INTEGER;
|
||||
|
||||
function NextPowerOfTwo(x : real) return real;
|
||||
function NextExpBaseTwo(x : real) return real;
|
||||
function NextPowerOfTwo(x : natural) return natural;
|
||||
function NextExpBaseTwo(x : natural) return natural;
|
||||
function GCD(a, b : natural) return natural;
|
||||
function LCM(a, b : natural) return natural;
|
||||
function UTILS_PERIOD_NS(f_in_MHz : real) return real;
|
||||
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural;
|
||||
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural;
|
||||
function f_correct(f : real) return natural;
|
||||
|
||||
end utils_pkg;
|
||||
|
||||
|
||||
package body utils_pkg is
|
||||
|
||||
-------------------------------------------------------------
|
||||
function MIN (X, Y: INTEGER) return INTEGER is
|
||||
variable res : integer := X;
|
||||
begin
|
||||
if Y < X then
|
||||
res := Y;
|
||||
end if;
|
||||
|
||||
return res;
|
||||
|
||||
end MIN;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function MAX (X, Y: INTEGER) return INTEGER is
|
||||
variable res : integer := X;
|
||||
begin
|
||||
if Y > X then
|
||||
res := Y;
|
||||
end if;
|
||||
|
||||
return res;
|
||||
|
||||
end MAX;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function NextExpBaseTwo(x : real) return real is
|
||||
begin
|
||||
return ceil(log2(x));
|
||||
end NextExpBaseTwo;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function NextPowerOfTwo(x : real) return real is
|
||||
begin
|
||||
|
||||
return 2.0**NextExpBaseTwo(x);
|
||||
end NextPowerOfTwo;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function NextExpBaseTwo(x : natural) return natural is
|
||||
begin
|
||||
return natural(NextExpBaseTwo(real(x)));
|
||||
end NextExpBaseTwo;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function NextPowerOfTwo(x : natural) return natural is
|
||||
begin
|
||||
|
||||
return 2**NextExpBaseTwo(x);
|
||||
end NextPowerOfTwo;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function GCD(a, b : natural) return natural is
|
||||
variable aa : natural;
|
||||
variable bb : natural;
|
||||
begin
|
||||
aa := a;
|
||||
bb := b;
|
||||
while bb /= 0 loop
|
||||
if aa > bb then
|
||||
aa := aa - bb;
|
||||
else
|
||||
bb := bb - aa;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
return aa;
|
||||
|
||||
end GCD;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function LCM(a, b : natural) return natural is
|
||||
begin
|
||||
|
||||
return (a * b)/GCD(a, b);
|
||||
|
||||
end LCM;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function UTILS_PERIOD_NS(f_in_MHz : real) return real is
|
||||
begin
|
||||
|
||||
return 1.0E3/f_in_MHz;
|
||||
|
||||
end UTILS_PERIOD_NS;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural is
|
||||
variable f_in : natural;
|
||||
variable f_out : natural;
|
||||
variable C : natural;
|
||||
variable M : natural;
|
||||
variable D : natural;
|
||||
begin
|
||||
C := f_correct(f_out_MHz);
|
||||
if C < 2 then
|
||||
C := f_correct(f_in_MHz);
|
||||
end if;
|
||||
|
||||
f_out := natural(ceil(real(C)*f_out_MHz));
|
||||
f_in := natural(ceil(real(C)*f_in_MHz));
|
||||
|
||||
M := LCM(f_in, f_out)/f_in;
|
||||
D := f_in/GCD(f_in, f_out);
|
||||
|
||||
assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
|
||||
|
||||
if M = 1 then
|
||||
M := 2;
|
||||
end if;
|
||||
|
||||
return M;
|
||||
|
||||
end UTILS_FREQ_M;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural is
|
||||
variable f_in : natural;
|
||||
variable f_out : natural;
|
||||
variable C : natural;
|
||||
variable M : natural;
|
||||
variable D : natural;
|
||||
begin
|
||||
C := f_correct(f_out_MHz);
|
||||
if C < 2 then
|
||||
C := f_correct(f_in_MHz);
|
||||
end if;
|
||||
|
||||
f_out := natural(ceil(real(C)*f_out_MHz));
|
||||
f_in := natural(ceil(real(C)*f_in_MHz));
|
||||
|
||||
M := LCM(f_in, f_out)/f_in;
|
||||
D := f_in/GCD(f_in, f_out);
|
||||
|
||||
assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
|
||||
|
||||
if M = 1 then
|
||||
D := 2*D;
|
||||
end if;
|
||||
|
||||
return D;
|
||||
|
||||
end UTILS_FREQ_D;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function f_correct(f : real) return natural is
|
||||
constant MAX_ITER : positive := 100;
|
||||
constant MAX_ERR : real := 0.01;
|
||||
variable fpart : real;
|
||||
variable err : real;
|
||||
begin
|
||||
for i in 1 to MAX_ITER loop
|
||||
fpart := real(i)*f - ceil(real(i)*f);
|
||||
err := abs(fpart);
|
||||
if err < max_err then
|
||||
return i;
|
||||
end if;
|
||||
end loop;
|
||||
end f_correct;
|
||||
|
||||
-------------------------------------------------------------
|
||||
end utils_pkg;
|
||||
|
||||
|
||||
|
||||
+462
-419
@@ -1,419 +1,462 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_nco
|
||||
-- Module Name: tb_nco.vhd
|
||||
-- Project Name: nco
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library ieee_proposed;
|
||||
use ieee_proposed.math_utility_pkg.all;
|
||||
use ieee_proposed.fixed_pkg.all;
|
||||
|
||||
library altera;
|
||||
use altera.altera_syn_attributes.all;
|
||||
|
||||
library work;
|
||||
use work.fixed_util_pkg.all;
|
||||
|
||||
ENTITY syn_ddc IS
|
||||
Generic
|
||||
(
|
||||
nbits_in : integer := 16;
|
||||
nbits_in_frac : integer := 14;
|
||||
nbits_out : integer := 32;
|
||||
nbits_out_frac : integer := 30;
|
||||
lo_nbits_phase : integer := 24;
|
||||
lo_nbits_freq : integer := 24;
|
||||
cic_nstages : integer := 5;
|
||||
cic_ratio : integer := 25;
|
||||
cic_scale_nbits : integer := 22
|
||||
);
|
||||
PORT
|
||||
(
|
||||
rst : in std_logic;
|
||||
|
||||
adc_clk : in std_logic;
|
||||
adc_da : in signed(15 downto 0);
|
||||
adc_ofa : in std_logic;
|
||||
adc_rand : out std_logic;
|
||||
adc_pga : out std_logic;
|
||||
adc_dith : out std_logic;
|
||||
adc_shdn : out std_logic;
|
||||
|
||||
usb_usbclk : in std_logic;
|
||||
usb_ifclk : in std_logic;
|
||||
usb_fd : out signed(15 downto 0);
|
||||
usb_pktend : out std_logic;
|
||||
usb_fifoadr : out unsigned(1 downto 0);
|
||||
usb_slcs_n : out std_logic;
|
||||
usb_slwr_n : out std_logic;
|
||||
usb_slrd_n : out std_logic;
|
||||
usb_sloe : out std_logic;
|
||||
usb_flaga : in std_logic;
|
||||
usb_flagb : in std_logic;
|
||||
usb_flagc : in std_logic;
|
||||
|
||||
cl_clk_out : out std_logic;
|
||||
cl_dout : out unsigned(23 downto 0);
|
||||
cl_pat_sel : out std_logic;
|
||||
cl_prbs_en : out std_logic;
|
||||
cl_ds_opt : out std_logic;
|
||||
cl_bal : out std_logic;
|
||||
cl_pd_n : out std_logic;
|
||||
cl_tsen : in std_logic;
|
||||
|
||||
reg_aen : in std_logic;
|
||||
reg_dio : inout unsigned(7 downto 0);
|
||||
reg_oe : in std_logic;
|
||||
reg_we : in std_logic
|
||||
|
||||
);
|
||||
END syn_ddc;
|
||||
|
||||
ARCHITECTURE behavior OF syn_ddc IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT ddc
|
||||
GENERIC
|
||||
(
|
||||
nbits_in : integer;
|
||||
nbits_in_frac : integer;
|
||||
nbits_out : integer;
|
||||
nbits_out_frac : integer;
|
||||
lo_nbits_phase : integer;
|
||||
lo_nbits_freq : integer;
|
||||
cic_nstages : integer;
|
||||
cic_ratio : integer;
|
||||
cic_scale_nbits : integer
|
||||
);
|
||||
PORT
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
lo_nco_rst : in std_logic;
|
||||
lo_nco_en : in std_logic;
|
||||
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
|
||||
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
|
||||
din_vld : in std_logic;
|
||||
din_i : in sfixed;
|
||||
din_q : in sfixed;
|
||||
dec_vld : out std_logic;
|
||||
dec_i : out sfixed;
|
||||
dec_q : out sfixed;
|
||||
dout_vld : out std_logic;
|
||||
dout_i : out sfixed;
|
||||
dout_q : out sfixed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Outputs
|
||||
SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
|
||||
SIGNAL ddc_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
|
||||
SIGNAL ddc_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
|
||||
SIGNAL ddc_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
|
||||
|
||||
SIGNAL dec_vld : std_logic;
|
||||
SIGNAL ddc_dec_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
|
||||
SIGNAL ddc_dec_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
|
||||
|
||||
|
||||
SIGNAL reg_lo_nco_rst : std_logic;
|
||||
SIGNAL reg_lo_nco_en : std_logic;
|
||||
SIGNAL reg_lo_freq_in : unsigned(31 downto 0);
|
||||
SIGNAL reg_lo_phase_in : unsigned(31 downto 0);
|
||||
|
||||
SIGNAL reg_en_addr : std_logic;
|
||||
SIGNAL reg_en_data : std_logic;
|
||||
SIGNAL reg_addr_last : std_logic;
|
||||
SIGNAL reg_data_last : std_logic;
|
||||
SIGNAL reg_addr_async : unsigned (7 downto 0);
|
||||
SIGNAL reg_data_async : unsigned (7 downto 0);
|
||||
SIGNAL reg_addr : unsigned (7 downto 0);
|
||||
SIGNAL reg_data : unsigned (7 downto 0);
|
||||
|
||||
SIGNAL fifo_usb_we : std_logic;
|
||||
SIGNAL fifo_usb_re : std_logic;
|
||||
SIGNAL fifo_usb_ff : std_logic;
|
||||
SIGNAL fifo_usb_ef : std_logic;
|
||||
SIGNAL fifo_usb_aff : std_logic;
|
||||
SIGNAL fifo_usb_aef : std_logic;
|
||||
|
||||
type fifo_usb_array_t is array (0 to 3) of unsigned (15 downto 0);
|
||||
SIGNAL fifo_usb_in : fifo_usb_array_t;
|
||||
SIGNAL fifo_usb_out : unsigned (15 downto 0);
|
||||
|
||||
SIGNAL fifo_usb_we_pipe : unsigned(3 downto 0);
|
||||
SIGNAL enable : std_logic;
|
||||
SIGNAL ddc_din_vld : std_logic;
|
||||
SIGNAL ddc_dout_vld : std_logic;
|
||||
|
||||
SIGNAL cl_we_pipe : unsigned(1 downto 0);
|
||||
type cl_data_array_t is array (0 to 1) of unsigned (31 downto 0);
|
||||
SIGNAL cl_sd_data : cl_data_array_t;
|
||||
|
||||
SIGNAL cl_dout_L : std_logic_vector(24 downto 0);
|
||||
SIGNAL cl_dout_H : std_logic_vector(24 downto 0);
|
||||
SIGNAL cl_dout_clk : std_logic_vector(24 downto 0);
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
inst_ddc : ddc
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_in => nbits_in,
|
||||
nbits_in_frac => nbits_in_frac,
|
||||
nbits_out => nbits_out,
|
||||
nbits_out_frac => nbits_out_frac,
|
||||
lo_nbits_phase => lo_nbits_phase,
|
||||
lo_nbits_freq => lo_nbits_freq,
|
||||
cic_nstages => cic_nstages,
|
||||
cic_ratio => cic_ratio,
|
||||
cic_scale_nbits => cic_scale_nbits
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => adc_clk,
|
||||
lo_nco_rst => reg_lo_nco_rst,
|
||||
lo_nco_en => reg_lo_nco_en,
|
||||
lo_freq_in => reg_lo_freq_in(lo_nbits_freq-1 downto 0),
|
||||
lo_phase_in => reg_lo_phase_in(lo_nbits_phase-1 downto 0),
|
||||
din_vld => ddc_din_vld,
|
||||
din_i => ddc_din_i,
|
||||
din_q => ddc_din_q,
|
||||
dec_vld => dec_vld,
|
||||
dec_i => ddc_dec_i,
|
||||
dec_q => ddc_dec_q,
|
||||
dout_vld => ddc_dout_vld,
|
||||
dout_i => ddc_dout_i,
|
||||
dout_q => ddc_dout_q
|
||||
);
|
||||
|
||||
reg_dio <= reg_addr when reg_oe = '1' else (others => 'Z');
|
||||
|
||||
----------------------------------------------------------
|
||||
-- Register control
|
||||
----------------------------------------------------------
|
||||
proc_reg_da_async:
|
||||
process(reg_we)
|
||||
begin
|
||||
if rising_edge(reg_we) then
|
||||
if reg_aen = '1' then
|
||||
reg_addr_async <= reg_dio;
|
||||
else
|
||||
reg_data_async <= reg_dio;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_reg_da_sync:
|
||||
process(adc_clk)
|
||||
-- process(usb_usbclk)
|
||||
begin
|
||||
if rising_edge(adc_clk) then
|
||||
-- if rising_edge(usb_usbclk) then
|
||||
if rst = '1' then
|
||||
reg_en_addr <= '0';
|
||||
reg_en_data <= '0';
|
||||
reg_addr_last <= '0';
|
||||
reg_data_last <= '0';
|
||||
elsif reg_we = '1' then
|
||||
reg_en_addr <= reg_aen and not reg_addr_last;
|
||||
reg_en_data <= not (reg_aen or reg_data_last);
|
||||
reg_addr_last <= reg_aen;
|
||||
reg_data_last <= not reg_aen;
|
||||
else
|
||||
reg_addr_last <= '0';
|
||||
reg_data_last <= '0';
|
||||
end if;
|
||||
reg_data <= reg_data_async;
|
||||
reg_addr <= reg_addr_async;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Registers
|
||||
proc_register_write:
|
||||
process(adc_clk)
|
||||
-- process(usb_usbclk)
|
||||
begin
|
||||
if rising_edge(adc_clk) then
|
||||
-- if rising_edge(usb_usbclk) then
|
||||
if rst = '1' then
|
||||
reg_lo_nco_rst <= '0';
|
||||
reg_lo_nco_en <= '0';
|
||||
elsif reg_en_data = '1' then
|
||||
case reg_addr is
|
||||
when X"00" => -- Control
|
||||
reg_lo_nco_rst <= reg_data(0);
|
||||
reg_lo_nco_en <= reg_data(1);
|
||||
|
||||
when X"10" => -- freqency
|
||||
reg_lo_freq_in(7 downto 0) <= reg_data;
|
||||
|
||||
when X"11" => -- freqency
|
||||
reg_lo_freq_in(15 downto 8) <= reg_data;
|
||||
|
||||
when X"12" => -- freqency
|
||||
reg_lo_freq_in(23 downto 16) <= reg_data;
|
||||
|
||||
when X"13" => -- freqency
|
||||
reg_lo_freq_in(31 downto 24) <= reg_data;
|
||||
|
||||
when X"20" => -- phase
|
||||
reg_lo_phase_in(7 downto 0) <= reg_data;
|
||||
|
||||
when X"21" => -- phase
|
||||
reg_lo_phase_in(15 downto 8) <= reg_data;
|
||||
|
||||
when X"22" => -- phase
|
||||
reg_lo_phase_in(23 downto 16) <= reg_data;
|
||||
|
||||
when X"23" => -- phase
|
||||
reg_lo_phase_in(31 downto 24) <= reg_data;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
----------------------------------------------------------
|
||||
-- DDC input
|
||||
----------------------------------------------------------
|
||||
proc_adc_input_register:
|
||||
process(adc_clk)
|
||||
begin
|
||||
if rising_edge(adc_clk) then
|
||||
ddc_din_vld <= enable;
|
||||
if enable = '1' then
|
||||
ddc_din_i <= sfixed(resize(adc_da, nbits_in));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ddc_din_q <= to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
|
||||
|
||||
enable <= '1';
|
||||
adc_rand <= '0';
|
||||
adc_pga <= '0';
|
||||
adc_dith <= '0';
|
||||
adc_shdn <= not enable;
|
||||
|
||||
----------------------------------------------------------
|
||||
-- USB FIFO output
|
||||
----------------------------------------------------------
|
||||
proc_usb_interleave_iq:
|
||||
process(adc_clk)
|
||||
variable i, q : unsigned(31 downto 0);
|
||||
begin
|
||||
if rising_edge(adc_clk) then
|
||||
if rst = '1' then
|
||||
fifo_usb_we_pipe <= (others => '0');
|
||||
elsif ddc_dout_vld = '1' then
|
||||
fifo_usb_we_pipe <= (others => '1');
|
||||
i := unsigned(ddc_dout_i);
|
||||
q := unsigned(ddc_dout_q);
|
||||
fifo_usb_in(0) <= i(15 downto 0);
|
||||
fifo_usb_in(1) <= i(31 downto 16);
|
||||
fifo_usb_in(2) <= q(15 downto 0);
|
||||
fifo_usb_in(3) <= q(31 downto 16);
|
||||
elsif fifo_usb_ff = '0' then
|
||||
fifo_usb_we_pipe <= fifo_usb_we_pipe(fifo_usb_we_pipe'left-1 downto 0) & '0';
|
||||
fifo_usb_in(0) <= fifo_usb_in(1);
|
||||
fifo_usb_in(1) <= fifo_usb_in(2);
|
||||
fifo_usb_in(2) <= fifo_usb_in(3);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_usbfifo: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 7,
|
||||
data_width => 16,
|
||||
almost_full_thresh => 96,
|
||||
almost_empty_thresh => 32
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_w => adc_clk,
|
||||
clk_r => usb_ifclk,
|
||||
we => fifo_usb_we,
|
||||
re => fifo_usb_re,
|
||||
data_w => fifo_usb_in(0),
|
||||
data_r => fifo_usb_out,
|
||||
fifo_full => fifo_usb_ff,
|
||||
fifo_empty => fifo_usb_ef,
|
||||
fifo_afull => fifo_usb_aff,
|
||||
fifo_aempty => fifo_usb_aef
|
||||
|
||||
);
|
||||
|
||||
fifo_usb_we <= fifo_usb_we_pipe(fifo_usb_we_pipe'left);
|
||||
usb_fd <= signed(fifo_usb_out);
|
||||
fifo_usb_re <= usb_flaga;
|
||||
usb_slcs_n <= '0';
|
||||
usb_slwr_n <= not usb_flaga;
|
||||
usb_slrd_n <= '1';
|
||||
usb_sloe <= '0';
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
-- Channel-Link DDR output
|
||||
----------------------------------------------------------
|
||||
proc_cl_interleave_iq:
|
||||
process(adc_clk)
|
||||
variable i, q : unsigned(31 downto 0);
|
||||
begin
|
||||
if rising_edge(adc_clk) then
|
||||
if rst = '1' then
|
||||
cl_we_pipe <= (others => '0');
|
||||
elsif ddc_dout_vld = '1' then
|
||||
cl_we_pipe <= (others => '1');
|
||||
i := unsigned(ddc_dout_i);
|
||||
q := unsigned(ddc_dout_q);
|
||||
cl_sd_data(0) <= i;
|
||||
cl_sd_data(1) <= q;
|
||||
else
|
||||
cl_we_pipe <= cl_we_pipe(cl_we_pipe'left-1 downto 0) & '0';
|
||||
cl_sd_data(0) <= cl_sd_data(1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_cl_ddr_out: entity work.cl_ddr_out
|
||||
PORT MAP
|
||||
(
|
||||
aclr => rst,
|
||||
datain_h => cl_dout_H,
|
||||
datain_l => cl_dout_L,
|
||||
outclock => adc_clk,
|
||||
outclocken => '1',
|
||||
dataout => cl_dout_clk
|
||||
);
|
||||
|
||||
cl_dout_H <= '0' & cl_we_pipe(cl_we_pipe'left) & "0000000" & std_logic_vector(cl_sd_data(0)(31 downto 16));
|
||||
cl_dout_L <= '1' & cl_we_pipe(cl_we_pipe'left) & "0000000" & std_logic_vector(cl_sd_data(0)(15 downto 0));
|
||||
cl_dout <= unsigned(cl_dout_clk(23 downto 0));
|
||||
cl_clk_out <= cl_dout_clk(24);
|
||||
cl_pat_sel <= '0';
|
||||
cl_prbs_en <= '0';
|
||||
cl_ds_opt <= '0';
|
||||
cl_bal <= '0';
|
||||
cl_pd_n <= '1';
|
||||
|
||||
----------------------------------------------------------
|
||||
END;
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_nco
|
||||
-- Module Name: tb_nco.vhd
|
||||
-- Project Name: nco
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library ieee_proposed;
|
||||
use ieee_proposed.math_utility_pkg.all;
|
||||
use ieee_proposed.fixed_pkg.all;
|
||||
|
||||
--library altera;
|
||||
--use altera.altera_syn_attributes.all;
|
||||
|
||||
library work;
|
||||
use work.fixed_util_pkg.all;
|
||||
|
||||
ENTITY syn_ddc IS
|
||||
Generic
|
||||
(
|
||||
nbits_in : integer := 16;
|
||||
nbits_in_frac : integer := 14;
|
||||
nbits_out : integer := 32;
|
||||
nbits_out_frac : integer := 30;
|
||||
lo_nbits_phase : integer := 24;
|
||||
lo_nbits_freq : integer := 24;
|
||||
cic_nstages : integer := 5;
|
||||
cic_ratio : integer := 25;
|
||||
cic_scale_nbits : integer := 22
|
||||
);
|
||||
PORT
|
||||
(
|
||||
rst : in std_logic;
|
||||
|
||||
adc_clk : in std_logic;
|
||||
adc_da : in signed(15 downto 0);
|
||||
adc_ofa : in std_logic;
|
||||
adc_rand : out std_logic;
|
||||
adc_pga : out std_logic;
|
||||
adc_dith : out std_logic;
|
||||
adc_shdn : out std_logic;
|
||||
|
||||
usb_usbclk : in std_logic;
|
||||
usb_ifclk : in std_logic;
|
||||
usb_fd : out signed(15 downto 0);
|
||||
usb_pktend : out std_logic;
|
||||
usb_fifoadr : out unsigned(1 downto 0);
|
||||
usb_slcs_n : out std_logic;
|
||||
usb_slwr_n : out std_logic;
|
||||
usb_slrd_n : out std_logic;
|
||||
usb_sloe : out std_logic;
|
||||
usb_flaga : in std_logic;
|
||||
usb_flagb : in std_logic;
|
||||
usb_flagc : in std_logic;
|
||||
|
||||
cl_clk_out : out std_logic;
|
||||
cl_dout : out unsigned(20 downto 0);
|
||||
cl_pd_n : out std_logic;
|
||||
|
||||
reg_aen : in std_logic;
|
||||
reg_dio : inout unsigned(7 downto 0);
|
||||
reg_oe : in std_logic;
|
||||
reg_we : in std_logic
|
||||
|
||||
);
|
||||
END syn_ddc;
|
||||
|
||||
ARCHITECTURE behavior OF syn_ddc IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT ddc
|
||||
GENERIC
|
||||
(
|
||||
nbits_in : integer;
|
||||
nbits_in_frac : integer;
|
||||
nbits_out : integer;
|
||||
nbits_out_frac : integer;
|
||||
lo_nbits_phase : integer;
|
||||
lo_nbits_freq : integer;
|
||||
cic_nstages : integer;
|
||||
cic_ratio : integer;
|
||||
cic_scale_nbits : integer
|
||||
);
|
||||
PORT
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
lo_nco_rst : in std_logic;
|
||||
lo_nco_en : in std_logic;
|
||||
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
|
||||
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
|
||||
din_vld : in std_logic;
|
||||
din_i : in sfixed;
|
||||
din_q : in sfixed;
|
||||
dec_vld : out std_logic;
|
||||
dec_i : out sfixed;
|
||||
dec_q : out sfixed;
|
||||
dout_vld : out std_logic;
|
||||
dout_i : out sfixed;
|
||||
dout_q : out sfixed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Outputs
|
||||
SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
|
||||
SIGNAL ddc_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
|
||||
SIGNAL ddc_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
|
||||
SIGNAL ddc_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
|
||||
|
||||
SIGNAL dec_vld : std_logic;
|
||||
SIGNAL ddc_dec_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
|
||||
SIGNAL ddc_dec_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
|
||||
|
||||
|
||||
SIGNAL reg_lo_nco_rst : std_logic;
|
||||
SIGNAL reg_lo_nco_en : std_logic;
|
||||
SIGNAL reg_lo_freq_in : unsigned(31 downto 0);
|
||||
SIGNAL reg_lo_phase_in : unsigned(31 downto 0);
|
||||
|
||||
SIGNAL reg_en_addr : std_logic;
|
||||
SIGNAL reg_en_data : std_logic;
|
||||
SIGNAL reg_addr_last : std_logic;
|
||||
SIGNAL reg_data_last : std_logic;
|
||||
SIGNAL reg_addr_async : unsigned (7 downto 0);
|
||||
SIGNAL reg_data_async : unsigned (7 downto 0);
|
||||
SIGNAL reg_addr : unsigned (7 downto 0);
|
||||
SIGNAL reg_data : unsigned (7 downto 0);
|
||||
|
||||
SIGNAL fifo_usb_we : std_logic;
|
||||
SIGNAL fifo_usb_re : std_logic;
|
||||
SIGNAL fifo_usb_ff : std_logic;
|
||||
SIGNAL fifo_usb_ef : std_logic;
|
||||
SIGNAL fifo_usb_aff : std_logic;
|
||||
SIGNAL fifo_usb_aef : std_logic;
|
||||
|
||||
type fifo_usb_array_t is array (0 to 3) of unsigned (15 downto 0);
|
||||
SIGNAL fifo_usb_in : fifo_usb_array_t;
|
||||
SIGNAL fifo_usb_out : unsigned (15 downto 0);
|
||||
|
||||
SIGNAL cl_clk : std_logic;
|
||||
SIGNAL fifo_cl_we : std_logic;
|
||||
SIGNAL fifo_cl_re : std_logic;
|
||||
SIGNAL fifo_cl_ff : std_logic;
|
||||
SIGNAL fifo_cl_ef : std_logic;
|
||||
SIGNAL fifo_cl_aff : std_logic;
|
||||
SIGNAL fifo_cl_aef : std_logic;
|
||||
|
||||
SIGNAL fifo_cl_in : unsigned (63 downto 0);
|
||||
SIGNAL fifo_cl_out : unsigned (63 downto 0);
|
||||
|
||||
SIGNAL fifo_usb_we_pipe : unsigned(3 downto 0);
|
||||
SIGNAL enable : std_logic;
|
||||
SIGNAL ddc_din_vld : std_logic;
|
||||
SIGNAL ddc_dout_vld : std_logic;
|
||||
|
||||
SIGNAL cl_rst_pipe : unsigned (63 downto 0);
|
||||
SIGNAL cl_rst : std_logic;
|
||||
SIGNAL cl_phase : unsigned(1 downto 0);
|
||||
SIGNAL cl_data : unsigned(20 downto 0);
|
||||
subtype cl_clkgen_cnt_t is natural range 0 to (2*cic_ratio/2/5)-1;
|
||||
SIGNAL cl_clkgen_cnt : cl_clkgen_cnt_t;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
inst_ddc : ddc
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_in => nbits_in,
|
||||
nbits_in_frac => nbits_in_frac,
|
||||
nbits_out => nbits_out,
|
||||
nbits_out_frac => nbits_out_frac,
|
||||
lo_nbits_phase => lo_nbits_phase,
|
||||
lo_nbits_freq => lo_nbits_freq,
|
||||
cic_nstages => cic_nstages,
|
||||
cic_ratio => cic_ratio,
|
||||
cic_scale_nbits => cic_scale_nbits
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => adc_clk,
|
||||
lo_nco_rst => reg_lo_nco_rst,
|
||||
lo_nco_en => reg_lo_nco_en,
|
||||
lo_freq_in => reg_lo_freq_in(lo_nbits_freq-1 downto 0),
|
||||
lo_phase_in => reg_lo_phase_in(lo_nbits_phase-1 downto 0),
|
||||
din_vld => ddc_din_vld,
|
||||
din_i => ddc_din_i,
|
||||
din_q => ddc_din_q,
|
||||
dec_vld => dec_vld,
|
||||
dec_i => ddc_dec_i,
|
||||
dec_q => ddc_dec_q,
|
||||
dout_vld => ddc_dout_vld,
|
||||
dout_i => ddc_dout_i,
|
||||
dout_q => ddc_dout_q
|
||||
);
|
||||
|
||||
reg_dio <= reg_addr when reg_oe = '1' else (others => 'Z');
|
||||
|
||||
----------------------------------------------------------
|
||||
-- Register control
|
||||
----------------------------------------------------------
|
||||
proc_reg_da_async:
|
||||
process(reg_we)
|
||||
begin
|
||||
if rising_edge(reg_we) then
|
||||
if reg_aen = '1' then
|
||||
reg_addr_async <= reg_dio;
|
||||
else
|
||||
reg_data_async <= reg_dio;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_reg_da_sync:
|
||||
process(adc_clk)
|
||||
-- process(usb_usbclk)
|
||||
begin
|
||||
if rising_edge(adc_clk) then
|
||||
-- if rising_edge(usb_usbclk) then
|
||||
if rst = '1' then
|
||||
reg_en_addr <= '0';
|
||||
reg_en_data <= '0';
|
||||
reg_addr_last <= '0';
|
||||
reg_data_last <= '0';
|
||||
elsif reg_we = '1' then
|
||||
reg_en_addr <= reg_aen and not reg_addr_last;
|
||||
reg_en_data <= not (reg_aen or reg_data_last);
|
||||
reg_addr_last <= reg_aen;
|
||||
reg_data_last <= not reg_aen;
|
||||
else
|
||||
reg_addr_last <= '0';
|
||||
reg_data_last <= '0';
|
||||
end if;
|
||||
reg_data <= reg_data_async;
|
||||
reg_addr <= reg_addr_async;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Registers
|
||||
proc_register_write:
|
||||
process(adc_clk)
|
||||
-- process(usb_usbclk)
|
||||
begin
|
||||
if rising_edge(adc_clk) then
|
||||
-- if rising_edge(usb_usbclk) then
|
||||
if rst = '1' then
|
||||
reg_lo_nco_rst <= '1';
|
||||
reg_lo_nco_en <= '0';
|
||||
elsif reg_en_data = '1' then
|
||||
case reg_addr is
|
||||
when X"00" => -- Control
|
||||
reg_lo_nco_rst <= reg_data(0);
|
||||
reg_lo_nco_en <= reg_data(1);
|
||||
|
||||
when X"10" => -- freqency
|
||||
reg_lo_freq_in(7 downto 0) <= reg_data;
|
||||
|
||||
when X"11" => -- freqency
|
||||
reg_lo_freq_in(15 downto 8) <= reg_data;
|
||||
|
||||
when X"12" => -- freqency
|
||||
reg_lo_freq_in(23 downto 16) <= reg_data;
|
||||
|
||||
when X"13" => -- freqency
|
||||
reg_lo_freq_in(31 downto 24) <= reg_data;
|
||||
|
||||
when X"20" => -- phase
|
||||
reg_lo_phase_in(7 downto 0) <= reg_data;
|
||||
|
||||
when X"21" => -- phase
|
||||
reg_lo_phase_in(15 downto 8) <= reg_data;
|
||||
|
||||
when X"22" => -- phase
|
||||
reg_lo_phase_in(23 downto 16) <= reg_data;
|
||||
|
||||
when X"23" => -- phase
|
||||
reg_lo_phase_in(31 downto 24) <= reg_data;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
----------------------------------------------------------
|
||||
-- DDC input
|
||||
----------------------------------------------------------
|
||||
proc_adc_input_register:
|
||||
process(adc_clk)
|
||||
begin
|
||||
if rising_edge(adc_clk) then
|
||||
ddc_din_i <= sfixed(resize(adc_da, nbits_in));
|
||||
ddc_din_vld <= reg_lo_nco_en;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ddc_din_q <= to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
|
||||
|
||||
adc_rand <= '0';
|
||||
adc_pga <= '0';
|
||||
adc_dith <= '0';
|
||||
adc_shdn <= not reg_lo_nco_en;
|
||||
|
||||
----------------------------------------------------------
|
||||
-- USB FIFO output
|
||||
----------------------------------------------------------
|
||||
proc_usb_interleave_iq:
|
||||
process(adc_clk)
|
||||
variable i, q : unsigned(31 downto 0);
|
||||
begin
|
||||
if rising_edge(adc_clk) then
|
||||
if rst = '1' then
|
||||
fifo_usb_we_pipe <= (others => '0');
|
||||
elsif ddc_dout_vld = '1' then
|
||||
fifo_usb_we_pipe <= (others => '1');
|
||||
i := to_unsigned(ufixed(ddc_dout_i));
|
||||
q := to_unsigned(ufixed(ddc_dout_q));
|
||||
fifo_usb_in(0) <= i(15 downto 0);
|
||||
fifo_usb_in(1) <= i(31 downto 16);
|
||||
fifo_usb_in(2) <= q(15 downto 0);
|
||||
fifo_usb_in(3) <= q(31 downto 16);
|
||||
elsif fifo_usb_ff = '0' then
|
||||
fifo_usb_we_pipe <= fifo_usb_we_pipe(fifo_usb_we_pipe'left-1 downto 0) & '0';
|
||||
fifo_usb_in(0) <= fifo_usb_in(1);
|
||||
fifo_usb_in(1) <= fifo_usb_in(2);
|
||||
fifo_usb_in(2) <= fifo_usb_in(3);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_usbfifo: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 7,
|
||||
data_width => 16,
|
||||
almost_full_thresh => 96,
|
||||
almost_empty_thresh => 32
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_w => adc_clk,
|
||||
clk_r => usb_ifclk,
|
||||
we => fifo_usb_we,
|
||||
re => fifo_usb_re,
|
||||
data_w => fifo_usb_in(0),
|
||||
data_r => fifo_usb_out,
|
||||
fifo_full => fifo_usb_ff,
|
||||
fifo_empty => fifo_usb_ef,
|
||||
fifo_afull => fifo_usb_aff,
|
||||
fifo_aempty => fifo_usb_aef
|
||||
|
||||
);
|
||||
|
||||
fifo_usb_we <= fifo_usb_we_pipe(fifo_usb_we_pipe'left);
|
||||
usb_fd <= signed(fifo_usb_out);
|
||||
fifo_usb_re <= usb_flaga;
|
||||
usb_slcs_n <= '0';
|
||||
usb_slwr_n <= not usb_flaga;
|
||||
usb_slrd_n <= '1';
|
||||
usb_sloe <= '0';
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
-- Channel-Link output
|
||||
----------------------------------------------------------
|
||||
inst_cl_fifo: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 4,
|
||||
data_width => 64,
|
||||
almost_full_thresh => 96,
|
||||
almost_empty_thresh => 32
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_w => adc_clk,
|
||||
clk_r => cl_clk,
|
||||
we => fifo_cl_we,
|
||||
re => fifo_cl_re,
|
||||
data_w => fifo_cl_in,
|
||||
data_r => fifo_cl_out,
|
||||
fifo_full => fifo_cl_ff,
|
||||
fifo_empty => fifo_cl_ef,
|
||||
fifo_afull => fifo_cl_aff,
|
||||
fifo_aempty => fifo_cl_aef
|
||||
|
||||
);
|
||||
|
||||
fifo_cl_in <= to_unsigned(ufixed(ddc_dout_i)) & to_unsigned(ufixed(ddc_dout_i));
|
||||
fifo_cl_we <= ddc_dout_vld;
|
||||
fifo_cl_re <= '1';
|
||||
|
||||
proc_cl_clkgen:
|
||||
process(adc_clk)
|
||||
begin
|
||||
if rising_edge(adc_clk) then
|
||||
if rst = '1' then
|
||||
cl_rst_pipe <= (others => '1');
|
||||
cl_clkgen_cnt <= cl_clkgen_cnt_t'high;
|
||||
cl_clk <= '0';
|
||||
else
|
||||
if cl_clkgen_cnt = 0 then
|
||||
cl_clkgen_cnt <= cl_clkgen_cnt_t'high;
|
||||
cl_clk <= not cl_clk;
|
||||
cl_rst_pipe <= cl_rst_pipe(cl_rst_pipe'left-1 downto 0) & '0';
|
||||
else
|
||||
cl_clkgen_cnt <= cl_clkgen_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cl_rst <= cl_rst_pipe(cl_rst_pipe'left);
|
||||
|
||||
proc_cl_interleave_iq:
|
||||
process(cl_clk)
|
||||
variable i, q : unsigned(31 downto 0);
|
||||
begin
|
||||
if rising_edge(cl_clk) then
|
||||
if cl_rst = '1' then
|
||||
cl_phase <= (others => '0');
|
||||
else
|
||||
i := fifo_cl_out(31 downto 0);
|
||||
q := fifo_cl_out(63 downto 32);
|
||||
if cl_phase(1) = '0' then
|
||||
if cl_phase(0) = '0' then
|
||||
cl_data <= not fifo_cl_ef & cl_phase & "00" & i(15 downto 0);
|
||||
else
|
||||
cl_data <= not fifo_cl_ef & cl_phase & "00" & i(31 downto 16);
|
||||
end if;
|
||||
else
|
||||
if cl_phase(0) = '0' then
|
||||
cl_data <= not fifo_cl_ef & cl_phase & "00" & q(15 downto 0);
|
||||
else
|
||||
cl_data <= not fifo_cl_ef & cl_phase & "00" & q(31 downto 16);
|
||||
end if;
|
||||
end if;
|
||||
cl_phase <= cl_phase + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cl_dout <= cl_data;
|
||||
cl_clk_out <= cl_clk;
|
||||
cl_pd_n <= not cl_rst;
|
||||
|
||||
----------------------------------------------------------
|
||||
END;
|
||||
|
||||
@@ -1,82 +1,82 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r2c_ra is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r2c_ra;
|
||||
|
||||
architecture Behavioral of dpram_1w1r2c_ra is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r2c_ra is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r2c_ra;
|
||||
|
||||
architecture Behavioral of dpram_1w1r2c_ra is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,82 +1,82 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r2c_ra is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r2c_ra;
|
||||
|
||||
architecture Behavioral of dpram_1w1r2c_ra is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r2c_ra is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r2c_ra;
|
||||
|
||||
architecture Behavioral of dpram_1w1r2c_ra is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,80 +1,80 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered output
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r2c_ro is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r2c_ro;
|
||||
|
||||
architecture Behavioral of dpram_1w1r2c_ro is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered output
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r2c_ro is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r2c_ro;
|
||||
|
||||
architecture Behavioral of dpram_1w1r2c_ro is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,81 +1,81 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered output
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r2c_ro is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r2c_ro;
|
||||
|
||||
architecture Behavioral of dpram_1w1r2c_ro is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered output
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r2c_ro is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r2c_ro;
|
||||
|
||||
architecture Behavioral of dpram_1w1r2c_ro is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,95 +1,95 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r2c_ra is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r2c_ra;
|
||||
|
||||
architecture Behavioral of dpram_2w2r2c_ra is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
signal addr_a_r : unsigned (addr_width-1 downto 0);
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
dout_a <= RAM(to_integer(addr_a_r));
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a, clk_b)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' and en_a = '1' and we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
elsif clk_b'event and clk_b = '1' and en_b = '1' and we_b = '1' then
|
||||
RAM(to_integer(addr_b)) <= din_b;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
addr_a_r <= addr_a;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r2c_ra is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r2c_ra;
|
||||
|
||||
architecture Behavioral of dpram_2w2r2c_ra is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
signal addr_a_r : unsigned (addr_width-1 downto 0);
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
dout_a <= RAM(to_integer(addr_a_r));
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a, clk_b)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' and en_a = '1' and we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
elsif clk_b'event and clk_b = '1' and en_b = '1' and we_b = '1' then
|
||||
RAM(to_integer(addr_b)) <= din_b;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
addr_a_r <= addr_a;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,93 +1,93 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r2c_ra is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r2c_ra;
|
||||
|
||||
architecture Behavioral of dpram_2w2r2c_ra is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
signal addr_a_r : unsigned (addr_width-1 downto 0);
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
dout_a <= RAM(to_integer(addr_a_r));
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
addr_a_r <= addr_a;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r2c_ra is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r2c_ra;
|
||||
|
||||
architecture Behavioral of dpram_2w2r2c_ra is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
signal addr_a_r : unsigned (addr_width-1 downto 0);
|
||||
signal addr_b_r : unsigned (addr_width-1 downto 0);
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
dout_a <= RAM(to_integer(addr_a_r));
|
||||
dout_b <= RAM(to_integer(addr_b_r));
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
addr_a_r <= addr_a;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
addr_b_r <= addr_b;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,88 +1,88 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered output
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r2c_ro is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r2c_ro;
|
||||
|
||||
architecture Behavioral of dpram_2w2r2c_ro is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
dout_a <= RAM(to_integer(addr_a));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered output
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r2c_ro is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r2c_ro;
|
||||
|
||||
architecture Behavioral of dpram_2w2r2c_ro is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
dout_a <= RAM(to_integer(addr_a));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -1,88 +1,88 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered output
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r2c_ro is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r2c_ro;
|
||||
|
||||
architecture Behavioral of dpram_2w2r2c_ro is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
dout_a <= RAM(to_integer(addr_a));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: Dual-Port RAM with 1 clock latency for simulation
|
||||
-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered output
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r2c_ro is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r2c_ro;
|
||||
|
||||
architecture Behavioral of dpram_2w2r2c_ro is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
dout_a <= RAM(to_integer(addr_a));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user