From 70a8763f3b01bf4dee1514e67b6d806a402a3686 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Fri, 30 Jan 2009 21:18:46 +0000
Subject: [PATCH] Initial version Committed on the Free edition of March Hare
 Software CVSNT Server. Upgrade to CVS Suite for more features and support:
 http://march-hare.com/cvsnt/

git-svn-id: http://moon:8086/svn/vhdl/trunk@295 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/FIFO/src/dpram_1w1r.vhd | 77 +++++++++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 lib/FIFO/src/dpram_1w1r.vhd

diff --git a/lib/FIFO/src/dpram_1w1r.vhd b/lib/FIFO/src/dpram_1w1r.vhd
new file mode 100644
index 0000000..c63153e
--- /dev/null
+++ b/lib/FIFO/src/dpram_1w1r.vhd
@@ -0,0 +1,77 @@
+-------------------------------------------------------------------------
+-- Project: FIFO, generic FIFOs written in VHDL
+-- Release 1
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_1w1r is
+	Generic (
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w1r;
+
+architecture Behavioral of dpram_1w1r is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	
+begin
+
+process (clka)
+begin
+if clka'event and clka = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) <= din_a;
+		end if;
+	end if;
+end if;
+end process;
+
+process (clkb)
+begin
+if clkb'event and clkb = '1' then
+	if en_b = '1' then
+		dout_b <= RAM(to_integer(addr_b));
+	end if;
+end if;
+end process;
+
+
+end Behavioral;
+